linux/drivers/pinctrl/pinctrl-nomadik.c
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   1/*
   2 * Generic GPIO driver for logic cells found in the Nomadik SoC
   3 *
   4 * Copyright (C) 2008,2009 STMicroelectronics
   5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
   6 *   Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
   7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License version 2 as
  11 * published by the Free Software Foundation.
  12 */
  13#include <linux/kernel.h>
  14#include <linux/module.h>
  15#include <linux/init.h>
  16#include <linux/device.h>
  17#include <linux/platform_device.h>
  18#include <linux/io.h>
  19#include <linux/clk.h>
  20#include <linux/err.h>
  21#include <linux/gpio.h>
  22#include <linux/spinlock.h>
  23#include <linux/interrupt.h>
  24#include <linux/irq.h>
  25#include <linux/irqdomain.h>
  26#include <linux/irqchip/chained_irq.h>
  27#include <linux/slab.h>
  28#include <linux/of_device.h>
  29#include <linux/of_address.h>
  30#include <linux/pinctrl/machine.h>
  31#include <linux/pinctrl/pinctrl.h>
  32#include <linux/pinctrl/pinmux.h>
  33#include <linux/pinctrl/pinconf.h>
  34/* Since we request GPIOs from ourself */
  35#include <linux/pinctrl/consumer.h>
  36#include <linux/platform_data/pinctrl-nomadik.h>
  37#include "pinctrl-nomadik.h"
  38#include "core.h"
  39
  40/*
  41 * The GPIO module in the Nomadik family of Systems-on-Chip is an
  42 * AMBA device, managing 32 pins and alternate functions.  The logic block
  43 * is currently used in the Nomadik and ux500.
  44 *
  45 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
  46 */
  47
  48struct nmk_gpio_chip {
  49        struct gpio_chip chip;
  50        struct irq_domain *domain;
  51        void __iomem *addr;
  52        struct clk *clk;
  53        unsigned int bank;
  54        unsigned int parent_irq;
  55        int secondary_parent_irq;
  56        u32 (*get_secondary_status)(unsigned int bank);
  57        void (*set_ioforce)(bool enable);
  58        spinlock_t lock;
  59        bool sleepmode;
  60        /* Keep track of configured edges */
  61        u32 edge_rising;
  62        u32 edge_falling;
  63        u32 real_wake;
  64        u32 rwimsc;
  65        u32 fwimsc;
  66        u32 rimsc;
  67        u32 fimsc;
  68        u32 pull_up;
  69        u32 lowemi;
  70};
  71
  72/**
  73 * struct nmk_pinctrl - state container for the Nomadik pin controller
  74 * @dev: containing device pointer
  75 * @pctl: corresponding pin controller device
  76 * @soc: SoC data for this specific chip
  77 * @prcm_base: PRCM register range virtual base
  78 */
  79struct nmk_pinctrl {
  80        struct device *dev;
  81        struct pinctrl_dev *pctl;
  82        const struct nmk_pinctrl_soc_data *soc;
  83        void __iomem *prcm_base;
  84};
  85
  86static struct nmk_gpio_chip *
  87nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
  88
  89static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
  90
  91#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
  92
  93static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
  94                                unsigned offset, int gpio_mode)
  95{
  96        u32 bit = 1 << offset;
  97        u32 afunc, bfunc;
  98
  99        afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
 100        bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
 101        if (gpio_mode & NMK_GPIO_ALT_A)
 102                afunc |= bit;
 103        if (gpio_mode & NMK_GPIO_ALT_B)
 104                bfunc |= bit;
 105        writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
 106        writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
 107}
 108
 109static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
 110                                unsigned offset, enum nmk_gpio_slpm mode)
 111{
 112        u32 bit = 1 << offset;
 113        u32 slpm;
 114
 115        slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
 116        if (mode == NMK_GPIO_SLPM_NOCHANGE)
 117                slpm |= bit;
 118        else
 119                slpm &= ~bit;
 120        writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
 121}
 122
 123static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
 124                                unsigned offset, enum nmk_gpio_pull pull)
 125{
 126        u32 bit = 1 << offset;
 127        u32 pdis;
 128
 129        pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
 130        if (pull == NMK_GPIO_PULL_NONE) {
 131                pdis |= bit;
 132                nmk_chip->pull_up &= ~bit;
 133        } else {
 134                pdis &= ~bit;
 135        }
 136
 137        writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
 138
 139        if (pull == NMK_GPIO_PULL_UP) {
 140                nmk_chip->pull_up |= bit;
 141                writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
 142        } else if (pull == NMK_GPIO_PULL_DOWN) {
 143                nmk_chip->pull_up &= ~bit;
 144                writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
 145        }
 146}
 147
 148static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
 149                                  unsigned offset, bool lowemi)
 150{
 151        u32 bit = BIT(offset);
 152        bool enabled = nmk_chip->lowemi & bit;
 153
 154        if (lowemi == enabled)
 155                return;
 156
 157        if (lowemi)
 158                nmk_chip->lowemi |= bit;
 159        else
 160                nmk_chip->lowemi &= ~bit;
 161
 162        writel_relaxed(nmk_chip->lowemi,
 163                       nmk_chip->addr + NMK_GPIO_LOWEMI);
 164}
 165
 166static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
 167                                  unsigned offset)
 168{
 169        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
 170}
 171
 172static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
 173                                  unsigned offset, int val)
 174{
 175        if (val)
 176                writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
 177        else
 178                writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
 179}
 180
 181static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
 182                                  unsigned offset, int val)
 183{
 184        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
 185        __nmk_gpio_set_output(nmk_chip, offset, val);
 186}
 187
 188static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
 189                                     unsigned offset, int gpio_mode,
 190                                     bool glitch)
 191{
 192        u32 rwimsc = nmk_chip->rwimsc;
 193        u32 fwimsc = nmk_chip->fwimsc;
 194
 195        if (glitch && nmk_chip->set_ioforce) {
 196                u32 bit = BIT(offset);
 197
 198                /* Prevent spurious wakeups */
 199                writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
 200                writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
 201
 202                nmk_chip->set_ioforce(true);
 203        }
 204
 205        __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
 206
 207        if (glitch && nmk_chip->set_ioforce) {
 208                nmk_chip->set_ioforce(false);
 209
 210                writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
 211                writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
 212        }
 213}
 214
 215static void
 216nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
 217{
 218        u32 falling = nmk_chip->fimsc & BIT(offset);
 219        u32 rising = nmk_chip->rimsc & BIT(offset);
 220        int gpio = nmk_chip->chip.base + offset;
 221        int irq = irq_find_mapping(nmk_chip->domain, offset);
 222        struct irq_data *d = irq_get_irq_data(irq);
 223
 224        if (!rising && !falling)
 225                return;
 226
 227        if (!d || !irqd_irq_disabled(d))
 228                return;
 229
 230        if (rising) {
 231                nmk_chip->rimsc &= ~BIT(offset);
 232                writel_relaxed(nmk_chip->rimsc,
 233                               nmk_chip->addr + NMK_GPIO_RIMSC);
 234        }
 235
 236        if (falling) {
 237                nmk_chip->fimsc &= ~BIT(offset);
 238                writel_relaxed(nmk_chip->fimsc,
 239                               nmk_chip->addr + NMK_GPIO_FIMSC);
 240        }
 241
 242        dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
 243}
 244
 245static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
 246{
 247        u32 val;
 248
 249        val = readl(reg);
 250        val = ((val & ~mask) | (value & mask));
 251        writel(val, reg);
 252}
 253
 254static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
 255        unsigned offset, unsigned alt_num)
 256{
 257        int i;
 258        u16 reg;
 259        u8 bit;
 260        u8 alt_index;
 261        const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
 262        const u16 *gpiocr_regs;
 263
 264        if (!npct->prcm_base)
 265                return;
 266
 267        if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
 268                dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
 269                        alt_num);
 270                return;
 271        }
 272
 273        for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
 274                if (npct->soc->altcx_pins[i].pin == offset)
 275                        break;
 276        }
 277        if (i == npct->soc->npins_altcx) {
 278                dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
 279                        offset);
 280                return;
 281        }
 282
 283        pin_desc = npct->soc->altcx_pins + i;
 284        gpiocr_regs = npct->soc->prcm_gpiocr_registers;
 285
 286        /*
 287         * If alt_num is NULL, just clear current ALTCx selection
 288         * to make sure we come back to a pure ALTC selection
 289         */
 290        if (!alt_num) {
 291                for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
 292                        if (pin_desc->altcx[i].used == true) {
 293                                reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
 294                                bit = pin_desc->altcx[i].control_bit;
 295                                if (readl(npct->prcm_base + reg) & BIT(bit)) {
 296                                        nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
 297                                        dev_dbg(npct->dev,
 298                                                "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
 299                                                offset, i+1);
 300                                }
 301                        }
 302                }
 303                return;
 304        }
 305
 306        alt_index = alt_num - 1;
 307        if (pin_desc->altcx[alt_index].used == false) {
 308                dev_warn(npct->dev,
 309                        "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
 310                        offset, alt_num);
 311                return;
 312        }
 313
 314        /*
 315         * Check if any other ALTCx functions are activated on this pin
 316         * and disable it first.
 317         */
 318        for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
 319                if (i == alt_index)
 320                        continue;
 321                if (pin_desc->altcx[i].used == true) {
 322                        reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
 323                        bit = pin_desc->altcx[i].control_bit;
 324                        if (readl(npct->prcm_base + reg) & BIT(bit)) {
 325                                nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
 326                                dev_dbg(npct->dev,
 327                                        "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
 328                                        offset, i+1);
 329                        }
 330                }
 331        }
 332
 333        reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
 334        bit = pin_desc->altcx[alt_index].control_bit;
 335        dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
 336                offset, alt_index+1);
 337        nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
 338}
 339
 340/*
 341 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
 342 *  - Save SLPM registers
 343 *  - Set SLPM=0 for the IOs you want to switch and others to 1
 344 *  - Configure the GPIO registers for the IOs that are being switched
 345 *  - Set IOFORCE=1
 346 *  - Modify the AFLSA/B registers for the IOs that are being switched
 347 *  - Set IOFORCE=0
 348 *  - Restore SLPM registers
 349 *  - Any spurious wake up event during switch sequence to be ignored and
 350 *    cleared
 351 */
 352static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
 353{
 354        int i;
 355
 356        for (i = 0; i < NUM_BANKS; i++) {
 357                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
 358                unsigned int temp = slpm[i];
 359
 360                if (!chip)
 361                        break;
 362
 363                clk_enable(chip->clk);
 364
 365                slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
 366                writel(temp, chip->addr + NMK_GPIO_SLPC);
 367        }
 368}
 369
 370static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
 371{
 372        int i;
 373
 374        for (i = 0; i < NUM_BANKS; i++) {
 375                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
 376
 377                if (!chip)
 378                        break;
 379
 380                writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
 381
 382                clk_disable(chip->clk);
 383        }
 384}
 385
 386static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
 387{
 388        int i;
 389        u16 reg;
 390        u8 bit;
 391        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
 392        const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
 393        const u16 *gpiocr_regs;
 394
 395        if (!npct->prcm_base)
 396                return NMK_GPIO_ALT_C;
 397
 398        for (i = 0; i < npct->soc->npins_altcx; i++) {
 399                if (npct->soc->altcx_pins[i].pin == gpio)
 400                        break;
 401        }
 402        if (i == npct->soc->npins_altcx)
 403                return NMK_GPIO_ALT_C;
 404
 405        pin_desc = npct->soc->altcx_pins + i;
 406        gpiocr_regs = npct->soc->prcm_gpiocr_registers;
 407        for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
 408                if (pin_desc->altcx[i].used == true) {
 409                        reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
 410                        bit = pin_desc->altcx[i].control_bit;
 411                        if (readl(npct->prcm_base + reg) & BIT(bit))
 412                                return NMK_GPIO_ALT_C+i+1;
 413                }
 414        }
 415        return NMK_GPIO_ALT_C;
 416}
 417
 418int nmk_gpio_get_mode(int gpio)
 419{
 420        struct nmk_gpio_chip *nmk_chip;
 421        u32 afunc, bfunc, bit;
 422
 423        nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
 424        if (!nmk_chip)
 425                return -EINVAL;
 426
 427        bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
 428
 429        clk_enable(nmk_chip->clk);
 430
 431        afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
 432        bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
 433
 434        clk_disable(nmk_chip->clk);
 435
 436        return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
 437}
 438EXPORT_SYMBOL(nmk_gpio_get_mode);
 439
 440
 441/* IRQ functions */
 442static inline int nmk_gpio_get_bitmask(int gpio)
 443{
 444        return 1 << (gpio % NMK_GPIO_PER_CHIP);
 445}
 446
 447static void nmk_gpio_irq_ack(struct irq_data *d)
 448{
 449        struct nmk_gpio_chip *nmk_chip;
 450
 451        nmk_chip = irq_data_get_irq_chip_data(d);
 452        if (!nmk_chip)
 453                return;
 454
 455        clk_enable(nmk_chip->clk);
 456        writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
 457        clk_disable(nmk_chip->clk);
 458}
 459
 460enum nmk_gpio_irq_type {
 461        NORMAL,
 462        WAKE,
 463};
 464
 465static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
 466                                  int gpio, enum nmk_gpio_irq_type which,
 467                                  bool enable)
 468{
 469        u32 bitmask = nmk_gpio_get_bitmask(gpio);
 470        u32 *rimscval;
 471        u32 *fimscval;
 472        u32 rimscreg;
 473        u32 fimscreg;
 474
 475        if (which == NORMAL) {
 476                rimscreg = NMK_GPIO_RIMSC;
 477                fimscreg = NMK_GPIO_FIMSC;
 478                rimscval = &nmk_chip->rimsc;
 479                fimscval = &nmk_chip->fimsc;
 480        } else  {
 481                rimscreg = NMK_GPIO_RWIMSC;
 482                fimscreg = NMK_GPIO_FWIMSC;
 483                rimscval = &nmk_chip->rwimsc;
 484                fimscval = &nmk_chip->fwimsc;
 485        }
 486
 487        /* we must individually set/clear the two edges */
 488        if (nmk_chip->edge_rising & bitmask) {
 489                if (enable)
 490                        *rimscval |= bitmask;
 491                else
 492                        *rimscval &= ~bitmask;
 493                writel(*rimscval, nmk_chip->addr + rimscreg);
 494        }
 495        if (nmk_chip->edge_falling & bitmask) {
 496                if (enable)
 497                        *fimscval |= bitmask;
 498                else
 499                        *fimscval &= ~bitmask;
 500                writel(*fimscval, nmk_chip->addr + fimscreg);
 501        }
 502}
 503
 504static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
 505                                int gpio, bool on)
 506{
 507        /*
 508         * Ensure WAKEUP_ENABLE is on.  No need to disable it if wakeup is
 509         * disabled, since setting SLPM to 1 increases power consumption, and
 510         * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
 511         */
 512        if (nmk_chip->sleepmode && on) {
 513                __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
 514                                    NMK_GPIO_SLPM_WAKEUP_ENABLE);
 515        }
 516
 517        __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
 518}
 519
 520static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
 521{
 522        struct nmk_gpio_chip *nmk_chip;
 523        unsigned long flags;
 524        u32 bitmask;
 525
 526        nmk_chip = irq_data_get_irq_chip_data(d);
 527        bitmask = nmk_gpio_get_bitmask(d->hwirq);
 528        if (!nmk_chip)
 529                return -EINVAL;
 530
 531        clk_enable(nmk_chip->clk);
 532        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
 533        spin_lock(&nmk_chip->lock);
 534
 535        __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
 536
 537        if (!(nmk_chip->real_wake & bitmask))
 538                __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
 539
 540        spin_unlock(&nmk_chip->lock);
 541        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
 542        clk_disable(nmk_chip->clk);
 543
 544        return 0;
 545}
 546
 547static void nmk_gpio_irq_mask(struct irq_data *d)
 548{
 549        nmk_gpio_irq_maskunmask(d, false);
 550}
 551
 552static void nmk_gpio_irq_unmask(struct irq_data *d)
 553{
 554        nmk_gpio_irq_maskunmask(d, true);
 555}
 556
 557static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 558{
 559        struct nmk_gpio_chip *nmk_chip;
 560        unsigned long flags;
 561        u32 bitmask;
 562
 563        nmk_chip = irq_data_get_irq_chip_data(d);
 564        if (!nmk_chip)
 565                return -EINVAL;
 566        bitmask = nmk_gpio_get_bitmask(d->hwirq);
 567
 568        clk_enable(nmk_chip->clk);
 569        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
 570        spin_lock(&nmk_chip->lock);
 571
 572        if (irqd_irq_disabled(d))
 573                __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
 574
 575        if (on)
 576                nmk_chip->real_wake |= bitmask;
 577        else
 578                nmk_chip->real_wake &= ~bitmask;
 579
 580        spin_unlock(&nmk_chip->lock);
 581        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
 582        clk_disable(nmk_chip->clk);
 583
 584        return 0;
 585}
 586
 587static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 588{
 589        bool enabled = !irqd_irq_disabled(d);
 590        bool wake = irqd_is_wakeup_set(d);
 591        struct nmk_gpio_chip *nmk_chip;
 592        unsigned long flags;
 593        u32 bitmask;
 594
 595        nmk_chip = irq_data_get_irq_chip_data(d);
 596        bitmask = nmk_gpio_get_bitmask(d->hwirq);
 597        if (!nmk_chip)
 598                return -EINVAL;
 599        if (type & IRQ_TYPE_LEVEL_HIGH)
 600                return -EINVAL;
 601        if (type & IRQ_TYPE_LEVEL_LOW)
 602                return -EINVAL;
 603
 604        clk_enable(nmk_chip->clk);
 605        spin_lock_irqsave(&nmk_chip->lock, flags);
 606
 607        if (enabled)
 608                __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
 609
 610        if (enabled || wake)
 611                __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
 612
 613        nmk_chip->edge_rising &= ~bitmask;
 614        if (type & IRQ_TYPE_EDGE_RISING)
 615                nmk_chip->edge_rising |= bitmask;
 616
 617        nmk_chip->edge_falling &= ~bitmask;
 618        if (type & IRQ_TYPE_EDGE_FALLING)
 619                nmk_chip->edge_falling |= bitmask;
 620
 621        if (enabled)
 622                __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
 623
 624        if (enabled || wake)
 625                __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
 626
 627        spin_unlock_irqrestore(&nmk_chip->lock, flags);
 628        clk_disable(nmk_chip->clk);
 629
 630        return 0;
 631}
 632
 633static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
 634{
 635        struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
 636
 637        clk_enable(nmk_chip->clk);
 638        nmk_gpio_irq_unmask(d);
 639        return 0;
 640}
 641
 642static void nmk_gpio_irq_shutdown(struct irq_data *d)
 643{
 644        struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
 645
 646        nmk_gpio_irq_mask(d);
 647        clk_disable(nmk_chip->clk);
 648}
 649
 650static struct irq_chip nmk_gpio_irq_chip = {
 651        .name           = "Nomadik-GPIO",
 652        .irq_ack        = nmk_gpio_irq_ack,
 653        .irq_mask       = nmk_gpio_irq_mask,
 654        .irq_unmask     = nmk_gpio_irq_unmask,
 655        .irq_set_type   = nmk_gpio_irq_set_type,
 656        .irq_set_wake   = nmk_gpio_irq_set_wake,
 657        .irq_startup    = nmk_gpio_irq_startup,
 658        .irq_shutdown   = nmk_gpio_irq_shutdown,
 659        .flags          = IRQCHIP_MASK_ON_SUSPEND,
 660};
 661
 662static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
 663                                   u32 status)
 664{
 665        struct nmk_gpio_chip *nmk_chip;
 666        struct irq_chip *host_chip = irq_get_chip(irq);
 667
 668        chained_irq_enter(host_chip, desc);
 669
 670        nmk_chip = irq_get_handler_data(irq);
 671        while (status) {
 672                int bit = __ffs(status);
 673
 674                generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
 675                status &= ~BIT(bit);
 676        }
 677
 678        chained_irq_exit(host_chip, desc);
 679}
 680
 681static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 682{
 683        struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
 684        u32 status;
 685
 686        clk_enable(nmk_chip->clk);
 687        status = readl(nmk_chip->addr + NMK_GPIO_IS);
 688        clk_disable(nmk_chip->clk);
 689
 690        __nmk_gpio_irq_handler(irq, desc, status);
 691}
 692
 693static void nmk_gpio_secondary_irq_handler(unsigned int irq,
 694                                           struct irq_desc *desc)
 695{
 696        struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
 697        u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
 698
 699        __nmk_gpio_irq_handler(irq, desc, status);
 700}
 701
 702static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
 703{
 704        irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
 705        irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
 706
 707        if (nmk_chip->secondary_parent_irq >= 0) {
 708                irq_set_chained_handler(nmk_chip->secondary_parent_irq,
 709                                        nmk_gpio_secondary_irq_handler);
 710                irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
 711        }
 712
 713        return 0;
 714}
 715
 716/* I/O Functions */
 717
 718static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
 719{
 720        /*
 721         * Map back to global GPIO space and request muxing, the direction
 722         * parameter does not matter for this controller.
 723         */
 724        int gpio = chip->base + offset;
 725
 726        return pinctrl_request_gpio(gpio);
 727}
 728
 729static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
 730{
 731        int gpio = chip->base + offset;
 732
 733        pinctrl_free_gpio(gpio);
 734}
 735
 736static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
 737{
 738        struct nmk_gpio_chip *nmk_chip =
 739                container_of(chip, struct nmk_gpio_chip, chip);
 740
 741        clk_enable(nmk_chip->clk);
 742
 743        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
 744
 745        clk_disable(nmk_chip->clk);
 746
 747        return 0;
 748}
 749
 750static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
 751{
 752        struct nmk_gpio_chip *nmk_chip =
 753                container_of(chip, struct nmk_gpio_chip, chip);
 754        u32 bit = 1 << offset;
 755        int value;
 756
 757        clk_enable(nmk_chip->clk);
 758
 759        value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
 760
 761        clk_disable(nmk_chip->clk);
 762
 763        return value;
 764}
 765
 766static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
 767                                int val)
 768{
 769        struct nmk_gpio_chip *nmk_chip =
 770                container_of(chip, struct nmk_gpio_chip, chip);
 771
 772        clk_enable(nmk_chip->clk);
 773
 774        __nmk_gpio_set_output(nmk_chip, offset, val);
 775
 776        clk_disable(nmk_chip->clk);
 777}
 778
 779static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
 780                                int val)
 781{
 782        struct nmk_gpio_chip *nmk_chip =
 783                container_of(chip, struct nmk_gpio_chip, chip);
 784
 785        clk_enable(nmk_chip->clk);
 786
 787        __nmk_gpio_make_output(nmk_chip, offset, val);
 788
 789        clk_disable(nmk_chip->clk);
 790
 791        return 0;
 792}
 793
 794static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 795{
 796        struct nmk_gpio_chip *nmk_chip =
 797                container_of(chip, struct nmk_gpio_chip, chip);
 798
 799        return irq_create_mapping(nmk_chip->domain, offset);
 800}
 801
 802#ifdef CONFIG_DEBUG_FS
 803
 804#include <linux/seq_file.h>
 805
 806static void nmk_gpio_dbg_show_one(struct seq_file *s,
 807        struct pinctrl_dev *pctldev, struct gpio_chip *chip,
 808        unsigned offset, unsigned gpio)
 809{
 810        const char *label = gpiochip_is_requested(chip, offset);
 811        struct nmk_gpio_chip *nmk_chip =
 812                container_of(chip, struct nmk_gpio_chip, chip);
 813        int mode;
 814        bool is_out;
 815        bool pull;
 816        u32 bit = 1 << offset;
 817        const char *modes[] = {
 818                [NMK_GPIO_ALT_GPIO]     = "gpio",
 819                [NMK_GPIO_ALT_A]        = "altA",
 820                [NMK_GPIO_ALT_B]        = "altB",
 821                [NMK_GPIO_ALT_C]        = "altC",
 822                [NMK_GPIO_ALT_C+1]      = "altC1",
 823                [NMK_GPIO_ALT_C+2]      = "altC2",
 824                [NMK_GPIO_ALT_C+3]      = "altC3",
 825                [NMK_GPIO_ALT_C+4]      = "altC4",
 826        };
 827
 828        clk_enable(nmk_chip->clk);
 829        is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
 830        pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
 831        mode = nmk_gpio_get_mode(gpio);
 832        if ((mode == NMK_GPIO_ALT_C) && pctldev)
 833                mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
 834
 835        seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
 836                   gpio, label ?: "(none)",
 837                   is_out ? "out" : "in ",
 838                   chip->get
 839                   ? (chip->get(chip, offset) ? "hi" : "lo")
 840                   : "?  ",
 841                   (mode < 0) ? "unknown" : modes[mode],
 842                   pull ? "pull" : "none");
 843
 844        if (label && !is_out) {
 845                int             irq = gpio_to_irq(gpio);
 846                struct irq_desc *desc = irq_to_desc(irq);
 847
 848                /* This races with request_irq(), set_irq_type(),
 849                 * and set_irq_wake() ... but those are "rare".
 850                 */
 851                if (irq >= 0 && desc->action) {
 852                        char *trigger;
 853                        u32 bitmask = nmk_gpio_get_bitmask(gpio);
 854
 855                        if (nmk_chip->edge_rising & bitmask)
 856                                trigger = "edge-rising";
 857                        else if (nmk_chip->edge_falling & bitmask)
 858                                trigger = "edge-falling";
 859                        else
 860                                trigger = "edge-undefined";
 861
 862                        seq_printf(s, " irq-%d %s%s",
 863                                   irq, trigger,
 864                                   irqd_is_wakeup_set(&desc->irq_data)
 865                                   ? " wakeup" : "");
 866                }
 867        }
 868        clk_disable(nmk_chip->clk);
 869}
 870
 871static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 872{
 873        unsigned                i;
 874        unsigned                gpio = chip->base;
 875
 876        for (i = 0; i < chip->ngpio; i++, gpio++) {
 877                nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
 878                seq_printf(s, "\n");
 879        }
 880}
 881
 882#else
 883static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
 884                                         struct pinctrl_dev *pctldev,
 885                                         struct gpio_chip *chip,
 886                                         unsigned offset, unsigned gpio)
 887{
 888}
 889#define nmk_gpio_dbg_show       NULL
 890#endif
 891
 892/* This structure is replicated for each GPIO block allocated at probe time */
 893static struct gpio_chip nmk_gpio_template = {
 894        .request                = nmk_gpio_request,
 895        .free                   = nmk_gpio_free,
 896        .direction_input        = nmk_gpio_make_input,
 897        .get                    = nmk_gpio_get_input,
 898        .direction_output       = nmk_gpio_make_output,
 899        .set                    = nmk_gpio_set_output,
 900        .to_irq                 = nmk_gpio_to_irq,
 901        .dbg_show               = nmk_gpio_dbg_show,
 902        .can_sleep              = 0,
 903};
 904
 905void nmk_gpio_clocks_enable(void)
 906{
 907        int i;
 908
 909        for (i = 0; i < NUM_BANKS; i++) {
 910                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
 911
 912                if (!chip)
 913                        continue;
 914
 915                clk_enable(chip->clk);
 916        }
 917}
 918
 919void nmk_gpio_clocks_disable(void)
 920{
 921        int i;
 922
 923        for (i = 0; i < NUM_BANKS; i++) {
 924                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
 925
 926                if (!chip)
 927                        continue;
 928
 929                clk_disable(chip->clk);
 930        }
 931}
 932
 933/*
 934 * Called from the suspend/resume path to only keep the real wakeup interrupts
 935 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
 936 * and not the rest of the interrupts which we needed to have as wakeups for
 937 * cpuidle.
 938 *
 939 * PM ops are not used since this needs to be done at the end, after all the
 940 * other drivers are done with their suspend callbacks.
 941 */
 942void nmk_gpio_wakeups_suspend(void)
 943{
 944        int i;
 945
 946        for (i = 0; i < NUM_BANKS; i++) {
 947                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
 948
 949                if (!chip)
 950                        break;
 951
 952                clk_enable(chip->clk);
 953
 954                writel(chip->rwimsc & chip->real_wake,
 955                       chip->addr + NMK_GPIO_RWIMSC);
 956                writel(chip->fwimsc & chip->real_wake,
 957                       chip->addr + NMK_GPIO_FWIMSC);
 958
 959                clk_disable(chip->clk);
 960        }
 961}
 962
 963void nmk_gpio_wakeups_resume(void)
 964{
 965        int i;
 966
 967        for (i = 0; i < NUM_BANKS; i++) {
 968                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
 969
 970                if (!chip)
 971                        break;
 972
 973                clk_enable(chip->clk);
 974
 975                writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
 976                writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
 977
 978                clk_disable(chip->clk);
 979        }
 980}
 981
 982/*
 983 * Read the pull up/pull down status.
 984 * A bit set in 'pull_up' means that pull up
 985 * is selected if pull is enabled in PDIS register.
 986 * Note: only pull up/down set via this driver can
 987 * be detected due to HW limitations.
 988 */
 989void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
 990{
 991        if (gpio_bank < NUM_BANKS) {
 992                struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
 993
 994                if (!chip)
 995                        return;
 996
 997                *pull_up = chip->pull_up;
 998        }
 999}
1000
1001static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1002                            irq_hw_number_t hwirq)
1003{
1004        struct nmk_gpio_chip *nmk_chip = d->host_data;
1005
1006        if (!nmk_chip)
1007                return -EINVAL;
1008
1009        irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1010        set_irq_flags(irq, IRQF_VALID);
1011        irq_set_chip_data(irq, nmk_chip);
1012        irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1013
1014        return 0;
1015}
1016
1017static const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1018        .map = nmk_gpio_irq_map,
1019        .xlate = irq_domain_xlate_twocell,
1020};
1021
1022static int nmk_gpio_probe(struct platform_device *dev)
1023{
1024        struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1025        struct device_node *np = dev->dev.of_node;
1026        struct nmk_gpio_chip *nmk_chip;
1027        struct gpio_chip *chip;
1028        struct resource *res;
1029        struct clk *clk;
1030        int secondary_irq;
1031        void __iomem *base;
1032        int irq_start = 0;
1033        int irq;
1034        int ret;
1035
1036        if (!pdata && !np) {
1037                dev_err(&dev->dev, "No platform data or device tree found\n");
1038                return -ENODEV;
1039        }
1040
1041        if (np) {
1042                pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1043                if (!pdata)
1044                        return -ENOMEM;
1045
1046                if (of_get_property(np, "st,supports-sleepmode", NULL))
1047                        pdata->supports_sleepmode = true;
1048
1049                if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1050                        dev_err(&dev->dev, "gpio-bank property not found\n");
1051                        return -EINVAL;
1052                }
1053
1054                pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1055                pdata->num_gpio   = NMK_GPIO_PER_CHIP;
1056        }
1057
1058        irq = platform_get_irq(dev, 0);
1059        if (irq < 0)
1060                return irq;
1061
1062        secondary_irq = platform_get_irq(dev, 1);
1063        if (secondary_irq >= 0 && !pdata->get_secondary_status)
1064                return -EINVAL;
1065
1066        res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1067        base = devm_ioremap_resource(&dev->dev, res);
1068        if (IS_ERR(base))
1069                return PTR_ERR(base);
1070
1071        clk = devm_clk_get(&dev->dev, NULL);
1072        if (IS_ERR(clk))
1073                return PTR_ERR(clk);
1074        clk_prepare(clk);
1075
1076        nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1077        if (!nmk_chip)
1078                return -ENOMEM;
1079
1080        /*
1081         * The virt address in nmk_chip->addr is in the nomadik register space,
1082         * so we can simply convert the resource address, without remapping
1083         */
1084        nmk_chip->bank = dev->id;
1085        nmk_chip->clk = clk;
1086        nmk_chip->addr = base;
1087        nmk_chip->chip = nmk_gpio_template;
1088        nmk_chip->parent_irq = irq;
1089        nmk_chip->secondary_parent_irq = secondary_irq;
1090        nmk_chip->get_secondary_status = pdata->get_secondary_status;
1091        nmk_chip->set_ioforce = pdata->set_ioforce;
1092        nmk_chip->sleepmode = pdata->supports_sleepmode;
1093        spin_lock_init(&nmk_chip->lock);
1094
1095        chip = &nmk_chip->chip;
1096        chip->base = pdata->first_gpio;
1097        chip->ngpio = pdata->num_gpio;
1098        chip->label = pdata->name ?: dev_name(&dev->dev);
1099        chip->dev = &dev->dev;
1100        chip->owner = THIS_MODULE;
1101
1102        clk_enable(nmk_chip->clk);
1103        nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1104        clk_disable(nmk_chip->clk);
1105
1106#ifdef CONFIG_OF_GPIO
1107        chip->of_node = np;
1108#endif
1109
1110        ret = gpiochip_add(&nmk_chip->chip);
1111        if (ret)
1112                return ret;
1113
1114        BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1115
1116        nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1117
1118        platform_set_drvdata(dev, nmk_chip);
1119
1120        if (!np)
1121                irq_start = pdata->first_irq;
1122        nmk_chip->domain = irq_domain_add_simple(np,
1123                                NMK_GPIO_PER_CHIP, irq_start,
1124                                &nmk_gpio_irq_simple_ops, nmk_chip);
1125        if (!nmk_chip->domain) {
1126                dev_err(&dev->dev, "failed to create irqdomain\n");
1127                /* Just do this, no matter if it fails */
1128                ret = gpiochip_remove(&nmk_chip->chip);
1129                return -ENOSYS;
1130        }
1131
1132        nmk_gpio_init_irq(nmk_chip);
1133
1134        dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1135
1136        return 0;
1137}
1138
1139static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1140{
1141        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1142
1143        return npct->soc->ngroups;
1144}
1145
1146static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1147                                       unsigned selector)
1148{
1149        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1150
1151        return npct->soc->groups[selector].name;
1152}
1153
1154static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1155                              const unsigned **pins,
1156                              unsigned *num_pins)
1157{
1158        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1159
1160        *pins = npct->soc->groups[selector].pins;
1161        *num_pins = npct->soc->groups[selector].npins;
1162        return 0;
1163}
1164
1165static struct pinctrl_gpio_range *
1166nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1167{
1168        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1169        int i;
1170
1171        for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1172                struct pinctrl_gpio_range *range;
1173
1174                range = &npct->soc->gpio_ranges[i];
1175                if (offset >= range->pin_base &&
1176                    offset <= (range->pin_base + range->npins - 1))
1177                        return range;
1178        }
1179        return NULL;
1180}
1181
1182static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1183                   unsigned offset)
1184{
1185        struct pinctrl_gpio_range *range;
1186        struct gpio_chip *chip;
1187
1188        range = nmk_match_gpio_range(pctldev, offset);
1189        if (!range || !range->gc) {
1190                seq_printf(s, "invalid pin offset");
1191                return;
1192        }
1193        chip = range->gc;
1194        nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1195}
1196
1197static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
1198                struct pinctrl_map *map, unsigned num_maps)
1199{
1200        int i;
1201
1202        for (i = 0; i < num_maps; i++)
1203                if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
1204                        kfree(map[i].data.configs.configs);
1205        kfree(map);
1206}
1207
1208static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
1209                unsigned *num_maps, unsigned reserve)
1210{
1211        unsigned old_num = *reserved_maps;
1212        unsigned new_num = *num_maps + reserve;
1213        struct pinctrl_map *new_map;
1214
1215        if (old_num >= new_num)
1216                return 0;
1217
1218        new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
1219        if (!new_map)
1220                return -ENOMEM;
1221
1222        memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
1223
1224        *map = new_map;
1225        *reserved_maps = new_num;
1226
1227        return 0;
1228}
1229
1230static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1231                unsigned *num_maps, const char *group,
1232                const char *function)
1233{
1234        if (*num_maps == *reserved_maps)
1235                return -ENOSPC;
1236
1237        (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1238        (*map)[*num_maps].data.mux.group = group;
1239        (*map)[*num_maps].data.mux.function = function;
1240        (*num_maps)++;
1241
1242        return 0;
1243}
1244
1245static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1246                unsigned *reserved_maps,
1247                unsigned *num_maps, const char *group,
1248                unsigned long *configs, unsigned num_configs)
1249{
1250        unsigned long *dup_configs;
1251
1252        if (*num_maps == *reserved_maps)
1253                return -ENOSPC;
1254
1255        dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1256                              GFP_KERNEL);
1257        if (!dup_configs)
1258                return -ENOMEM;
1259
1260        (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1261
1262        (*map)[*num_maps].data.configs.group_or_pin = group;
1263        (*map)[*num_maps].data.configs.configs = dup_configs;
1264        (*map)[*num_maps].data.configs.num_configs = num_configs;
1265        (*num_maps)++;
1266
1267        return 0;
1268}
1269
1270#define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1271#define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1272        .size = ARRAY_SIZE(y), }
1273
1274static const unsigned long nmk_pin_input_modes[] = {
1275        PIN_INPUT_NOPULL,
1276        PIN_INPUT_PULLUP,
1277        PIN_INPUT_PULLDOWN,
1278};
1279
1280static const unsigned long nmk_pin_output_modes[] = {
1281        PIN_OUTPUT_LOW,
1282        PIN_OUTPUT_HIGH,
1283        PIN_DIR_OUTPUT,
1284};
1285
1286static const unsigned long nmk_pin_sleep_modes[] = {
1287        PIN_SLEEPMODE_DISABLED,
1288        PIN_SLEEPMODE_ENABLED,
1289};
1290
1291static const unsigned long nmk_pin_sleep_input_modes[] = {
1292        PIN_SLPM_INPUT_NOPULL,
1293        PIN_SLPM_INPUT_PULLUP,
1294        PIN_SLPM_INPUT_PULLDOWN,
1295        PIN_SLPM_DIR_INPUT,
1296};
1297
1298static const unsigned long nmk_pin_sleep_output_modes[] = {
1299        PIN_SLPM_OUTPUT_LOW,
1300        PIN_SLPM_OUTPUT_HIGH,
1301        PIN_SLPM_DIR_OUTPUT,
1302};
1303
1304static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1305        PIN_SLPM_WAKEUP_DISABLE,
1306        PIN_SLPM_WAKEUP_ENABLE,
1307};
1308
1309static const unsigned long nmk_pin_gpio_modes[] = {
1310        PIN_GPIOMODE_DISABLED,
1311        PIN_GPIOMODE_ENABLED,
1312};
1313
1314static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1315        PIN_SLPM_PDIS_DISABLED,
1316        PIN_SLPM_PDIS_ENABLED,
1317};
1318
1319struct nmk_cfg_param {
1320        const char *property;
1321        unsigned long config;
1322        const unsigned long *choice;
1323        int size;
1324};
1325
1326static const struct nmk_cfg_param nmk_cfg_params[] = {
1327        NMK_CONFIG_PIN_ARRAY("ste,input",               nmk_pin_input_modes),
1328        NMK_CONFIG_PIN_ARRAY("ste,output",              nmk_pin_output_modes),
1329        NMK_CONFIG_PIN_ARRAY("ste,sleep",               nmk_pin_sleep_modes),
1330        NMK_CONFIG_PIN_ARRAY("ste,sleep-input",         nmk_pin_sleep_input_modes),
1331        NMK_CONFIG_PIN_ARRAY("ste,sleep-output",        nmk_pin_sleep_output_modes),
1332        NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup",        nmk_pin_sleep_wakeup_modes),
1333        NMK_CONFIG_PIN_ARRAY("ste,gpio",                nmk_pin_gpio_modes),
1334        NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable",  nmk_pin_sleep_pdis_modes),
1335};
1336
1337static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1338{
1339        int ret = 0;
1340
1341        if (nmk_cfg_params[index].choice == NULL)
1342                *config = nmk_cfg_params[index].config;
1343        else {
1344                /* test if out of range */
1345                if  (val < nmk_cfg_params[index].size) {
1346                        *config = nmk_cfg_params[index].config |
1347                                nmk_cfg_params[index].choice[val];
1348                }
1349        }
1350        return ret;
1351}
1352
1353static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1354{
1355        int i, pin_number;
1356        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1357
1358        if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1359                for (i = 0; i < npct->soc->npins; i++)
1360                        if (npct->soc->pins[i].number == pin_number)
1361                                return npct->soc->pins[i].name;
1362        return NULL;
1363}
1364
1365static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1366                unsigned long *configs)
1367{
1368        bool has_config = 0;
1369        unsigned long cfg = 0;
1370        int i, val, ret;
1371
1372        for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1373                ret = of_property_read_u32(np,
1374                                nmk_cfg_params[i].property, &val);
1375                if (ret != -EINVAL) {
1376                        if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1377                                *configs |= cfg;
1378                                has_config = 1;
1379                        }
1380                }
1381        }
1382
1383        return has_config;
1384}
1385
1386static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1387                struct device_node *np,
1388                struct pinctrl_map **map,
1389                unsigned *reserved_maps,
1390                unsigned *num_maps)
1391{
1392        int ret;
1393        const char *function = NULL;
1394        unsigned long configs = 0;
1395        bool has_config = 0;
1396        unsigned reserve = 0;
1397        struct property *prop;
1398        const char *group, *gpio_name;
1399        struct device_node *np_config;
1400
1401        ret = of_property_read_string(np, "ste,function", &function);
1402        if (ret >= 0)
1403                reserve = 1;
1404
1405        has_config = nmk_pinctrl_dt_get_config(np, &configs);
1406
1407        np_config = of_parse_phandle(np, "ste,config", 0);
1408        if (np_config)
1409                has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1410
1411        ret = of_property_count_strings(np, "ste,pins");
1412        if (ret < 0)
1413                goto exit;
1414
1415        if (has_config)
1416                reserve++;
1417
1418        reserve *= ret;
1419
1420        ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve);
1421        if (ret < 0)
1422                goto exit;
1423
1424        of_property_for_each_string(np, "ste,pins", prop, group) {
1425                if (function) {
1426                        ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1427                                          group, function);
1428                        if (ret < 0)
1429                                goto exit;
1430                }
1431                if (has_config) {
1432                        gpio_name = nmk_find_pin_name(pctldev, group);
1433
1434                        ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps,
1435                                              gpio_name, &configs, 1);
1436                        if (ret < 0)
1437                                goto exit;
1438                }
1439
1440        }
1441exit:
1442        return ret;
1443}
1444
1445static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1446                                 struct device_node *np_config,
1447                                 struct pinctrl_map **map, unsigned *num_maps)
1448{
1449        unsigned reserved_maps;
1450        struct device_node *np;
1451        int ret;
1452
1453        reserved_maps = 0;
1454        *map = NULL;
1455        *num_maps = 0;
1456
1457        for_each_child_of_node(np_config, np) {
1458                ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1459                                &reserved_maps, num_maps);
1460                if (ret < 0) {
1461                        nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps);
1462                        return ret;
1463                }
1464        }
1465
1466        return 0;
1467}
1468
1469static const struct pinctrl_ops nmk_pinctrl_ops = {
1470        .get_groups_count = nmk_get_groups_cnt,
1471        .get_group_name = nmk_get_group_name,
1472        .get_group_pins = nmk_get_group_pins,
1473        .pin_dbg_show = nmk_pin_dbg_show,
1474        .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1475        .dt_free_map = nmk_pinctrl_dt_free_map,
1476};
1477
1478static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1479{
1480        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1481
1482        return npct->soc->nfunctions;
1483}
1484
1485static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1486                                         unsigned function)
1487{
1488        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1489
1490        return npct->soc->functions[function].name;
1491}
1492
1493static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1494                                   unsigned function,
1495                                   const char * const **groups,
1496                                   unsigned * const num_groups)
1497{
1498        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1499
1500        *groups = npct->soc->functions[function].groups;
1501        *num_groups = npct->soc->functions[function].ngroups;
1502
1503        return 0;
1504}
1505
1506static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1507                          unsigned group)
1508{
1509        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1510        const struct nmk_pingroup *g;
1511        static unsigned int slpm[NUM_BANKS];
1512        unsigned long flags = 0;
1513        bool glitch;
1514        int ret = -EINVAL;
1515        int i;
1516
1517        g = &npct->soc->groups[group];
1518
1519        if (g->altsetting < 0)
1520                return -EINVAL;
1521
1522        dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1523
1524        /*
1525         * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1526         * we may pass through an undesired state. In this case we take
1527         * some extra care.
1528         *
1529         * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1530         *  - Save SLPM registers (since we have a shadow register in the
1531         *    nmk_chip we're using that as backup)
1532         *  - Set SLPM=0 for the IOs you want to switch and others to 1
1533         *  - Configure the GPIO registers for the IOs that are being switched
1534         *  - Set IOFORCE=1
1535         *  - Modify the AFLSA/B registers for the IOs that are being switched
1536         *  - Set IOFORCE=0
1537         *  - Restore SLPM registers
1538         *  - Any spurious wake up event during switch sequence to be ignored
1539         *    and cleared
1540         *
1541         * We REALLY need to save ALL slpm registers, because the external
1542         * IOFORCE will switch *all* ports to their sleepmode setting to as
1543         * to avoid glitches. (Not just one port!)
1544         */
1545        glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1546
1547        if (glitch) {
1548                spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1549
1550                /* Initially don't put any pins to sleep when switching */
1551                memset(slpm, 0xff, sizeof(slpm));
1552
1553                /*
1554                 * Then mask the pins that need to be sleeping now when we're
1555                 * switching to the ALT C function.
1556                 */
1557                for (i = 0; i < g->npins; i++)
1558                        slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1559                nmk_gpio_glitch_slpm_init(slpm);
1560        }
1561
1562        for (i = 0; i < g->npins; i++) {
1563                struct pinctrl_gpio_range *range;
1564                struct nmk_gpio_chip *nmk_chip;
1565                struct gpio_chip *chip;
1566                unsigned bit;
1567
1568                range = nmk_match_gpio_range(pctldev, g->pins[i]);
1569                if (!range) {
1570                        dev_err(npct->dev,
1571                                "invalid pin offset %d in group %s at index %d\n",
1572                                g->pins[i], g->name, i);
1573                        goto out_glitch;
1574                }
1575                if (!range->gc) {
1576                        dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1577                                g->pins[i], g->name, i);
1578                        goto out_glitch;
1579                }
1580                chip = range->gc;
1581                nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1582                dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1583
1584                clk_enable(nmk_chip->clk);
1585                bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1586                /*
1587                 * If the pin is switching to altfunc, and there was an
1588                 * interrupt installed on it which has been lazy disabled,
1589                 * actually mask the interrupt to prevent spurious interrupts
1590                 * that would occur while the pin is under control of the
1591                 * peripheral. Only SKE does this.
1592                 */
1593                nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1594
1595                __nmk_gpio_set_mode_safe(nmk_chip, bit,
1596                        (g->altsetting & NMK_GPIO_ALT_C), glitch);
1597                clk_disable(nmk_chip->clk);
1598
1599                /*
1600                 * Call PRCM GPIOCR config function in case ALTC
1601                 * has been selected:
1602                 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1603                 *   must be set.
1604                 * - If selection is pure ALTC and previous selection was ALTCx,
1605                 *   then some bits in PRCM GPIOCR registers must be cleared.
1606                 */
1607                if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1608                        nmk_prcm_altcx_set_mode(npct, g->pins[i],
1609                                g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1610        }
1611
1612        /* When all pins are successfully reconfigured we get here */
1613        ret = 0;
1614
1615out_glitch:
1616        if (glitch) {
1617                nmk_gpio_glitch_slpm_restore(slpm);
1618                spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1619        }
1620
1621        return ret;
1622}
1623
1624static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1625                            unsigned function, unsigned group)
1626{
1627        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1628        const struct nmk_pingroup *g;
1629
1630        g = &npct->soc->groups[group];
1631
1632        if (g->altsetting < 0)
1633                return;
1634
1635        /* Poke out the mux, set the pin to some default state? */
1636        dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1637}
1638
1639static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1640                                   struct pinctrl_gpio_range *range,
1641                                   unsigned offset)
1642{
1643        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1644        struct nmk_gpio_chip *nmk_chip;
1645        struct gpio_chip *chip;
1646        unsigned bit;
1647
1648        if (!range) {
1649                dev_err(npct->dev, "invalid range\n");
1650                return -EINVAL;
1651        }
1652        if (!range->gc) {
1653                dev_err(npct->dev, "missing GPIO chip in range\n");
1654                return -EINVAL;
1655        }
1656        chip = range->gc;
1657        nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1658
1659        dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1660
1661        clk_enable(nmk_chip->clk);
1662        bit = offset % NMK_GPIO_PER_CHIP;
1663        /* There is no glitch when converting any pin to GPIO */
1664        __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1665        clk_disable(nmk_chip->clk);
1666
1667        return 0;
1668}
1669
1670static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1671                                  struct pinctrl_gpio_range *range,
1672                                  unsigned offset)
1673{
1674        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1675
1676        dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1677        /* Set the pin to some default state, GPIO is usually default */
1678}
1679
1680static const struct pinmux_ops nmk_pinmux_ops = {
1681        .get_functions_count = nmk_pmx_get_funcs_cnt,
1682        .get_function_name = nmk_pmx_get_func_name,
1683        .get_function_groups = nmk_pmx_get_func_groups,
1684        .enable = nmk_pmx_enable,
1685        .disable = nmk_pmx_disable,
1686        .gpio_request_enable = nmk_gpio_request_enable,
1687        .gpio_disable_free = nmk_gpio_disable_free,
1688};
1689
1690static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1691                              unsigned long *config)
1692{
1693        /* Not implemented */
1694        return -EINVAL;
1695}
1696
1697static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1698                              unsigned long *configs, unsigned num_configs)
1699{
1700        static const char *pullnames[] = {
1701                [NMK_GPIO_PULL_NONE]    = "none",
1702                [NMK_GPIO_PULL_UP]      = "up",
1703                [NMK_GPIO_PULL_DOWN]    = "down",
1704                [3] /* illegal */       = "??"
1705        };
1706        static const char *slpmnames[] = {
1707                [NMK_GPIO_SLPM_INPUT]           = "input/wakeup",
1708                [NMK_GPIO_SLPM_NOCHANGE]        = "no-change/no-wakeup",
1709        };
1710        struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1711        struct nmk_gpio_chip *nmk_chip;
1712        struct pinctrl_gpio_range *range;
1713        struct gpio_chip *chip;
1714        unsigned bit;
1715        pin_cfg_t cfg;
1716        int pull, slpm, output, val, i;
1717        bool lowemi, gpiomode, sleep;
1718
1719        range = nmk_match_gpio_range(pctldev, pin);
1720        if (!range) {
1721                dev_err(npct->dev, "invalid pin offset %d\n", pin);
1722                return -EINVAL;
1723        }
1724        if (!range->gc) {
1725                dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1726                        pin);
1727                return -EINVAL;
1728        }
1729        chip = range->gc;
1730        nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1731
1732        for (i = 0; i < num_configs; i++) {
1733                /*
1734                 * The pin config contains pin number and altfunction fields,
1735                 * here we just ignore that part. It's being handled by the
1736                 * framework and pinmux callback respectively.
1737                 */
1738                cfg = (pin_cfg_t) configs[i];
1739                pull = PIN_PULL(cfg);
1740                slpm = PIN_SLPM(cfg);
1741                output = PIN_DIR(cfg);
1742                val = PIN_VAL(cfg);
1743                lowemi = PIN_LOWEMI(cfg);
1744                gpiomode = PIN_GPIOMODE(cfg);
1745                sleep = PIN_SLEEPMODE(cfg);
1746
1747                if (sleep) {
1748                        int slpm_pull = PIN_SLPM_PULL(cfg);
1749                        int slpm_output = PIN_SLPM_DIR(cfg);
1750                        int slpm_val = PIN_SLPM_VAL(cfg);
1751
1752                        /* All pins go into GPIO mode at sleep */
1753                        gpiomode = true;
1754
1755                        /*
1756                         * The SLPM_* values are normal values + 1 to allow zero
1757                         * to mean "same as normal".
1758                         */
1759                        if (slpm_pull)
1760                                pull = slpm_pull - 1;
1761                        if (slpm_output)
1762                                output = slpm_output - 1;
1763                        if (slpm_val)
1764                                val = slpm_val - 1;
1765
1766                        dev_dbg(nmk_chip->chip.dev,
1767                                "pin %d: sleep pull %s, dir %s, val %s\n",
1768                                pin,
1769                                slpm_pull ? pullnames[pull] : "same",
1770                                slpm_output ? (output ? "output" : "input")
1771                                : "same",
1772                                slpm_val ? (val ? "high" : "low") : "same");
1773                }
1774
1775                dev_dbg(nmk_chip->chip.dev,
1776                        "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1777                        pin, cfg, pullnames[pull], slpmnames[slpm],
1778                        output ? "output " : "input",
1779                        output ? (val ? "high" : "low") : "",
1780                        lowemi ? "on" : "off");
1781
1782                clk_enable(nmk_chip->clk);
1783                bit = pin % NMK_GPIO_PER_CHIP;
1784                if (gpiomode)
1785                        /* No glitch when going to GPIO mode */
1786                        __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1787                if (output)
1788                        __nmk_gpio_make_output(nmk_chip, bit, val);
1789                else {
1790                        __nmk_gpio_make_input(nmk_chip, bit);
1791                        __nmk_gpio_set_pull(nmk_chip, bit, pull);
1792                }
1793                /* TODO: isn't this only applicable on output pins? */
1794                __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1795
1796                __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1797                clk_disable(nmk_chip->clk);
1798        } /* for each config */
1799
1800        return 0;
1801}
1802
1803static const struct pinconf_ops nmk_pinconf_ops = {
1804        .pin_config_get = nmk_pin_config_get,
1805        .pin_config_set = nmk_pin_config_set,
1806};
1807
1808static struct pinctrl_desc nmk_pinctrl_desc = {
1809        .name = "pinctrl-nomadik",
1810        .pctlops = &nmk_pinctrl_ops,
1811        .pmxops = &nmk_pinmux_ops,
1812        .confops = &nmk_pinconf_ops,
1813        .owner = THIS_MODULE,
1814};
1815
1816static const struct of_device_id nmk_pinctrl_match[] = {
1817        {
1818                .compatible = "stericsson,stn8815-pinctrl",
1819                .data = (void *)PINCTRL_NMK_STN8815,
1820        },
1821        {
1822                .compatible = "stericsson,db8500-pinctrl",
1823                .data = (void *)PINCTRL_NMK_DB8500,
1824        },
1825        {
1826                .compatible = "stericsson,db8540-pinctrl",
1827                .data = (void *)PINCTRL_NMK_DB8540,
1828        },
1829        {},
1830};
1831
1832static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state)
1833{
1834        struct nmk_pinctrl *npct;
1835
1836        npct = platform_get_drvdata(pdev);
1837        if (!npct)
1838                return -EINVAL;
1839
1840        return pinctrl_force_sleep(npct->pctl);
1841}
1842
1843static int nmk_pinctrl_resume(struct platform_device *pdev)
1844{
1845        struct nmk_pinctrl *npct;
1846
1847        npct = platform_get_drvdata(pdev);
1848        if (!npct)
1849                return -EINVAL;
1850
1851        return pinctrl_force_default(npct->pctl);
1852}
1853
1854static int nmk_pinctrl_probe(struct platform_device *pdev)
1855{
1856        const struct platform_device_id *platid = platform_get_device_id(pdev);
1857        struct device_node *np = pdev->dev.of_node;
1858        struct device_node *prcm_np;
1859        struct nmk_pinctrl *npct;
1860        struct resource *res;
1861        unsigned int version = 0;
1862        int i;
1863
1864        npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1865        if (!npct)
1866                return -ENOMEM;
1867
1868        if (platid)
1869                version = platid->driver_data;
1870        else if (np) {
1871                const struct of_device_id *match;
1872
1873                match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1874                if (!match)
1875                        return -ENODEV;
1876                version = (unsigned int) match->data;
1877        }
1878
1879        /* Poke in other ASIC variants here */
1880        if (version == PINCTRL_NMK_STN8815)
1881                nmk_pinctrl_stn8815_init(&npct->soc);
1882        if (version == PINCTRL_NMK_DB8500)
1883                nmk_pinctrl_db8500_init(&npct->soc);
1884        if (version == PINCTRL_NMK_DB8540)
1885                nmk_pinctrl_db8540_init(&npct->soc);
1886
1887        if (np) {
1888                prcm_np = of_parse_phandle(np, "prcm", 0);
1889                if (prcm_np)
1890                        npct->prcm_base = of_iomap(prcm_np, 0);
1891        }
1892
1893        /* Allow platform passed information to over-write DT. */
1894        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1895        if (res)
1896                npct->prcm_base = devm_ioremap(&pdev->dev, res->start,
1897                                               resource_size(res));
1898        if (!npct->prcm_base) {
1899                if (version == PINCTRL_NMK_STN8815) {
1900                        dev_info(&pdev->dev,
1901                                 "No PRCM base, "
1902                                 "assuming no ALT-Cx control is available\n");
1903                } else {
1904                        dev_err(&pdev->dev, "missing PRCM base address\n");
1905                        return -EINVAL;
1906                }
1907        }
1908
1909        /*
1910         * We need all the GPIO drivers to probe FIRST, or we will not be able
1911         * to obtain references to the struct gpio_chip * for them, and we
1912         * need this to proceed.
1913         */
1914        for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1915                if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) {
1916                        dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1917                        return -EPROBE_DEFER;
1918                }
1919                npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip;
1920        }
1921
1922        nmk_pinctrl_desc.pins = npct->soc->pins;
1923        nmk_pinctrl_desc.npins = npct->soc->npins;
1924        npct->dev = &pdev->dev;
1925
1926        npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
1927        if (!npct->pctl) {
1928                dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1929                return -EINVAL;
1930        }
1931
1932        /* We will handle a range of GPIO pins */
1933        for (i = 0; i < npct->soc->gpio_num_ranges; i++)
1934                pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
1935
1936        platform_set_drvdata(pdev, npct);
1937        dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1938
1939        return 0;
1940}
1941
1942static const struct of_device_id nmk_gpio_match[] = {
1943        { .compatible = "st,nomadik-gpio", },
1944        {}
1945};
1946
1947static struct platform_driver nmk_gpio_driver = {
1948        .driver = {
1949                .owner = THIS_MODULE,
1950                .name = "gpio",
1951                .of_match_table = nmk_gpio_match,
1952        },
1953        .probe = nmk_gpio_probe,
1954};
1955
1956static const struct platform_device_id nmk_pinctrl_id[] = {
1957        { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1958        { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1959        { "pinctrl-db8540", PINCTRL_NMK_DB8540 },
1960        { }
1961};
1962
1963static struct platform_driver nmk_pinctrl_driver = {
1964        .driver = {
1965                .owner = THIS_MODULE,
1966                .name = "pinctrl-nomadik",
1967                .of_match_table = nmk_pinctrl_match,
1968        },
1969        .probe = nmk_pinctrl_probe,
1970        .id_table = nmk_pinctrl_id,
1971#ifdef CONFIG_PM
1972        .suspend = nmk_pinctrl_suspend,
1973        .resume = nmk_pinctrl_resume,
1974#endif
1975};
1976
1977static int __init nmk_gpio_init(void)
1978{
1979        int ret;
1980
1981        ret = platform_driver_register(&nmk_gpio_driver);
1982        if (ret)
1983                return ret;
1984        return platform_driver_register(&nmk_pinctrl_driver);
1985}
1986
1987core_initcall(nmk_gpio_init);
1988
1989MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1990MODULE_DESCRIPTION("Nomadik GPIO Driver");
1991MODULE_LICENSE("GPL");
1992
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