linux/drivers/pinctrl/pinctrl-coh901.c
<<
i2nvv4./spa > v4./form > v4.a i2nvv4 href="../linux+v3=1v4./drivers/pinctrl/pinctrl-coh901.c">i2nvv4.img src="../.static/gfx/right.png" alt=">>">i2./spa >i2.spa class="lxr_search">i2nvi2nvv4.input typl2 hidden" naml2 navtarget" 2nval2 ">i2nvv4.input typl2 text" naml2 search" id2 search">i2nvv4.butt/optypl2 submit">Search v4./form > ./spa >i2.spa class="lxr_prefs" > v4.a href="+prefs?return=drivers/pinctrl/pinctrl-coh901.c"i2nvv4 onclick="return ajax_prefs();">i2nvv4Prefs> v4./a>i2./spa >nvv4 4./div >nvv4 4.form ac" ="ajax+*" method="post" onsubmit="return false;">i2.input typl2 hidden" naml2 ajax_lookup" id2 ajax_lookup" 2nval2 ">invv4 4./form >invv4 4.div class="headingbott/m">
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4 41./a>.spa  class="comment">/*./spa  >4 42./a>.spa  class="comment"> * U300 GPIO module../spa  >4 43./a>.spa  class="comment"> *./spa  >4 44./a>.spa  class="comment"> * Copyright (C) 2007-2012 ST-Ericss/opAB./spa  >4 45./a>.spa  class="comment"> * License terms: GNU General Public License (GPL) vers4 46./a>.spa  class="comment"> * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)./spa  >4 47./a>.spa  class="comment"> * Author: Linus Walleij <linus.walleij@linaro.org>./spa  >4 48./a>.spa  class="comment"> * Author: Jonas Aaberg <jonas.aberg@stericss/o.com>./spa  >4 49./a>.spa  class="comment"> */./spa  >4 4.29a>#include <linux/module.h29a>>>4 1129a>#include <linux/irq.h29a>>>4 1229a>#include <linux/interrupt.h29a>>>4 1329a>#include <linux/delay.h29a>>>4 1429a>#include <linux/errno.h29a>>>4 1529a>#include <linux/io.h29a>>>4 1629a>#include <linux/irqdomain.h29a>>>4 1729a>#include <linux/clk.h29a>>>4 1829a>#include <linux/err.h29a>>>4 1929a>#include <linux/platform_device.h29a>>>4 2.29a>#include <linux/gpio.h29a>>>4 2129a>#include <linux/list.h29a>>>4 2229a>#include <linux/slab.h29a>>>4 2329a>#include <linux/pinctrl/consumer.h29a>>>4 2429a>#include <linux/pinctrl/pinconf-generic.h29a>>>4 2529a>#include "pinctrl-coh901.h29a>">4 2629a>>4 2729a>#define4.a href="+code=U300_GPIO_PORT_STRIDE" class="sref">U300_GPIO_PORT_STRIDE29a>                           (0x30)>4 28./a>.spa  class="comment">/*./spa  >4 29./a>.spa  class="comment"> * Control Register 32bit (R/W)./spa  >4 30./a>.spa  class="comment"> * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores./spa  >4 31./a>.spa  class="comment"> * gives the number of GPIO pins../spa  >4 32./a>.spa  class="comment"> * bit 8-2  (mask 0x000001FC) contains the core vers4 33./a>.spa  class="comment"> */./spa  >4 3429a>#define4.a href="+code=U300_GPIO_CR" class="sref">U300_GPIO_CR29a>                                    (0x00)>4 3529a>#define4.a href="+code=U300_GPIO_CR_SYNC_SEL_ENABLE" class="sref">U300_GPIO_CR_SYNC_SEL_ENABLE29a>                    (0x00000002UL)>4 3629a>#define4.a href="+code=U300_GPIO_CR_BLOCK_CLKRQ_ENABLE" class="sref">U300_GPIO_CR_BLOCK_CLKRQ_ENABLE29a>                 (0x00000001UL)>4 3729a>#define4.a href="+code=U300_GPIO_PXPDIR" class="sref">U300_GPIO_PXPDIR29a>                                (0x04)>4 3829a>#define4.a href="+code=U300_GPIO_PXPDOR" class="sref">U300_GPIO_PXPDOR29a>                                (0x08)>4 3929a>#define4.a href="+code=U300_GPIO_PXPCR" class="sref">U300_GPIO_PXPCR29a>                                 (0x0C)>4 4029a>#define4.a href="+code=U300_GPIO_PXPCR_ALL_PINS_MODE_MASK" class="sref">U300_GPIO_PXPCR_ALL_PINS_MODE_MASK29a>              (0x0000FFFFUL)>4 4129a>#define4.a href="+code=U300_GPIO_PXPCR_PIN_MODE_MASK" class="sref">U300_GPIO_PXPCR_PIN_MODE_MASK29a>                   (0x00000003UL)>4 4229a>#define4.a href="+code=U300_GPIO_PXPCR_PIN_MODE_SHIFT" class="sref">U300_GPIO_PXPCR_PIN_MODE_SHIFT29a>                  (0x00000002UL)>4 4329a>#define4.a href="+code=U300_GPIO_PXPCR_PIN_MODE_INPUT" class="sref">U300_GPIO_PXPCR_PIN_MODE_INPUT29a>                  (0x00000000UL)>4 4429a>#define4.a href="+code=U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL" class="sref">U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL29a>       (0x00000001UL)>4 4529a>#define4.a href="+code=U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN" class="sref">U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN29a>      (0x00000002UL)>4 4629a>#define4.a href="+code=U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE" class="sref">U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE29a>     (0x00000003UL)>4 4729a>#define4.a href="+code=U300_GPIO_PXPER" class="sref">U300_GPIO_PXPER29a>                                 (0x10)>4 4829a>#define4.a href="+code=U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK" class="sref">U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK29a>        (0x000000FFUL)>4 4929a>#define4.a href="+code=U300_GPIO_PXPER_PULL_UP_DISABLE" class="sref">U300_GPIO_PXPER_PULL_UP_DISABLE29a>                 (0x00000001UL)>4 5029a>#define4.a href="+code=U300_GPIO_PXIEV" class="sref">U300_GPIO_PXIEV29a>                                 (0x14)>4 5129a>#define4.a href="+code=U300_GPIO_PXIEN" class="sref">U300_GPIO_PXIEN29a>                                 (0x18)>4 5229a>#define4.a href="+code=U300_GPIO_PXIFR" class="sref">U300_GPIO_PXIFR29a>                                 (0x1C)>4 5329a>#define4.a href="+code=U300_GPIO_PXICR" class="sref">U300_GPIO_PXICR29a>                                 (0x20)>4 5429a>#define4.a href="+code=U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK" class="sref">U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK29a>             (0x000000FFUL)>4 5529a>#define4.a href="+code=U300_GPIO_PXICR_IRQ_CONFIG_MASK" class="sref">U300_GPIO_PXICR_IRQ_CONFIG_MASK29a>                 (0x00000001UL)>4 5629a>#define4.a href="+code=U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE" class="sref">U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE29a>         (0x00000000UL)>4 5729a>#define4.a href="+code=U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE" class="sref">U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE29a>          (0x00000001UL)>4 5829a>>4 59./a>.spa  class="comment">/* 8 bits per port, no vers4 6029a>#define4.a href="+code=U300_GPIO_NUM_PORTS" class="sref">U300_GPIO_NUM_PORTS29a> 7>4 6129a>#define4.a href="+code=U300_GPIO_PINS_PER_PORT" class="sref">U300_GPIO_PINS_PER_PORT29a> 8>4 6229a>#define4.a href="+code=U300_GPIO_MAX" class="sref">U300_GPIO_MAX29a> (.a href="+code=U300_GPIO_PINS_PER_PORT" class="sref">U300_GPIO_PINS_PER_PORT29a> *4.a href="+code=U300_GPIO_NUM_PORTS" class="sref">U300_GPIO_NUM_PORTS29a>)>4 6329a>>4 6429a>struct4.a href="+code=u300_gpio" class="sref">u300_gpio29a> {>4 6529a>        struct4.a href="+code=gpio_chip" class="sref">gpio_chip29a> .a href="+code=chip" class="sref">chip29a>;>4 6629a>        struct4.a href="+code=list_head" class="sref">list_head29a> .a href="+code=port_list" class="sref">port_list29a>;>4 6729a>        struct4.a href="+code=clk" class="sref">clk29a> *.a href="+code=clk" class="sref">clk29a>;>4 6829a>        void4.a href="+code=__iomem" class="sref">__iomem29a> *.a href="+code=base" class="sref">base29a>;>4 6929a>        struct4.a href="+code=device" class="sref">device29a> *.a href="+code=dev" class="sref">dev29a>;>4 7029a>        .a href="+code=u32" class="sref">u3229a> .a href="+code=stride" class="sref">stride29a>;>4 7129a>        .spa  class="comment">/* Register offsets */./spa  >4 7229a>        .a href="+code=u32" class="sref">u3229a> .a href="+code=pcr" class="sref">pcr29a>;>4 7329a>        .a href="+code=u32" class="sref">u3229a> .a href="+code=dor" class="sref">dor29a>;>4 7429a>        .a href="+code=u32" class="sref">u3229a> .a href="+code=dir" class="sref">dir29a>;>4 7529a>        .a href="+code=u32" class="sref">u3229a> .a href="+code=per" class="sref">per29a>;>4 7629a>        .a href="+code=u32" class="sref">u3229a> .a href="+code=icr" class="sref">icr29a>;>4 7729a>        .a href="+code=u32" class="sref">u3229a> .a href="+code=ien" class="sref">ien29a>;>4 7829a>        .a href="+code=u32" class="sref">u3229a> .a href="+code=iev" class="sref">iev29a>;>4 7929a>};>4 8029a>>4 8129a>struct4.a href="+code=u300_gpio_port" class="sref">u300_gpio_port29a> {>4 8229a>        struct4.a href="+code=list_head" class="sref">list_head29a> .a href="+code=node" class="sref">node29a>;>4 8329a>        struct4.a href="+code=u300_gpio" class="sref">u300_gpio29a> *.a href="+code=gpio" class="sref">gpio29a>;>4 8429a>        char .a href="+code=naml" class="sref">naml29a>[8];>4 8529a>        struct4.a href="+code=irq_domain" class="sref">irq_domain29a> *.a href="+code=domain" class="sref">domain29a>;>4 8629a>        int4.a href="+code=irq" class="sref">irq29a>;>4 8729a>        int4.a href="+code=number" class="sref">number29a>;>4 8829a>        .a href="+code=u8" class="sref">u829a> .a href="+code=toggle_edge_mode" class="sref">toggle_edge_mode29a>;>4 8929a>};>4 9029a>>4 91./a>.spa  class="comment">/*./spa  >4 92./a>.spa  class="comment"> * Macro to expand to read a specific register found in the "gpio"4 93./a>.spa  class="comment"> * struct. It requires the struct4u300_gpio *gpio variable to exist in29spa  >4 94./a>.spa  class="comment"> * its context. It calculates the port offset from the given pin29spa  >4 95./a>.spa  class="comment"> * offset, muliplies by the port stride and adds the register offset29spa  >4 96./a>.spa  class="comment"> * so it provides a pointer to the desired register../spa  >4 97./a>.spa  class="comment"> */./spa  >4 9829a>#define4.a href="+code=U300_PIN_REG" class="sref">U300_PIN_REG29a>(.a href="+code=pin" class="sref">pin29a>,4.a href="+code=reg" class="sref">reg29a>) \>4 9929a>        (.a href="+code=gpio" class="sref">gpio29a>->.a href="+code=base" class="sref">base29a> + (.a href="+code=pin" class="sref">pin29a> >> 3) *4.a href="+code=gpio" class="sref">gpio29a>->.a href="+code=stride" class="sref">stride29a> + .a href="+code=gpio" class="sref">gpio29a>->.a href="+code=reg" class="sref">reg29a>)>410029a>>4101./a>.spa  class="comment">/*./spa  >4102./a>.spa  class="comment"> * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO./spa  >4103./a>.spa  class="comment"> * register../spa  >4104./a>.spa  class="comment"> */./spa  >410529a>#define4.a href="+code=U300_PIN_BIT" class="sref">U300_PIN_BIT29a>(.a href="+code=pin" class="sref">pin29a>) \>410629a>        (1 << (.a href="+code=pin" class="sref">pin29a> & 0x07))>410729a>>410829a>struct4.a href="+code=u300_gpio_confdata" class="sref">u300_gpio_confdata29a> {>410929a>        .a href="+code=u16" class="sref">u1629a> .a href="+code=bias_mode" class="sref">bias_mode29a>;>411029a>        .a href="+code=bool" class="sref">bool29a> .a href="+code=output" class="sref">output29a>;>411129a>        int4.a href="+code=outval" class="sref">outval29a>;>411229a>};>411329a>>411429a>#define4.a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a> { \>411529a>        ..a href="+code=bias_mode" class="sref">bias_mode29a> =4.a href="+code=PIN_CONFIG_BIAS_HIGH_IMPEDANCE" class="sref">PIN_CONFIG_BIAS_HIGH_IMPEDANCE29a>,4\>411629a>        ..a href="+code=output" class="sref">output29a> =4.a href="+code=false" class="sref">false29a>,4\>411729a>}>411829a>>411929a>#define4.a href="+code=U300_PULL_UP_INPUT" class="sref">U300_PULL_UP_INPUT29a> { \>412029a>        ..a href="+code=bias_mode" class="sref">bias_mode29a> =4.a href="+code=PIN_CONFIG_BIAS_PULL_UP" class="sref">PIN_CONFIG_BIAS_PULL_UP29a>,4\>412129a>        ..a href="+code=output" class="sref">output29a> =4.a href="+code=false" class="sref">false29a>,4\>412229a>}>412329a>>412429a>#define4.a href="+code=U300_OUTPUT_LOW" class="sref">U300_OUTPUT_LOW29a> { \>412529a>        ..a href="+code=output" class="sref">output29a> =4.a href="+code=true" class="sref">true29a>,4\>412629a>        ..a href="+code=outval" class="sref">outval29a> =40,4\>412729a>}>412829a>>412929a>#define4.a href="+code=U300_OUTPUT_HIGH" class="sref">U300_OUTPUT_HIGH29a> { \>413029a>        ..a href="+code=output" class="sref">output29a> =4.a href="+code=true" class="sref">true29a>,4\>413129a>        ..a href="+code=outval" class="sref">outval29a> =41,4\>413229a>}>413329a>>4134./a>.spa  class="comment">/* Initial configura2413529a>static const struct4.a href="+code=__initconst" class="sref">__initconst29a> .a href="+code=u300_gpio_confdata" class="sref">u300_gpio_confdata29a>>413629a>.a href="+code=bs335_gpio_config" class="sref">bs335_gpio_config29a>[.a href="+code=U300_GPIO_NUM_PORTS" class="sref">U300_GPIO_NUM_PORTS29a>][.a href="+code=U300_GPIO_PINS_PER_PORT" class="sref">U300_GPIO_PINS_PER_PORT29a>] =4{>413729a>        .spa  class="comment">/* Port 0,4pins 0-7p*/./spa  >413829a>        {>413929a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>414029a>                .a href="+code=U300_OUTPUT_HIGH" class="sref">U300_OUTPUT_HIGH29a>,>414129a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>414229a>                .a href="+code=U300_OUTPUT_LOW" class="sref">U300_OUTPUT_LOW29a>,>414329a>                .a href="+code=U300_OUTPUT_LOW" class="sref">U300_OUTPUT_LOW29a>,>414429a>                .a href="+code=U300_OUTPUT_LOW" class="sref">U300_OUTPUT_LOW29a>,>414529a>                .a href="+code=U300_OUTPUT_LOW" class="sref">U300_OUTPUT_LOW29a>,>414629a>                .a href="+code=U300_OUTPUT_LOW" class="sref">U300_OUTPUT_LOW29a>,>414729a>        },>414829a>        .spa  class="comment">/* Port 1,4pins 0-7p*/./spa  >414929a>        {>415029a>                .a href="+code=U300_OUTPUT_LOW" class="sref">U300_OUTPUT_LOW29a>,>415129a>                .a href="+code=U300_OUTPUT_LOW" class="sref">U300_OUTPUT_LOW29a>,>415229a>                .a href="+code=U300_OUTPUT_LOW" class="sref">U300_OUTPUT_LOW29a>,>415329a>                .a href="+code=U300_PULL_UP_INPUT" class="sref">U300_PULL_UP_INPUT29a>,>415429a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>415529a>                .a href="+code=U300_OUTPUT_HIGH" class="sref">U300_OUTPUT_HIGH29a>,>415629a>                .a href="+code=U300_OUTPUT_LOW" class="sref">U300_OUTPUT_LOW29a>,>415729a>                .a href="+code=U300_OUTPUT_LOW" class="sref">U300_OUTPUT_LOW29a>,>415829a>        },>415929a>        .spa  class="comment">/* Port 2,4pins 0-7p*/./spa  >416029a>        {>416129a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>416229a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>416329a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>416429a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>416529a>                .a href="+code=U300_OUTPUT_LOW" class="sref">U300_OUTPUT_LOW29a>,>416629a>                .a href="+code=U300_PULL_UP_INPUT" class="sref">U300_PULL_UP_INPUT29a>,>416729a>                .a href="+code=U300_OUTPUT_LOW" class="sref">U300_OUTPUT_LOW29a>,>416829a>                .a href="+code=U300_PULL_UP_INPUT" class="sref">U300_PULL_UP_INPUT29a>,>416929a>        },>417029a>        .spa  class="comment">/* Port 3,4pins 0-7p*/./spa  >417129a>        {>417229a>                .a href="+code=U300_PULL_UP_INPUT" class="sref">U300_PULL_UP_INPUT29a>,>417329a>                .a href="+code=U300_OUTPUT_LOW" class="sref">U300_OUTPUT_LOW29a>,>417429a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>417529a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>417629a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>417729a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>417829a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>417929a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>418029a>        },>418129a>        .spa  class="comment">/* Port 4,4pins 0-7p*/./spa  >418229a>        {>418329a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>418429a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>418529a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>418629a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>418729a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>418829a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>418929a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>419029a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>419129a>        },>419229a>        .spa  class="comment">/* Port 5,4pins 0-7p*/./spa  >419329a>        {>419429a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>419529a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>419629a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>419729a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>419829a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>419929a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>420029a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>420129a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>420229a>        },>420329a>        .spa  class="comment">/* Port 6,4pind 0-7p*/./spa  >420429a>        {>420529a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>420629a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>420729a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>420829a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>420929a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>421029a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>421129a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>421229a>                .a href="+code=U300_FLOATING_INPUT" class="sref">U300_FLOATING_INPUT29a>,>421329a>        }>421429a>};>421529a>>4216./a>.spa  class="comment">/**./spa  >4217./a>.spa  class="comment"> * to_u300_gpio() - get the pointer to u300_gpio./spa  >4218./a>.spa  class="comment"> * @chip: the gpio chip member of the structure u300_gpio./spa  >4219./a>.spa  class="comment"> */./spa  >422029a>static .a href="+code=inline" class="sref">inline29a> struct4.a href="+code=u300_gpio" class="sref">u300_gpio29a> *.a href="+code=to_u300_gpio" class="sref">to_u300_gpio29a>(struct4.a href="+code=gpio_chip" class="sref">gpio_chip29a> *.a href="+code=chip" class="sref">chip29a>)>422129a>{>422229a>        return4.a href="+code=container_of" class="sref">container_of29a>(.a href="+code=chip" class="sref">chip29a>, struct4.a href="+code=u300_gpio" class="sref">u300_gpio29a>,4.a href="+code=chip" class="sref">chip29a>);>422329a>}>422429a>>422529a>static int4.a href="+code=u300_gpio_request" class="sref">u300_gpio_request29a>(struct4.a href="+code=gpio_chip" class="sref">gpio_chip29a> *.a href="+code=chip" class="sref">chip29a>, unsigned4.a href="+code=offset" class="sref">offset29a>)>422629a>{>422729a>        .spa  class="comment">/*./spa  >4228./a>.spa  class="comment">         * Map back to global GPIO space and request muxing, the direc24229./a>.spa  class="comment">         * paramlter does not matter for this controller../spa  >423029a>.spa  class="comment">         */./spa  >423129a>        int4.a href="+code=gpio" class="sref">gpio29a> =4.a href="+code=chip" class="sref">chip29a>->.a href="+code=base" class="sref">base29a> + .a href="+code=offset" class="sref">offset29a>;>423229a>>423329a>        return4.a href="+code=pinctrl_request_gpio" class="sref">pinctrl_request_gpio29a>(.a href="+code=gpio" class="sref">gpio29a>);>4234./a>}>423529a>>423629a>static void4.a href="+code=u300_gpio_free" class="sref">u300_gpio_free29a>(struct4.a href="+code=gpio_chip" class="sref">gpio_chip29a> *.a href="+code=chip" class="sref">chip29a>, unsigned4.a href="+code=offset" class="sref">offset29a>)>423729a>{>423829a>        int4.a href="+code=gpio" class="sref">gpio29a> =4.a href="+code=chip" class="sref">chip29a>->.a href="+code=base" class="sref">base29a> + .a href="+code=offset" class="sref">offset29a>;>423929a>>424029a>        .a href="+code=pinctrl_free_gpio" class="sref">pinctrl_free_gpio29a>(.a href="+code=gpio" class="sref">gpio29a>);>424129a>}>424229a>>424329a>static int4.a href="+code=u300_gpio_get" class="sref">u300_gpio_get29a>(struct4.a href="+code=gpio_chip" class="sref">gpio_chip29a> *.a href="+code=chip" class="sref">chip29a>, unsigned4.a href="+code=offset" class="sref">offset29a>)>424429a>{>424529a>        struct4.a href="+code=u300_gpio" class="sref">u300_gpio29a> *.a href="+code=gpio" class="sref">gpio29a> =4.a href="+code=to_u300_gpio" class="sref">to_u300_gpio29a>(.a href="+code=chip" class="sref">chip29a>);>424629a>>424729a>        return4.a href="+code=readl" class="sref">readl29a>(.a href="+code=U300_PIN_REG" class="sref">U300_PIN_REG29a>(.a href="+code=offset" class="sref">offset29a>,4.a href="+code=dir" class="sref">dir29a>)) & .a href="+code=U300_PIN_BIT" class="sref">U300_PIN_BIT29a>(.a href="+code=offset" class="sref">offset29a>);>424829a>}>424929a>>425029a>static void4.a href="+code=u300_gpio_set" class="sref">u300_gpio_set29a>(struct4.a href="+code=gpio_chip" class="sref">gpio_chip29a> *.a href="+code=chip" class="sref">chip29a>, unsigned4.a href="+code=offset" class="sref">offset29a>, int4.a href="+code=value" class="sref">value29a>)>425129a>{>425229a>        struct4.a href="+code=u300_gpio" class="sref">u300_gpio29a> *.a href="+code=gpio" class="sref">gpio29a> =4.a href="+code=to_u300_gpio" class="sref">to_u300_gpio29a>(.a href="+code=chip" class="sref">chip29a>);>425329a>        unsigned4long4.a href="+code=flags" class="sref">flags29a>;>425429a>        .a href="+code=u32" class="sref">u3229a> .a href="+code=val" class="sref">val29a>;>425529a>>425629a>        .a href="+code=local_irq_save" class="sref">local_irq_save29a>(.a href="+code=flags" class="sref">flags29a>);>425729a>>425829a>        .a href="+code=val" class="sref">val29a> =4.a href="+code=readl" class="sref">readl29a>(.a href="+code=U300_PIN_REG" class="sref">U300_PIN_REG29a>(.a href="+code=offset" class="sref">offset29a>,4.a href="+code=dor" class="sref">dor29a>));>425929a>        if (.a href="+code=value" class="sref">value29a>)>426029a>                .a href="+code=writel" class="sref">writel29a>(.a href="+code=val" class="sref">val29a> | .a href="+code=U300_PIN_BIT" class="sref">U300_PIN_BIT29a>(.a href="+code=offset" class="sref">offset29a>),4.a href="+code=U300_PIN_REG" class="sref">U300_PIN_REG29a>(.a href="+code=offset" class="sref">offset29a>,4.a href="+code=dor" class="sref">dor29a>));>426129a>        else>426229a>                .a href="+code=writel" class="sref">writel29a>(.a href="+code=val" class="sref">val29a> & ~.a href="+code=U300_PIN_BIT" class="sref">U300_PIN_BIT29a>(.a href="+code=offset" class="sref">offset29a>),4.a href="+code=U300_PIN_REG" class="sref">U300_PIN_REG29a>(.a href="+code=offset" class="sref">offset29a>,4.a href="+code=dor" class="sref">dor29a>));>426329a>>426429a>        .a href="+code=local_irq_restore" class="sref">local_irq_restore29a>(.a href="+code=flags" class="sref">flags29a>);>426529a>}>426629a>>426729a>static int4.a href="+code=u300_gpio_direc2u300_gpio_direc2(struct4.a href="+code=gpio_chip" class="sref">gpio_chip29a> *.a href="+code=chip" class="sref">chip29a>, unsigned4.a href="+code=offset" class="sref">offset29a>)>426829a>{>426929a>        struct4.a href="+code=u300_gpio" class="sref">u300_gpio29a> *.a href="+code=gpio" class="sref">gpio29a> =4.a href="+code=to_u300_gpio" class="sref">to_u300_gpio29a>(.a href="+code=chip" class="sref">chip29a>);>427029a>        unsigned4long4.a href="+code=flags" class="sref">flags29a>;>427129a>        .a href="+code=u32" class="sref">u3229a> .a href="+code=val" class="sref">val29a>;>427229a>>427329a>        .a href="+code=local_irq_save" class="sref">local_irq_save29a>(.a href="+code=flags" class="sref">flags29a>);>427429a>        .a href="+code=val" class="sref">val29a> =4.a href="+code=readl" class="sref">readl29a>(.a href="+code=U300_PIN_REG" class="sref">U300_PIN_REG29a>(.a href="+code=offset" class="sref">offset29a>,4.a href="+code=pcr" class="sref">pcr29a>));>427529a>        .spa  class="comment">/* Mask out this pin, note 2 bits per setting4*/./spa  >427629a>        .a href="+code=val" class="sref">val29a> &= ~(.a href="+code=U300_GPIO_PXPCR_PIN_MODE_MASK" class="sref">U300_GPIO_PXPCR_PIN_MODE_MASK29a> << ((.a href="+code=offset" class="sref">offset29a> & 0x07) << 1));>427729a>        .a href="+code=writel" class="sref">writel29a>(.a href="+code=val" class="sref">val29a>,4.a href="+code=U300_PIN_REG" class="sref">U300_PIN_REG29a>(.a href="+code=offset" class="sref">offset29a>,4.a href="+code=pcr" class="sref">pcr29a>));>427829a>        .a href="+code=local_irq_restore" class="sref">local_irq_restore29a>(.a href="+code=flags" class="sref">flags29a>);>427929a>        return40;>428029a>}>428129a>>428229a>static int4.a href="+code=u300_gpio_direc2u300_gpio_direc2(struct4.a href="+code=gpio_chip" class="sref">gpio_chip29a> *.a href="+code=chip" class="sref">chip29a>, unsigned4.a href="+code=offset" class="sref">offset29a>,>428329a>                                      int4.a href="+code=value" class="sref">value29a>)>428429a>{>428529a>        struct4.a href="+code=u300_gpio" class="sref">u300_gpio29a> *.a href="+code=gpio" class="sref">gpio29a> =4.a href="+code=to_u300_gpio" class="sref">to_u300_gpio29a>(.a href="+code=chip" class="sref">chip29a>);>428629a>        unsigned4long4.a href="+code=flags" class="sref">flags29a>;>428729a>        .a href="+code=u32" class="sref">u3229a> .a href="+code=oldmode" class="sref">oldmode29a>;>428829a>        .a href="+code=u32" class="sref">u3229a> .a href="+code=val" class="sref">val29a>;>428929a>>429029a>        .a href="+code=local_irq_save" class="sref">local_irq_save29a>(.a href="+code=flags" class="sref">flags29a>);>429129a>        .a href="+code=val" class="sref">val29a> =4.a href="+code=readl" class="sref">readl29a>(.a href="+code=U300_PIN_REG" class="sref">U300_PIN_REG29a>(.a href="+code=offset" class="sref">offset29a>,4.a href="+code=pcr" class="sref">pcr29a>));>429229a>        .spa  class="comment">/*./spa  >429329a>.spa  class="comment">         * Drive mode must be set by the special mode set func24294./a>.spa  class="comment">         * push/pull mode by default if no mode has been selec2ed../spa  >429529a>.spa  class="comment">         */./spa  >429629a>        .a href="+code=oldmode" class="sref">oldmode29a> =4.a href="+code=val" class="sref">val29a> & (.a href="+code=U300_GPIO_PXPCR_PIN_MODE_MASK" class="sref">U300_GPIO_PXPCR_PIN_MODE_MASK29a> <<>429729a>                         ((.a href="+code=offset" class="sref">offset29a> & 0x07) << 1));>429829a>        .spa  class="comment">/* mode = 0 means input, else some mode is already set */./spa  >429929a>        if (.a href="+code=oldmode" class="sref">oldmode29a> == 0) {>430029a>                .a href="+code=val" class="sref">val29a> &= ~(.a href="+code=U300_GPIO_PXPCR_PIN_MODE_MASK" class="sref">U300_GPIO_PXPCR_PIN_MODE_MASK29a> <<>430129a>                         ((.a href="+code=offset" class="sref">offset29a> & 0x07) << 1));>430229a>                .a href="+code=val" class="sref">val29a> |= (.a href="+code=U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL" class="sref">U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL29a>>430329a>                        << ((.a href="+code=offset" class="sref">offset29a> & 0x07) << 1));>430429a>                .a href="+code=writel" class="sref">writel29a>(.a href="+code=val" class="sref">val29a>,4.a href="+code=U300_PIN_REG" class="sref">U300_PIN_REG29a>(.a href="+code=offset" class="sref">offset29a>,4.a href="+code=pcr" class="sref">pcr29a>));>430529a>        }>430629a>        .a href="+code=u300_gpio_set" class="sref">u300_gpio_set29a>(.a href="+code=chip" class="sref">chip29a>, .a href="+code=offset" class="sref">offset29a>,4.a href="+code=value" class="sref">value29a>);>430729a>        .a href="+code=local_irq_restore" class="sref">local_irq_restore29a>(.a href="+code=flags" class="sref">flags29a>);>430829a>        return40;>430929a>}>431029a>>431129a>static int4.a href="+code=u300_gpio_to_irq" class="sref">u300_gpio_to_irq29a>(struct4.a href="+code=gpio_chip" class="sref">gpio_chip29a> *.a href="+code=chip" class="sref">chip29a>, unsigned4.a href="+code=offset" class="sref">offset29a>)>431229a>{>431329a>        struct4.a href="+code=u300_gpio" class="sref">u300_gpio29a> *.a href="+code=gpio" class="sref">gpio29a> =4.a href="+code=to_u300_gpio" class="sref">to_u300_gpio29a>(.a href="+code=chip" class="sref">chip29a>);>431429a>        int4.a href="+code=portno" class="sref">portno29a> =4.a href="+code=offset" class="sref">offset29a> >> 3;>431529a>        struct4.a href="+code=u300_gpio_port" class="sref">u300_gpio_port29a> *.a href="+code=port" class="sref">port29a> =4.a href="+code=NULL" class="sref">NULL29a>;>431629a>        struct4.a href="+code=list_head" class="sref">list_head29a> *.a href="+code=p" class="sref">p29a>;>431729a>        int4.a href="+code=retirq" class="sref">retirq29a>;>431829a>        .a href="+code=bool" class="sref">bool29a> .a href="+code=found" class="sref">found29a> =4.a href="+code=false" class="sref">false29a>;>431929a>>432029a>        .a href="+code=list_for_each" class="sref">list_for_each29a>(.a href="+code=p" class="sref">p29a>, &.a href="+code=gpio" class="sref">gpio29a>->.a href="+code=port_list" class="sref">port_list29a>) {>432129a>                .a href="+code=port" class="sref">port29a> =4.a href="+code=list_entry" class="sref">list_entry29a>(.a href="+code=p" class="sref">p29a>, struct4.a href="+code=u300_gpio_port" class="sref">u300_gpio_port29a>,4.a href="+code=node" class="sref">node29a>);>432229a>                if (.a href="+code=port" class="sref">port29a>->.a href="+code=number" class="sref">number29a> == .a href="+code=portno" class="sref">portno29a>) {>432329a>                        .a href="+code=found" class="sref">found29a> =4.a href="+code=true" class="sref">true29a>;>432429a>                        break;>432529a>                }>432629a>        }>432729a>        if (!.a href="+code=found" class="sref">found29a>) {>432829a>                .a href="+code=dev_err" class="sref">dev_err29a>(.a href="+code=gpio" class="sref">gpio29a>->.a href="+code=dev" class="sref">dev29a>,4.spa  class="string">"could not locate port for GPIO %d IRQ\n"./spa  ,>432929a>                        .a href="+code=offset" class="sref">offset29a>);>433029a>                return4-.a href="+code=EINVAL" class="sref">EINVAL29a>;>433129a>        }>433229a>>433329a>        .spa  class="comment">/*./spa  >4334./a>.spa  class="comment">         * The local hwirqs on the port are the lower three bits, there29spa  >433529a>.spa  class="comment">         * are exactly 8 IRQs per port since they are 8-bit29spa  >4336./a>.spa  class="comment">         */./spa  >433729a>        .a href="+code=retirq" class="sref">retirq29a> =4.a href="+code=irq_find_mapping" class="sref">irq_find_mapping29a>(.a href="+code=port" class="sref">port29a>->.a href="+code=domain" class="sref">domain29a>,4(.a href="+code=offset" class="sref">offset29a> & 0x7));>433829a>>433929a>        .a href="+code=dev_dbg" class="sref">dev_dbg29a>(.a href="+code=gpio" class="sref">gpio29a>->.a href="+code=dev" class="sref">dev29a>,4.spa  class="string">"request IRQ for GPIO %d, return4%d from port %d\n"./spa  ,>434029a>                .a href="+code=offset" class="sref">offset29a>,4.a href="+code=retirq" class="sref">retirq29a>,4.a href="+code=port" class="sref">port29a>->.a href="+code=number" class="sref">number29a>);>434129a>        return4.a href="+code=retirq" class="sref">retirq29a>;>434229a>}>434329a>>4344./a>.spa  class="comment">/* Returning4-EINVAL means "supported but not available" */./spa  >434529a>int4.a href="+code=u300_gpio_config_get" class="sref">u300_gpio_config_get29a>(struct4.a href="+code=gpio_chip" class="sref">gpio_chip29a> *.a href="+code=chip" class="sref">chip29a>,>434629a>                         unsigned4.a href="+code=offset" class="sref">offset29a>,>434729a>                         unsigned4long4*.a href="+code=config" class="sref">config29a>)>434829a>{>434929a>        struct4.a href="+code=u300_gpio" class="sref">u300_gpio29a> *.a href="+code=gpio" class="sref">gpio29a> =4.a href="+code=to_u300_gpio" class="sref">to_u300_gpio29a>(.a href="+code=chip" class="sref">chip29a>);>435029a>        enum .a href="+code=pin_config_param" class="sref">pin_config_param29a> .a href="+code=param" class="sref">param29a> = (enum .a href="+code=pin_config_param" class="sref">pin_config_param29a>)4*.a href="+code=config" class="sref">config29a>;>435129a>        .a href="+code=bool" class="sref">bool29a> .a href="+code=biasmode" class="sref">biasmode29a>;>435129a>        .a href="+code=bool" class="sref">bool29a> .a aml2 L207">420729a>                .a href="+code=Uvers/pinctrl/pinctrl-coh901.c#L232" id2 L232" class="line" naml2 L232">423229a>>434529a>int4.a href="+coOney arivers/p;= 9a>mp    s/pi rangestruct4.a href="+code=gpio_chip" class="sref">gpio_chipss="sref"3local_irq_save29a>(.a hr3f="+c355aml2 L253 .a href="+code=booc#L351" id2 L351" c01.c#L351" id2n1" !!" class="sref">p429229a>        .spa  class="comment">/*./spa  >424829a>}>424="+code=param" class="sref">param29a> = (enum .a347" clasinctrl-coh901.c#L257" id3 L25735o_input29a>(struct4.a href="+code=gpio_chip" clas3al29a> =43a href="+code=readl" cla3s="sr35global GPIO space and request muxing,ref">val29a>e tworef="+trl/pinctde=not mshift    sf="+0,1struct4.a href="+code=gpio_chip" class="sref">gpio_chipslass="sreIN_REG29a>(.a href="+cod3=offs3t" class="sref">offset29a>,4.>                .a href="+code"sref">pcr29a>));>429229a>        .spa  class="comment">/*./spa  >429329a>.s3 L260">423029a>                .a 3ref="35uest IRQ for GPIO %d, ret                .a href="+code" naml2 href="drivers/pinctrl/pinctrl-coh901.c#L277" id2 L277" class="line" naml2 L277">427729a>        .a href="+code=writel" class="sref">writel29a>(.a href="+code=val" class="sref">val29a>,4.a href="+code=U300_PIN_REG" class="3 class="s3ef">U300_PIN_BIT29a>(.a 3ref="36rt_list" class="sref">port_lt                .a href="+code" .a href=f="+code=writel" class="sref">writel29a>(.a href="+code=val" class="sref"val29a>,4.a href="+code=U300_PIN_REG" class="3 -coh901.class="sref">writel29a>(.3 href36/o_output29a>(struct4.a href="+code=gpio_chip" cl3_BIT" cla3s="sref">U300_PIN_BIT29a3(.a h3ef="+code=offsswitch-coh901.c#L323" idnctrl-coh901.c#L351" id2 L35class="sref">gpio29a>->.a href="+code=dev" clclass="sr3f">local_irq_restore29a>3.a hr36irqs on the pcasess="sref">port_l77">CONFIGrl-AS_HIGH_IMPEDANCEl-coh901.c#L35177">CONFIGrl-AS_HIGH_IMPEDANCErqs :ss="sref">gpio29a>->.a href="+code=dev" clcpinctrs/pctrl/pinctrl-coh901.c#L235" id36901.c#L326" id2 L326">bool29a> .a href="+code=biasmode" class="sref"de" val29a>,4.a href="+code=U300_PIN_REG" class="3 s="sref"32 L267" class="line" nam32 L2636 class="line" naml2 Lrl-coh901.c#L323" ioc#L351" id2 L351" c01.c#L351" id2n929a>        struct4.a href="+code=u300_gpio" u300_gpio_3irec236                      unsigne310">431029a>>g3io_chip29a> *.a href="+c3de=ch369a>{>val29a> & ~.a href="+code=U300_PI3class="sr3f">u300_gpio29a> *.a hre3="+co36quot;could not locate unsigne310">43l-coh901.c#L332" id2 L332" class="line" naml2 L332">433229a>>to_u300_gpio39a>(.36    return4-.a href="line" naml2 L326">432629a>        }>427129a>        .3 href3"+code=u32" clcasess="sref">port_l77">CONFIGrl-AS_ &am_UPl-coh901.c#L35177">CONFIGrl-AS_ &am_UPrqs :ss="sref">gpio29a>->.a href="+code=dev" cl272" id2 3272" class="line" naml2 3272">37u300_gpio_port" class>bool29a> .a href="+code=biasmode" class="sref"de" val29a>,4.a href="+code=U300_PIN_REG" class="3ss="sref"3local_irq_save29a>(.a hr3f="+c37drivers/pinctrl/pinctrl-class="sref">dev_oc#L351" id2 L351" c01.c#L351" id2n929a>        struct4.a href="+code=u300_gpio" /pinctrl/3inctrl-coh901.c#L274" id3 L27437ss="line" naml2 L324">432429a310">431029a>>U300_3IN_REG29a>(.a href="+cod3=offs37901.c#L326" id2 L326"ass="sref">val29a> & ~.a href="+code=U300_PI3id2 L276"3class="line" naml2 L276"34276237 class="line" naml2 L unsigne310">43l-coh901.c#L332" id2 L332" class="line" naml2 L332">433229a>>432629a>        }>g3PIN_REG29a>(.a href="+co3e=off3et" class="srecasess="sref">port_l77">CONFIGrDRIVE     << ((.a href="77">CONFIGrDRIVE     <&rqs :ss="sref">gpio29a>->.a href="+code=dev" cl2lass="sr3ctrl/pinctrl-coh901.c#L239" id37quot;could not locate>bool29a> .a href="+code=biasmode" class="sref"de" val29a>,4.a href="+code=U300_PIN_REG" class="3s0_gpio" 3coh901.c#L281" id2 L281"3class37    return4-.a href="rl-coh901.c#L323" i>                .a href="+code"ssref">pcr29a>));>03">430329a>                        << ((.a href="+code=offset" class="sref">offset29a> & 0929a>        struct4.a href="+code=u300_gpio" c#L282" i32 L282" class="line" nam32 L2838mber" class="sref">nu>432429a310">431029a>>u300_gpio3direc38u300_gpio_port" classass="sref">val29a> & ~.a href="+code=U300_PI3ss="sref"3gpio_chip29a> *.a href="3code=38drivers/pinctrl/pinct unsigne310">43l-coh901.c#L332" id2 L332" class="line" naml2 L332">433229a>>428329a>{>432629a>        }>u300_gpio29a> *.a hre3="+co384" class="srecasess="sref">port_l77">CONFIGrDRIVE OPENrDRAINlt; ((.a href="77">CONFIGrDRIVE OPENrDRAINrqs :ss="sref">gpio29a>->.a href="+code=dev" cl00_gpio" 3lass="sref">to_u300_gpio39a>(.38 class="line" naml2 L>bool29a> .a href="+code=biasmode" class="sref"de" val29a>,4.a href="+code=U300_PIN_REG" class="3ine" naml3 L287">428729a>        .3 href38                     rl-coh901.c#L323" i>                .a href="+code"ssref">pcr29a>));>03">430329a>                    OPENrDRAINlt; ((.a href="03">430329a>                    OPENrDRAINp; 0929a>        struct4.a href="+code=u300_gpio" c"sref">g38" id2 L288" class="line3 naml389a>{>431029a>>38quot;could not locateass="sref">val29a> & ~.a href="+code=U300_PI3s0_gpio" 3local_irq_save29a>(.a hr3f="+c38    return4-.a href="+code=EI310">43l-coh901.c#L332" id2 L332" class="line" naml2 L332">433229a>>nuline" naml2 L326">432629a>        }>U300_3IN_REG29a>(.a href="+cod3=offs3t" class="srefcasess="sref">port_l77">CONFIGrDRIVE OPENrSOURCEl-coh901.c#L35177">CONFIGrDRIVE OPENrSOURCErqs :ss="sref">gpio29a>->.a href="+code=dev" cla  class=3comment">         * Driv3 mode39drivers/pinctrl/pinct>bool29a> .a href="+code=biasmode" class="sref"de" val29a>,4.a href="+code=U300_PIN_REG" class="3coh901.c#3294" id2 L294" class="li3e" na399a>{>                .a href="+code"ssref">pcr29a>));>03">430329a>                    OPENrSOURCEl-coh901.c#L35103">430329a>                    OPENrSOURCEp; 0929a>        struct4.a href="+code=u300_gpio" 1.c#L295"3id2 L295" class="line" n3ml2 L39901.c#L326" id2 L326" class="310">431029a>>val29a> & ~.a href="+code=U300_PI3PCR_PIN_M3DE_MASK" class="sref">U330_GPI39                      unsigne310">43l-coh901.c#L332" id2 L332" class="line" naml2 L332">433229a>>g398" id2 L298" class="lin3" nam32 L298">429829a>      line" naml2 L326">432629a>        }>429929a>   ref="dr:ss="sref">gpio29a>->.a href="+code=dev" cla0_gpio" 32 L300">430029a>        3     39    return4-.a href="line" naml2 L326">432629a>        }>.spa  class="comment">/* Returning4-EINVA4oh901.c#L402" id2 L302" class="lin4" nam40ctrl/pinctrl-coh901.l-coh901.c#L332" NOTSUPPl-coh901.c#L351 NOTSUPPl2 L332">433229a>>/* Returning4-EINVA4inctrl-co4901.c#L304" id2 L304" cl4ss="l40f="drivers/pinctrl5incU300_PIN_REG29a>(.a h4ef="+4ode=of>,>434629a>                         unsigned4.a href="+code=offset" class="sref">offset29a>,>config29a>)>u300_gpio_set29a4(.a h40 class="line" naml2 L unsigneg_param29a>)4*.a href="+code=config" class="sref">config29a>;>        struct4.a href="+code=u300_gpio"4" class="4ref">offset29a>,4.a href4"+cod4=valueass="sref">gpio29a>->.a href="+code=dev" c4rivers/pi4ctrl/pinctrl-coh901.c#L348" id4 L308" class="hip" class="sref">chip29a>);>435029a>        enum .a href="+code=pin_config_param" class="sref">pin_config_param29a> .a href="+code=param" class="sref">param29a> = (enum 4l/pinctrl4coh901.c#L310" id2 L310"4class4"line" naml2 Lass="sref">u3229a> .a href="+code=oldmode" class="sref">oldmode29a>;>429029a>        .a href="+code=local_irq_save" cl4" class="4ref">u300_gpio_to_irq29a4(stru4t4.a href="+code=gpio_chip" class="sref">gpio_chip49a> *.a h4ef="+code=chip" class="s4ef">c41naml2 L253 .a href="+code=bo129a>        .a href="+code=val" class="sref">val29a> =4.a href="+code=readl" class="sref">readl29a>(.a href="+code=U300_PIN_REG" class="s4class="sr4f">u300_gpio29a> *.a hre4="+co41f="+code=offsswitch-coh901.c#L323" idnctrl-coh901.c#L351" id2 L35class="sref">gpio29a>->.a href="+code=dev" c400_gpio" 4lass="sref">to_u300_gpio49a>(.41irqs on the pcasess="sref">port_l77">CONFIGrl-AS_DISABLEl-coh901.c#L35177">CONFIGrl-AS_DISABLErqs :ss="sref">gpio29a>->.a href="+code=dev" c4rs/pinctr4/pinctrl-coh901.c#L315" 4d2 L3414" class="srecasess="sref">port_l77">CONFIGrl-AS_HIGH_IMPEDANCEl-coh901.c#L35177">CONFIGrl-AS_HIGH_IMPEDANCErqs :ss="sref">gpio29a>->.a href="+code=dev" c4code=NULL4 class="sref">NULL29a>;>4a hre41 class="line" naml2 L id2 L290" class="line" naml2 L290">4290"sref">pcr29a>));>429229a>        .spa  class="comment">/*./spa  >U300_PIN_REG29a>(.a href="+code=offset" class="sref">offset29a>,4.a href="+code=dor" class="sref">dor29a>));>426129a>        else>/*./spa  >429829a>      line" naml2 L326">432629a>        }>port_l77">CONFIGrl-AS_ &am_UPl-coh901.c#L35177">CONFIGrl-AS_ &am_UPrqs :ss="sref">gpio29a>->.a href="+code=dev" c4s="sref">4ist_for_each29a>(.a href4"+cod41    return4-.a href=" id2 L290" class="line" naml2 L290">4290"sref">pcr29a>));>429229a>        .spa  class="comment">/*./spa  >gpio29a>->.a href="4code=42mber" class="sref">number29a>);>),4.a href="+code=U300_PIN_REG" class="sref">U300_PIN_REG29a>(.a href="+code=offset" class="sref">offset29a>,4.a href="+code=dor" class="sref">dor29a>));>426329a>>/*./spa  > *.a h4f">p29a>, struct4.a href4"+cod4=u300_gpio_port" classline" naml2 L326">432629a>        }>portno29a>) {><4 href4"drivers/pinctcasess="sref">port_l77">CONFIGrDRIVE     << ((.a href="77">CONFIGrDRIVE     <&rqs :ss="sref">gpio29a>->.a href="+code=dev" c4nctrl/pin4trl-coh901.c#L324" id2 L424" c4ass="line" naml2 L324" id2 L290" class="line" naml2 L290">4290"sref">pcr29a>));>429229a>        .spa  class="comment">/*./spa  >429329a>.s4    }>U300_PIN_REG29a>(.a href="+co2 L301">430129a>                         ((.a href="+code=offset" class="sref">offset29a> & d2 L293" class="line" naml2 L293">429329a>.s4 ode=NULL4pinctrl-coh901.c#L327" i42 L324" class="line" naml2 LLLLLLLLLL  .a href="+code=writel" class="sref">writel29a>(.a href="+code=val" class="sref">val29a>,4.a href="+code=U300_PIN_REG" class="4" class="4ref">found29a>) {>430329a>                        << ((.a href="+code=offset" class="sref">offset29a> & 0x07) << 1));>                4a hre429a>{>writel29a>(.a href="+code=val" class="sref">val29a>,4.a href="+code=U300_PIN_REG" class="4"lse29a>;4>dev29a>,4.spa  class="s4ring"4"could not locate port for GPIO .a href="+code=pcr" class="sref">pcr29a>));>430529a>        }>430629a>        .a href="+codeG" class="4"="sref">4naml2 L330">433029a>    4     4     return4-.a href="line" naml2 L326">432629a>        }>433129a>     4  }><43+code=u32" clcasess="sref">port_l77">CONFIGrDRIVE OPENrDRAINlt; ((.a href="77">CONFIGrDRIVE OPENrDRAINrqs :ss="sref">gpio29a>->.a href="+code=dev" c4-coh901.c4L333" id2 L333" class="l4ne" n43u300_gpio_port" class="sref">u300_gps="line" naml2 L290">4290"sref">pcr29a>));>429229a>        .spa  class="comment">/*./spa  >4de=dev" c4-tno" cla4vers/pinctrl/pinctrl-coh401.c#43>>430129a>                         ((.a href="+code=offset" class="sref">offset29a> & d2 L293" class="line" naml2 L293">429329a>.s4a  class=4comment">         * The 4ocal 439a>{>writel29a>(.a href="+code=val" class="sref">val29a>,4.a href="+code=U300_PIN_REG" class="4coh901.c#4335" id2 L335" class="li4e" na43901.c#L326" id2 L326"EG" class="sref">U300_PIN_REG29a>(.a hrefass="line" naml2 L303">430329a>                    OPENrDRAINlt; ((.a href="03">430329a>                    OPENrDRAINp; 0al29a>,4.a href="+code=U300_PIN_REG" class="4code=NULL46" class="line" naml2 L346">4343 class="line" naml2 LLLLLLLLL  .a href="+code=writel" class="sref">writel29a>(.a href="+code=val" class="sref">val29a>,4.a href="+code=U300_PIN_REG" class="4c class="4ref="+code=retirq" class4"sref43                     f="drivers/pinc,4.a href="+code=U300_PIN_REG" class="sref">U300_PIN_REG29a>(.a href="+cctrl-coh901.c#L305" id2 L305" class="line" naml2 L305">430529a>        }>430629a>        .a href="+codeG" class="4code=port4 class="sref">port29a>-&4t;.a 43 L298">429829a>      line" naml2 L326">432629a>        }>dev_db429a>(.a href="+code=gpio4 clas43-coh901.c#L31casess="sref">port_l77">CONFIGrDRIVE OPENrSOURCEl-coh901.c#L35177">CONFIGrDRIVE OPENrSOURCErqs :ss="sref">gpio29a>->.a href="+code=dev" c4f">dev29a4,4.spa  class="string">&4uot;r43    return4-.a href=" id2 L290" class="line" naml2 L290">4290"sref">pcr29a>));>429229a>        .spa  class="comment">/*./spa  >430629a>        .a href="+codeG" class="4lass="sre4">port29a>->.a href="4code=4umber" class="sref">number29a>);>430129a>                         ((.a href="+code=offset" class="sref">offset29a> & d2 L293" class="line" naml2 L293">429329a>.s4naml2 L344">434229a>}>430229a>                 .a href="+code=writel" class="sref">writel29a>(.a href="+code=val" class="sref">val29a>,4.a href="+code=U300_PIN_REG" class="4c#L344" i42 L344" class="line" nam42 L3444>>430329a>                    OPENrSOURCEl-coh901.c#L35103">430329a>                    OPENrSOURCEp; 0al29a>,4.a href="+code=U300_PIN_REG" class="4c  class=4ot;supported but not ava4lable44e" naml2 L304">430429a>                .a href="+code=writel" class="sref">writel29a>(.a href="+code=val" class="sref">val29a>,4.a href="+code=U300_PIN_REG"4h901.c#L345" id2 L345" class="line4 naml44de=offset" class="sref">offset29a>,4.a href="+code=pcr" class="sref">pcr29a>));>430529a>        }>val29a>,4.a href="+code=U300_PIN_REG"4hode=NULL4ref="+code=chip" class="4ref">44 class="line" naml2 Lline" naml2 L326">432629a>        }>434429a> 4              ref="dr:ss="sref">gpio29a>->.a href="+code=dev" c4" id2 L344" class="line" naml2 L344">434429a>{>     >        return40;>430929a>}>u300_gpio29a> *.a hre4="+co44quot;could not locate port for GPIO %d IRQ\n"./spa  ,>432929a>                        .a href=illegal 29a>;>ura bee   .a hre"+code=retirq" c" naml2 L309">430929a>}>dev29a4lass="sref">to_u300_gpio49a>(.44    return4-.a href="310">43l-coh901.c#L332" id2 L332" class="line" naml2 L332">433229a>>.spa  class="comment">/* Returning4-EINVA4l-coh901.4#L351" id2 L342" " class4"line4 naml2 L253 .a href="+code=bo129a>     >        return40;>430929a>}>435429a> 4      .a href=310">431029a>>423229a4>/* Returning4-EINVA4l901.c#L34inctrl/pinctrl-coh905e174s="li4e" nam/a>.spa  class="comment">/* Returning4-EINVA4lode=NULL4local_irq_save29a>(.a hr4f="+c455aml2, unsig L346">434629a>                         unsigned4.a href="+c434629a>       /pinctrl-ci            unsign/pinctrl-ci   4290"srass="sref">gpio29a>->.a href="+code=dev" c4a347" cla4inctrl-coh901.c#L257" id4 L25745             . href="+code=bo1abref="+code=pcr" c1abre" naml2 L304">430429a>=                    .a href=/pin-trl--i   ode=retirq" class="sref">retirq29a>,4.a href="+code=port" 4al29a> =44a href="+code=readl" cla4s="sr45global GPIO s. href="+code=boown>;>430429a>=  href="+code=boTHIS    ULEl-coh901.c#L351THIS    ULE>    ass="sref">retirq29a>,4.a href="+code=port" 4alass="sr4IN_REG29a>(.a href="+cod4=offs4t" class="sref. href="+code=bo  .a href="drivers/pinct.a hr" naml2 L304">430429=  href="+code=bo/pinctrl-c  .a href="drivers/pin/pinctrl-c  .a hr>    ass="sref">retirq29a>,4.a href="+code=port" 4a">dev29a4029a>                .a 4ref="45uest IRQ for . href="+code=bofre   return40;>430429a> =  href="+code=bo/pinctrl-cfre   return40;>    ass="sref">retirq29a>,4.a href="+code=port" 4 class="s4ef">U300_PIN_BIT29a>(.a 4ref="46rt_list" clas. href="+code=bocoh901.c#L346" id2e" namlml2 L304">430429a>  =  href="+code=bo/pinctrl-ccoh901.c#L346" id2 L346" clag29a>)>writel29a>(.4 href461t_list" clas. href="+code=bof="drivers/pinctrls" namlml2 L304">430429a>  =  href="+code=bo/pinctrl-cf="drivers/pinctrl/pinctrl-coh901.cU300_PIN_BIT29a4(.a h4ef="+code=offs. href="+code=bodirec bee_sref"aml2 L329">43292irec bee_sref"="+code=offs=  href="+code=bo/pinctrl-cdirec bee_sref"aml2 L329">4329/pinctrl-cdirec bee_sref"01.clocal_irq_restore29a>4.a hr46irqs on the p. href="+code=bodirec bee_outef"aml2 L329">43292irec bee_outef"rqs on the =  href="+code=bo/pinctrl-cdirec bee_outef"aml2 L329">4329/pinctrl-cdirec bee_outef"01.coffset29a>"drivers/p L304">430429a>  =  href="+code=bo/pinctrl-cass="sref">offset29a>)>>u300_gpio_4irec246o_input29a>(struct4.a href="+code=gpio_chip" clas4="sref">g4io_chip29a> *.a href="+c4de=ch469a>{>, unsigvoi.a href="+code=co)>;>chip29a>);>431329a>        struct4.a href="+code=u300_gpio"4class="sr4f">u300_gpio29a> *.a hre4="+co46=gpio" class="sref">gpio29a> =4.a href="+code=to_u400_gpio" 4lass="sref">to_u300_gpio49a>(.46uest IRQ for GPIO %d, retrl/pinctrl-coh901.c#L290" id2 L290" class="line" naml2 L290">429029a>        .a href="+code=local_irq_save" cl4ine" naml4 L271">427129a>        .4 href474.a href="+code=gpio_chip" class="sref">gpio_chip4272" id2 4272" class="line" naml2 4272">47naml2 L253 .a href="+code=bos="line" naml2 L290">4290"sref">pcr29a>));>429229a>        .spa  class="comment">/*./spa  >val29a>,4.a href="+code=U300_PIN_REG"4ss="sref"4local_irq_save29a>(.a hr4f="+c47drivers/pinctpace and request muxing,rSet f="+ depend0_gpon , unestruct4.a href="+code=gpio_chip" class="sref">gpio_chi4/pinctrl/4inctrl-coh901.c#L274" id4 L27447ss="line" namrl-coh901.c#L323" i/pinctrl-ccoh901.c#L346" id2 L346" clag29a>)>(ml2 L321">432129a>                .a href="+code=port" class="sref"s="sref">offset29a>,>4313class="sref">gpio29a>->.a href="+code=dev" c4ef">U300_4IN_REG29a>(.a href="+cod4=offs47901.c#L326" id2 L326"pace and request muxing,rHigh now, let's    gg>;pon fall0_gpedge nex29a>enstruct4.a href="+code=gpio_chip" class="sref">gpio_chi4/ode=NULL4class="line" naml2 L276"44276247 class="line" naml2 Lf">offset29a>,4.a href="+code=pcr" class="sref">pcr29a>));>offset29a>,4.a href="+code=dor" class="sref">dor29a>));>426329a>>/*./spa  >val29a>,4.a href="+code=U300_PIN_REG"4s/o_input4SK29a> << ((.a hre4="+co47                      port for GPIO Ŷ%d from port %d\n"./spa  ,>434029a>              nex29f="+on fall0_gpedge on cod href="+code=retirq" class="sref">retirq29a>,4.a href="+code=port" 4i"sref">g4PIN_REG29a>(.a href="+co4e=off479a>{>dor29a>));>val29a>,4.a href="+code=U300_PIN_REG"4slass="sr4ctrl/pinctrl-coh901.c#L249" id47quot;could no}Lass=lass="sref">gpio29a>->.a href="+code=dev" c4e0_gpio" 4coh901.c#L281" id2 L281"4class47    return4-.a href="pace and request muxing,rLow now, let's    gg>;pon ris0_gpedge nex29a>enstruct4.a href="+code=gpio_chip" class="sref">gpio_chi4c#L282" i42 L282" class="line" nam42 L2848mber" class="sref">nuf">offset29a>,4.a href="+code=pcr" class="sref">pcr29a>));>offset29a>,4.a href="+code=dor" class="sref">dor29a>));>426129a>        else>/*./spa  >val29a>,4.a href="+code=U300_PIN_REG"4u300_gpio4direc48u300_gpio_port" class port for GPIO Ŷ%d from port %d\n"./spa  ,>434029a>              nex29f="+on ris0_gpedge on cod href="+code=retirq" class="sref">retirq29a>,4.a href="+code=port" 4ss="sref"4gpio_chip29a> *.a href="4code=48drivers/pinctrl/pinct unsigne="sref">dor29a>));>val29a>,4.a href="+code=U300_PIN_REG"4" id2 L284" class="line" naml2 L284">428429a>{>.spa  class="comment">/* Returning4-EINVA4class="sr4f">u300_gpio29a> *.a hre4="+co484" cl./a>.spa  class="comment">/* Returning4-EINVA4code=NULL4lass="sref">to_u300_gpio49a>(.48 clas/a>.spa  class="comment">/* Returning4-EINVA4c/o_input4 L287">428729a>        .4 href48     , unsig>,>chipdrivdata06" class="lineirivdatainctrl-coh901.c#L350"9a>(.a href="+cod namtrl-coh901.c#L313" id2 L31   gg>;>g48" id2 L288" class="line4 naml489a>{>ass="sref">gpio29a>->.a href="+code=dev" c448quot;could nohip" class="sref">chip29a>);>odataag29cdriv,>val29a>,4.a href="+code=U300_PIN_REG"4"0_gpio" 4local_irq_save29a>(.a hr4f="+c48href="+code=chip" class="sref">chip29a>);>435029a> eturn4.a href="+code=retirq" class="sref">retir id2 L350" class="line" nam="sref">val29a>,4.a href="+code=U300_PIN_REG"4/pinctrl/4inctrl-coh901.c#L291" id4 L29149mber" class=">,>writel29a>(.ss="line" naml2 L3eturn4.a href="+code=retirq" class="sref">retirq29a>;>(.a href="+cod nam" class="sref">retir are a>(.a href="+co are  nam="sref">val29a>,4.a href="+code=U300_PIN_REG"4//o_outpu4IN_REG29a>(.a href="+cod4=offs49naml2 L253 .a href="+code=botrl/pinctrl-coh901.c#L290" id2 L290" class="line" naml2 L290">429029a>        .a href="+code=local_irq_save" cl4a  class=4comment">         * Driv4 mode4934" id2 L334" class="line" naml2 L334">4334./a>.s4coh901.c#4294" id2 L294" class="li4e" na49ss="line" namrl-c="line" naml2 L3   gg>;>42482f="F_TRIGGER_RISIN" class="line" nf="F_TRIGGER_RISIN" namnine" nne" nd2 L334" class="line" naml2 L334">4334./a>.s4class="sr4id2 L295" class="line" n4ml2 L49901.c#L326" id2 L="line" naml2 L3   gg>;>42482f="F_TRIGGER_FALLIN" class="line" nf="F_TRIGGER_FALLIN">4313class="sref">gpio29a>->.a href="+code=dev" c4      .a 4ref="+code=oldmode" clas4="sre49 class="line" naml2 Lpace and request muxing,uct4.a href="+code=gpio_chip" class="sref">gpio_chi4PCR_PIN_M4DE_MASK" class="sref">U340_GPI49retirq29a> =4.a href="+code=irq_finddddddddd* Thee=offsblock ca> only    gg>;pon fall0_gpOR ris0_gpedges,uct4.a href="+code=gpio_chip" class="sref">gpio_chi4P"sref">g498" id2 L298" class="lin4" nam42 L298q29a> =4.a href="+code=irq_finddddddddd* pio_both. So we ne01.to toggle9a>e f="+ w>enepio9a>e pctrlt4.a href="+code=gpio_chip" class="sref">gpio_chi4Plass="sr4d2 L299" class="line" na4l2 L249">429q29a> =4.a href="+code=irq_finddddddddd* goeset29a>one , unesto t>e othio9with a special , unesass=rlt4.a href="+code=gpio_chip" class="sref">gpio_chi4P0_gpio" 42 L300">430029a>        4     49    rq29a> =4.a href="+code=irq_finddddddddd*ruct4.a href="+code=gpio_chip" class="sref">gpio_chi5_PXPCR_PI5_MODE_MASK29a> <<>5a hre50mber" class="sref">nuf">offset29a>,4Ŷ%d from port %d\n"./spa  ,>gpio_chi5_1XPCR_PI5_N_REG29a>(.a href="+cod5" nam50 L302">430229a>              340">434029a>                 gg>;pon both ris0_gpot mfall0_gpedge on cod href="+code=retirq" class="sref">retirq29a>,4.a href="+code=port" 500_GPIO_P5PCR_PIN_MODE_OUTPUT_PUSH5PULL250drivers/pinctrl/pinct unsigne="sref">dor29a>));>val29a>,4.a href="+code=U300_PIN_REG"5inctrl-co5901.c#L304" id2 L304" cl5ss="l50ss="line" naml2 L324" id2 L290" claseturn4.a href="+code=retirq" class="sref">retirtoggle_edge_               .a htoggle_edge_    /pinfdsref">pcr29a>));>03">4">offset29a>,4.a href="+code=dor" class="sref">dor29a>));>val29a>,4.a href="+code=U300_PIN_REG"5i4ctrl-co59d2 L295" class="line" n5ef="+50de=offset" class="sref">offset29a>,4)>;>dor29a>));>val29a>,4.a href="+code=U300_PIN_REG"5i5ctrl-co59ef="+code=oldmode" clas5(.a h50 class="line"}Lass=lrl-coh901.c#L323" i   gg>;>42482f="F_TRIGGER_RISIN" class="line" nf="F_TRIGGER_RISIN" namniass="sref">gpio29a>->.a href="+code=dev" c5" class="5ref">offset29a>,4.a href5"+cod50                      port for GPIO Ŷ%d from port %d\n"./spa  ,>434029a>                 gg>;pon ris0_gpedge on cod href="+code=retirq" class="sref">retirq29a>,4.a href="+code=port" 507class="5r8" id2 L298" class="lin58" id509a>{>dor29a>));>val29a>,4.a href="+code=U300_PIN_REG"5l/pinctrl5coh901.c#L310" id2 L310"5class50quot;could not locate port for GPIO s="line" naml2 L290">4290"sref">pcr29a>));>429229a>        .spa  class="comment">/*./spa  >val29a>,4.a href="+code=U300_PIN_REG"5l9pinctrl5c L300">430029a>        52 L3150    return4-.a href=" id2 L290" clas.a href="+code=pcr" class="sref">pcr29a>));>offset29a>,4.a href="+code=dor" class="sref">dor29a>));>426129a>        else>/*./spa  >val29a>,4.a href="+code=U300_PIN_REG"5" class="5ref">u300_gpio_to_irq29a5(stru51mber" class="sref">nuf">offset29a>,4eturn4.a href="+code=retirq" class="sref">retirtoggle_edge_               .a htoggle_edge_    /pinf="+co2 Lef">pcr29a>));>03">4">offset29a>,4.a href="+code=dor" class="sref">dor29a>));>val29a>,4.a href="+code=U300_PIN_REG"59a> *.a h5ef="+code=chip" class="s5ef">c51naml2 L253 .a}Lass=lrl-coh901.c#L323" i   gg>;>42482f="F_TRIGGER_FALLIN" class="line" nf="F_TRIGGER_FALLIN">4313iass="sref">gpio29a>->.a href="+code=dev" c5class="sr5f">u300_gpio29a> *.a hre5="+co51>>434029a>                 gg>;pon fall0_gpedge on cod href="+code=retirq" class="sref">retirq29a>,4.a href="+code=port" 500_gpio" 5lass="sref">to_u300_gpio59a>(.51e" naml2 L304">430429a>      ="sref">dor29a>));>val29a>,4.a href="+code=U300_PIN_REG"594ctrl-co5/pinctrl-coh901.c#L315" 5d2 L351de=offset" class="sref">offset29a>,4s="line" naml2 L290">4290"sref">pcr29a>));>429229a>        .spa  class="comment">/*./spa  >val29a>,4.a href="+code=U300_PIN_REG"595ctrl-co5 class="sref">NULL29a>;>5a hre51 class="line" naml2 L id2 L290" clas.a href="+code=pcr" class="sref">pcr29a>));>offset29a>,4.a href="+code=dor" class="sref">dor29a>));>426329a>>/*./spa  >val29a>,4.a href="+code=U300_PIN_REG"59 class="501.c#L317" id2 L317" cla5s="li51                     f="drivers/pinceturn4.a href="+code=retirq" class="sref">retirtoggle_edge_               .a htoggle_edge_    /pinf="+co2 Lef">pcr29a>));>03">4">offset29a>,4.a href="+code=dor" class="sref">dor29a>));>val29a>,4.a href="+code=U300_PIN_REG"5civers/pi531829a>        .a href="5code=51 L298">429829./a>.spa  class="comment">/* Returning4-EINVA5alse29a>;5/* Returning4-EINVA5a9pinctrl5ist_for_each29a>(.a href5"+cod51    return4-.310">431029a>>gpio29a>->.a href="5code=52mber"./a>.spa  class="comment">/* Returning4-EINVA5la> *.a h5f">p29a>, struct4.a href5"+cod5=u300_/a>.spa  class="comment">/* Returning4-EINVA5llass="sr5s="sref">portno29a>) {><5 href5"drive, unsigvoi.a href="+code=co)>chipdrivdata06" class="lineirivdatainctrl-coh901.c#L350"9a>(.a href="+cod nam329a>        struct4.a href="+code=u300_gpio"5nctrl/pin5trl-coh901.c#L324" id2 L524" c5ass="lass="sref">gpio29a>->.a href="+code=dev" c5    }>chip29a>);>odataag29cdriv,>val29a>,4.>->.a href="+code=dev" c5 5ctrl-co5pinctrl-coh901.c#L327" i52 L325" class="line"hip" class="sref">chip29a>);>435029a> eturn4.a href="+code=retirq" class="sref">retir id2 L350" class="line" nam="sref">val29a>,4.a href="+code=U300_PIN_REG"5" class="5ref">found29a>) {>writel29a>(.ss="line" naml2 L3eturn4.a href="+code=retirq" class="sref">retirq29a>;>(.a href="+cod nam" class="sref">retir are a>(.a href="+co are  nam="sref">val29a>,4.a href="+code=U300_PIN_REG"5"ivers/pi5432829a>                5a hre529a>{>429029a>        .a href="+code=local_irq_save" cl5"lse29a>;5>dev29a>,4.spa  class="s5ring"52line" naml2 Lass="sref">u3229a> .a href="+code=oldmode" class="sref">oldmode29a>;>5naml2 L330">433029a>    5     5     rmode29a>;>433129a>     5  }><53+code=u32" clnctrl/pinctrl-cŶ%d from port %d\n"./spa  ,>434029a>              enabl 9f="+for  are  href=lu on c=re href=s, ritel2 href="+code=retirq" class="sref">retirq29a>,4.a href="+code=port" 5-coh901.c5L333" id2 L333" class="l5ne" n53u300_gpio_port" classs port for GPIO &a>(.a href="+cod nam" class="sref">retir are a>(.a href="+co are  namoh901.c#L306" id2 turn4.a href="+code=retirq" class="sref">retirqass>dor29a>));>val29a>,4.a href="+code=U300_PIN_REG"5-tno" cla5vers/pinctrl/pinctrl-coh501.c#53>>dor29a>129a>        .a href="+code=val" class="sref">val29a> =4.a href="+code=readl" class="sref">readl29a>(.a href="+code=U300_PIN_REG" class="s5a  class=5comment">         * The 5ocal 539a>{>offset29a>,4s="line" naml2 L290">4290"sref">pcr29a>));>429229a>        .spa  class="comment">/*./spa  >val29a>,4.a href="+code=U300_PIN_REG"5coh901.c#5335" id2 L335" class="li5e" na53901.c#L326" i id2 L290" clas.a href="+code=pcr" class="sref">pcr29a>));>offset29a>,4.a href="+code=dor" class="sref">dor29a>));>426129a>        .spa  class="comment">/*./spa  >val29a>,4.a href="+code=U300_PIN_REG"5c5ctrl-co56" class="line" naml2 L356">4353 class="line"="sref">dor29a>129a>     >        return40;>430929a>}>.spa  class="comment">/* Returning4-EINVA5code=port5 class="sref">port29a>-&5t;.a 53 L298/a>.spa  class="comment">/* Returning4-EINVA5clse29a>;529a>(.a href="+code=gpio5 clas53-coh9, unsigvoi.a href="+code=co)>chipdrivdata06" class="lineirivdatainctrl-coh901.c#L350"9a>(.a href="+cod nam329a>        struct4.a href="+code=u300_gpio"5f">dev29a5,4.spa  class="string">&5uot;r53    rass="sref">gpio29a>->.a href="+code=dev" c5lass="sre5">port29a>->.a href="5code=5umber" class="hip" class="sref">chip29a>);>odataag29cdriv,>val29a>,4.>->.a href="+code=dev" c5lcoh901.c5">434229a>}>430229hip" class="sref">chip29a>);>435029a> eturn4.a href="+code=retirq" class="sref">retir id2 L350" class="line" nam="sref">val29a>,4.a href="+code=U300_PIN_REG"5c#L344" i52 L344" class="line" nam52 L3454>>writel29a>(.ss="line" naml2 L3eturn4.a href="+code=retirq" class="sref">retirq29a>;>(.a href="+cod nam" class="sref">retir are a>(.a href="+co are  nam="sref">val29a>,4.a href="+code=U300_PIN_REG"5c  class=5ot;supported but not ava5lable549a>{>offset29a>,4trl/pinctrl-coh901.c#L290" id2 L290" class="line" naml2 L290">429029a>        .a href="+code=local_irq_save" cl5h901.c#L355" id2 L345" class="line5 naml54de=offset" class="sref">u3229a> .a href="+code=oldmode" class="sref">oldmode29a>;>54 clas/a>.spa  class="comment">/* Returning4-EINVA5L347" cla5s="line" naml2 L347">434529a> 5              ="sref">dor29a>129a>        .a href="+code=val" class="sref">val29a> =4.a href="+code=readl" class="sref">readl29a>(.a href="+code=U300_PIN_REG" class="s5" id2 L345" class="line" naml2 L345">434549a>{>4290"sref">pcr29a>));>429229a>        .spa  class="comment">/*./spa  >val29a>,4.a href="+code=U300 class="s5"lse29a>;5f">u300_gpio29a> *.a hre5="+co54quot;could no id2 L290" clas.a href="+code=pcr" class="sref">pcr29a>));>offset29a>,4.a href="+code=dor" class="sref">dor29a>));>429229a>        .spa  class="comment">/*./spa  >val29a>,4.a href="+code=U300 class="s5"">dev29a5lass="sref">to_u300_gpio59a>(.54uest IRQ for GPIO %d, re129a>     >        return40;>430929a>}>.spa  class="comment">/* Returning4-EINVA5l-coh901.5#L351" id2 L342" " class5"line55u300_/a>.spa  class="comment">/* Returning4-EINVA5L351" cla5s="line" naml2 L351">435529a> 55drive, unsighip" class="sref">chipdrivs="sref">offset29a>drivs="sL290" id2 L290" clas/pinctrl-cdrii            unsign/pinctrl-cdrii   4290"srass="sref">gpio29a>->.a href="+code=dev" c5" class="5ine" naml2 L232">423229a5>=                    .a href=/pin-trl--drii   ode=retirq" class="sref">retirq29a>,4.a href="+code=port" 5l901.c#L35inctrl/pinctrl-coh905e175s="li55901.c#L326" i. href="+code=bodrivenabl   return40;>=  href="+code=co)>retirq29a>,4.a href="+code=port" 5lode=NULL5local_irq_save29a>(.a hr5f="+c55501.c#L326" i. href="+code=bodrivdisabl   return40;>=  href="+code=co)>retirq29a>,4.a href="+code=port" 5l347" cla5inctrl-coh901.c#L257" id5 L25755             . href="+code=boass="29ctyp   return40;>retirq29a>,4.a href="+code=port" 5l id2 L345a href="+code=readl" cla5s="sr55 L298/a>.spa  class="comment">/* Returning4-EINVA5alass="sr5IN_REG29a>(.a href="+cod5=offs5t" cla}029a>>dev29a5029a>                .a 5ref="55    rmode29a>;>U300_PIN_BIT29a>(.a 5ref="56rt_li, unsigvoi.a href="+code=co)>;>(.a href="+core  namohhip" class="sref">chipdrivdesc  return40;>        struct4.a href="+code=u300_gpio"5 -coh901.5lass="sref">writel29a>(.5 href561t_liass="sref">gpio29a>->.a href="+code=dev" c5 351" cla5s="sref">U300_PIN_BIT29a5(.a h5ef="+code=offship" class="sref">chip29a>);>og29chandl>;vdata06" class="lineirivg29chandl>;vdatactrl/pinctrl-coh901.re a>(.a href="+core  nam" naml2 L309">430929a>}>local_irq_restore29a>5.a hr56irqs on the phip" class="sref">chip29a>);>435029a> eturn4.a href="+code=retirq" class="sref">retir id2 L350" class="line" nam="sref">val29a>,4.a href="+code=U300_PIN_REG"5 901.c#L35ctrl/pinctrl-coh901.c#L255" id56901.c#L326" i>,>/*./cod class naml2 L350">435029a> eturn4.a href="+code=retirq" class="sref">retirq29a>;>e rightphipidestruct4.a href="+code=gpio_chip" class="sref">gpio_chi5 ode=NULL52 L267" class="line" nam52 L2656501.c#L326" iass="sref">u3229a> .a href="+s="line" naml2 L290">429029a>        .a href="+code=local_irq_save" cl5u300_gpio_5irec256o_input29a>(struct4.a href="+code=gpio_chip" clas5="sref">g5io_chip29a> *.a href="+c5de=ch569a>{>retirdrivdata06" class="lineirivdatainct. href="+code=bos="sref">offset29a>,>retirdrivack06" class="lineirivackctrl/ml2 L321">432129a>  9esc  return40;>retirdrivdata06" class="lineirivdatainct" naml2 L309">430929a>}>u300_gpio29a> *.a hre5="+co56quot;could no ace and request muxing,rRead evmux registerstruct4.a href="+code=gpio_chip" class="sref">gpio_chi5 ">dev29a5lass="sref">to_u300_gpio59a>(.56uest IRQ for GPIO %d, res="line" naml2 L290">4290"sref">pcr29a>));>429229a>        .spa cod class="comment">/*./cod class namref="drivers/pincie340" class="linei naml2 s="sref">val29a>,4.a href="+code=U300 class="s5ine" naml5 L271">427129a>        .5 href570uot;could no ace and request muxing,rMask relevaux bitsstruct4.a href="+code=gpio_chip" class="sref">gpio_chi5272" id2 5272" class="line" naml2 5272">57naml2 L253 .a href="+code=bos="line" naml2 L290">4290"="+co2 0xFFU;"pace and request muxing,r8 bitsspersc=re truct4.a href="+code=gpio_chip" class="sref">gpio_chi52351" cla5local_irq_save29a>(.a hr5f="+c57drivers/pinctpace and request muxing,rACK9f="+(clear evmux) truct4.a href="+code=gpio_chip" class="sref">gpio_chi52 class="5inctrl-coh901.c#L274" id5 L274579a>{>offset29a>,4.a href="+code=pcr" class="sref">pcr29a>));>430529a>        }>/*./cod class namref="drivers/pincie340" class="linei naml2 s="sref">val29a>,4.a href="+code=U300 class="s5i901.c#L35IN_REG29a>(.a href="+cod5=offs57" nam/a>.spa  class="comment">/* Returning4-EINVA5/ode=NULL5class="line" naml2 L276"54276257 class="line"pace and request muxing,rCall9f="+handl>; truct4.a href="+code=gpio_chip" class="sref">gpio_chi52/o_input5SK29a> << ((.a hre5="+co57             rl-coh901.c#L323" is="line" naml2 L290">4290"!2 03iass="sref">gpio29a>->.a href="+code=dev" c5i"sref">g5PIN_REG29a>(.a href="+co5e=off579a>{>/*./iri class429029a>        .a href="+code=local_irq_save" cl5slass="sr5ctrl/pinctrl-coh901.c#L259" id57-coh9/a>.spa  class="comment">/* Returning4-EINVA5e0_gpio" 5coh901.c#L281" id2 L281"5class57    return4-.a href="pinctrl-coh901.cor_each="29cbit9" id2 L309" claor_each="29cbitctrl/pinctrl-coh901.re  class="comment">/*./iri class4290, ml2 L321">432129a>  href="drivers/pinctrl/pinctrl-coh901.c#L305" id30329aINS_PER_PORet29a>,4.a href="+cod30329aINS_PER_POReaml2 iass="sref">gpio29a>->.a href="+code=dev" c5c#L282" i52 L282" class="line" nam52 L2858mber" class="sref">nu#L326" i>,>offset29a>cods="stirqoffset" class="sref">ofind_mapp   .6" class="lineirivfind_mapp   30529a>        }>retirdomain06" class="linedomain namref="drivers/pincie  class="comment">/*./iri class4290s="sref">val29a>,4.a href="+code=U300 class="s5u300_gpio5direc58u300_gpio_port" class#L326" i>,>writel29a>(.ssa href="driverscod class="comment">/*./cod class naml+s port for GPIO iri class="comment">/*./iri class429029a>        .a href="+code=local_irq_save" cl5ss="sref"5gpio_chip29a> *.a href="5code=5834" id2 L334" class="line" naml2 L334">4334./a>.s5" id2 L285" class="line" naml2 L285">42858e" naml2 L304">430429a>      ="sref">dor29a>Ŷ%d from port %d\n"./spa  ,>434029a>              =offsf="+href=" on cod href="+code=retirq" class="sref">retirq29a>,4.a href="+code=port" 5class="sr5f">u300_gpio29a> *.a hre5="+co58de=offset" class="sre">430429a>      ="sref">dor29a>cods="sref">offset29a>cods="stirqtr="sref">dor29a>));>val29a>,4.a href="+code=U300_PIN_REG"5code=NULL5lass="sref">to_u300_gpio59a>(.58 class="line" naml2 La>      ="sref">dor29a>genericchandl>s="sref">offset29a>genericchandl>s="s30529a>        }>offset29a>cods="stirqn="sref">val29a>,4.a href="+code=U300_PIN_REG"5c/o_input5 L287">428729a>        .5 href58                     a>      =ace and request muxing,uct4.a href="+code=gpio_chip" class="sref">gpio_chi5c"sref">g58" id2 L288" class="line5 naml58 L298q29a> =4.a href="+code=irq_finddddddddddddddddd* T  gg>;0_gpf="+on both ris0_gpot mfall0_gpedgeuct4.a href="+code=gpio_chip" class="sref">gpio_chi5class="sr5289" class="line" naml2 5289">58">429q29a> =4.a href="+code=irq_finddddddddddddddddd* ne01s mockeryuct4.a href="+code=gpio_chip" class="sref">gpio_chi5c0_gpio" 5local_irq_save29a>(.a hr5f="+c58    rq29a> =4.a href="+code=irq_finddddddddddddddddd*ruct4.a href="+code=gpio_chip" class="sref">gpio_chi5/pinctrl/5inctrl-coh901.c#L291" id5 L29159mber" class="sref">nu#L326" i>l-coh901.c#L323" ieturn4.a href="+code=retirq" class="sref">retirtoggle_edge_               .a htoggle_edge_    /pinf="+coe=offset" class="sref">offset29a>,4.a href="+code=dor" class="sref">dor29a>));>(.a href="+cod5=offs59u300_gpio_port" class#L326" ia>      =ss="sref">chip29a>)toggle_   gg>;>dor29a>));>val29a>,4.a href="+code=U300_PIN_REG"5a  class=5comment">         * Driv5 mode59>>/* Returning4-EINVA5coh901.c#5294" id2 L294" class="li5e" na599a>{>.spa  class="comment">/* Returning4-EINVA5class="sr5id2 L295" class="line" n5ml2 L59" nam/a>.spa  class="comment">/* Returning4-EINVA5      .a 5ref="+code=oldmode" clas5="sre59 class="line"="sref">dor29a>9esc  return40;>retirdrivdata06" class="lineirivdatainct. href="+code=bos="sref">offset29a>,>retirdrivunmask06" class="lineirivunmaskctrl/ml2 L321">432129a>  9esc  return40;>retirdrivdata06" class="lineirivdatainct" naml2 L309">430929a>}>U350_GPI59     ./a>.spa  class="comment">/* Returning4-EINVA5P"sref">g598" id2 L298" class="lin5" nam59 L298/a>.spa  class="comment">/* Returning4-EINVA5Plass="sr5d2 L299" class="line" na5l2 L259-coh9, unsigvoi.a href="+code=co__init9" id2 L309" cl__initL290" id2 L290" clas/pinctrl-cdnit_pin06" class="line/pinctrl-cdnit_pinctrl/hip" class="sref">chip29a>);>retirq29a>,4.a href="+code=port" 5P0_gpio" 52 L300">430029a>        5     59    return4-.a href="lass="sref">nu#L326" i>,>writel29a>(lass="sref">retirq29a>,4.a href="+code=port" 6_PXPCR_PI6_MODE_MASK29a> <<>6a hre60mber" class="sref">nuuuuuuuuuuuuuuuuuuuuuuuconstship" class="sref">chip29a>);>offset29a>,onfinct329a>        struct4.a href="+code=u300_gpio"6_1XPCR_PI6_N_REG29a>(.a href="+cod6" nam601t_liass="sref">gpio29a>->.a href="+code=dev" c600_GPIO_P6PCR_PIN_MODE_OUTPUT_PUSH6PULL260drivers/pinctpace and request muxing,rSet f="+: sref" or outef"d*ruct4.a href="+code=gpio_chip" class="sref">gpio_chi6inctrl-co6901.c#L304" id2 L304" cl6ss="l60ss="line" namrl-coh901.c#L323" iconfref">offset29a>,onfinct" class="sref">retiroutef"aml2 L329">4329outef"01.c iass="sref">gpio29a>->.a href="+code=dev" c6i4ctrl-co69d2 L295" class="line" n6ef="+60de=offset" class="sref">offset29a>,4)>4329/pinctrl-cdirec bee_outef"01.c(ml2 L321">432129a>                .a href="+code=port" class="sref"s="sref">offset29a>,>431fdc#L313" id2 L31confref">offset29a>,onfinct" class="sref">retirouthref="drivers/pincouthreinct" naml2 L309">430929a>}>.spa  class="comment">/* Returning4-EINVA6" class="6ref">offset29a>,4.a href6"+cod60                      ace and request muxing,rDeac bvunesbias f="+ for outef"d*ruct4.a href="+code=gpio_chip" class="sref">gpio_chi6i7class="6r8" id2 L298" class="lin68" id609a>{>chip29a>);>432129a>                .a href="+code=port" class="sref"s="sref">offset29a>,>431fhref="+code=gpio_chip" class="sref">gpio_chi6i8class="6r2 L299" class="line" na6class60quot;could not locateeeeeeeeeeeeeeeeeeeeeec#L313" id2 L31e=doCONFIGor"AS_HIGH_IMPEDANCEss="line" naml2e=doCONFIGor"AS_HIGH_IMPEDANCEinct" naml2 L309">430929a>}>430029a>        62 L3160    rmode29a>;>u300_gpio_to_irq29a6(stru61mber" class="sref">nuface and request muxing,rSet gpio_chi69a> *.a h6ef="+code=chip" class="s6ef">c61u300_gpio_port" classass="sref">chip29a>);>432129a>                .a href="+code=port" class="sref"s="sref">offset29a>,>431fhref="+code=gpio_chip" class="sref">gpio_chi690_GPIO_P6f">u300_gpio29a> *.a hre6="+co61>>430929a>}>to_u300_gpio69a>(.61e" nanaml2 L309">430929a>}>offset29a>,4Ŷ%d from port %d\n"./spa  ,>434029a>              el2 up cod href=" as outef", hreu+: href="+code=retirq" class="sref">retirq29a>,4.a href="+code=port" 695ctrl-co6 class="sref">NULL29a>;>6a hre61 class="line" naml2 Lass="sref">offset29a>,43" class="line" naml2 L313">431fdc#L313" id2 L31confref">offset29a>,onfinct" class="sref">retirouthref="drivers/pincouthreinct" naml2 L309">430929a>}>gpio29a>->.a href="+code=dev" c6civers/pi631829a>        .a href="6code=619a>{>chip29a>);>4329/pinctrl-cdirec bee_sref"01.c(ml2 L321">432129a>                .a href="+code=port" class="sref"s="sref">offset29a>,>431" naml2 L309">430929a>}>/* Returning4-EINVA6a9pinctrl6ist_for_each29a>(.a href6"+cod61    return4-.a href="pace and request muxing,rAlways el2 outef"dlow+on sref" * Rsstruct4.a href="+code=gpio_chip" class="sref">gpio_chi6lass="sre6">gpio29a>->.a href="6code=62mber" class="sref">nuf">offset29a>,4/pinctrl-cf="drivers/pinctrl/pinctrl-cf="01.c(ml2 L321">432129a>                .a href="+code=port" class="sref"s="sref">offset29a>,>431f 0" naml2 L309">430929a>}>p29a>, struct4.a href6"+cod6=u300_/a>.spa  class="comment">/* Returning4-EINVA6llass="sr6s="sref">portno29a>) {><6 href62>>gpio_chi6l0_gpio" 6trl-coh901.c#L324" id2 L624" c62ss="line" naml2 L324" id2 L290" clas29a>);>432129a>                .a href="+code=port" class="sref"s="sref">offset29a>,>431fdc#L313" id2 L31confref">offset29a>,onfinct" class="sref">retirbias_               .a hbias_    >431" naml2 L309">430929a>}>.spa  class="comment">/* Returning4-EINVA6 5ctrl-co6pinctrl-coh901.c#L327" i62 L3262 class="line" naml2 Lf">offset29a>,4Ŷ%d from port %d\n"./spa  ,>434029a>              el2 up cod href=" as sref", bias: href=04x+code=retirq" class="sref">retirq29a>,4.a href="+code=port" 6" class="6ref">found29a>) {>431fdc#L313" id2 L31confref">offset29a>,onfinct" class="sref">retirbias_               .a hbias_    >431" naml2 L309">430929a>}>429829./a>.spa  class="comment">/* Returning4-EINVA6"lse29a>;6>dev29a>,4.spa  class="s6ring"62line"./a>.spa  class="comment">/* Returning4-EINVA6"9pinctrl6naml2 L330">433029a>    6     6     rmode29a>;>433129a>     6  }><63rt_li, unsigvoi.a href="+code=co__init9" id2 L309" cl__initL290" id2 L290" clas/pinctrl-cdnit_/pinct5272" class=="line/pinctrl-cdnit_/pinct527ctrl/hip" class="sref">chip29a>);>        struct4.a href="+code=u300_gpio"6-coh901.c6L333" id2 L333" class="l6ne" n631t_liass="sref">gpio29a>->.a href="+code=dev" c6-tno" cla6vers/pinctrl/pinctrl-coh601.c#63>>         * The 6ocal 63e" nanaml2 L309">430929a>}>gpio_chi6c5ctrl-co66" class="line" naml2 L366">4363 class="line"for /pinctrl-coh901.r06" class="linei>431 = 0oe=offset" class=r06" class="linei>431 l" cl=offset" class="sref30329NUM_POReSt29a>,4.a href="+cod30329NUM_POReS42902e=offset" class=r06" class="linei>431++ iass="sref">gpio29a>->.a href="+code=dev" c6c class="6ref="+code=retirq" class6"sref63                     for /pinctrl-coh901.j06" class="linej4290 = 0oe=offset" class=j06" class="linej4290 l" cl8oe=offset" class=j06" class="linej4290++ iass="sref">gpio29a>->.a href="+code=dev" c6civers/pi6 class="sref">port29a>-&6t;.a 639a>{>chip29a>);>offset29a>,onfinct29a>        .a href="+code=local_irq_save" cl6alse29a>;629a>(.a href="+code=gpio6 clas63quot;could not locateeeeeeeee>,>writel29a>(.ss="line" naml2 L3r06" class="linei>431*8) +s port for GPIO j06" class="linej429029a>        .a href="+code=local_irq_save" cl6a9pinctrl6,4.spa  class="string">&6uot;r63    rmode29a>;>port29a>->.a href="6code=64mber" class="sref">nuuuuuuuuu-coh901.c#L350"confref">offset29a>,onfinct.ssml2 L321">432129a>  bs335ctrl-cconfig           .a hbs335ctrl-cconfiginct["line" naml2 L3r06" class="linei>431]["line" naml2 L3j06" class="linej4290]29a>        .a href="+code=local_irq_save" cl6lcoh901.c6">434229a>}>431fdc#L313" id2 L31confref">offset29a>,onfinct" naml2 L309">430929a>}>>/* Returning4-EINVA6c  class=6ot;supported but not ava6lable649a>{>.spa  class="comment">/* Returning4-EINVA6h901.c#L365" id2 L345" class="line6 naml64de=of./a>.spa  class="comment">/* Returning4-EINVA6h5ctrl-co6ref="+code=chip" class="6ref">64 clas/a>.spa  class="comment">/* Returning4-EINVA6L347" cla6s="line" naml2 L347">434629a> 6      , unsig"line" naml2 L3rnml2 L3" class="lineinml2 a>{>chip29a>);>        struct4.a href="+code=u300_gpio"6" id2 L346" class="line" naml2 L346">434649a>{>ass="sref">gpio29a>->.a href="+code=dev" c6"lse29a>;6f">u300_gpio29a> *.a hre6="+co64quot;could nohip" class="sref">chip29a>);>430929a>}>to_u300_gpio69a>(.64uest IRQ for hip" class="sref">chiplist_hea&a>(.a href="+colist_hea&inctrl-coh901.c#L350"en4.a href="+code>431fdl-coh901.c#L350"n06" class="linentirq naml2 L309">430929a>}>430929a>}>432129a>  ref="drivers/pinctrl/pinctrl-coh901.c#L340" id2e=re_listn4.a href="+code=re_list nam3iass="sref">gpio29a>->.a href="+code=dev" c6L351" cla6s="line" naml2 L351">435629a> 65>>chip29a>);>431" naml2 L309">430929a>}>423229a6>432129a>  eturn4.a href="+code=retirq" class="sref">retirq              .a hn   >431" naml2 L309">430929a>}>retirdomain06" class="linedomain nam329a>        struct4.a href="+code=u300_gpio"6lode=NULL6local_irq_save29a>(.a hr6f="+c65 class="line" naml2 Lass="sref">offset29a>,4irivdomain_remo .a href="+code=virivdomain_remo .ctrl/-coh901.c#L350"eturn4.a href="+code=retirq" class="sref">retirdomain06" class="linedomain nam3 naml2 L309">430929a>}>430929a>}>429829./a>.spa  class="comment">/* Returning4-EINVA6alass="sr6IN_REG29a>(.a href="+cod6=offs65line"./a>.spa  class="comment">/* Returning4-EINVA6a">dev29a6029a>                .a 6ref="65    rmode29a>;>U300_PIN_BIT29a>(.a 6ref="66rt_li=ace and request muxing,uct4.a href="+code=gpio_chip" class="sref">gpio_chi6 -coh901.6lass="sref">writel29a>(.6 href661t_liq29a> =4.a href="+code=* Here we map a =offsin t>e href= trl-cchip cod 29acesto a cod in nt4.a href="+code=gpio_chip" class="sref">gpio_chi6 351" cla6s="sref">U300_PIN_BIT29a6(.a h6ef="+cq29a> =4.a href="+code=* t>e href= ss="sre cod 29ace. T>e cod ,ontroll>; used is nt4.a href="+code=gpio_chip" class="sref">gpio_chi6  class="6f">local_irq_restore29a>6.a hr66irqs q29a> =4.a href="+code=* ss="sref29a>. nt4.a href="+code=gpio_chip" class="sref">gpio_chi6 901.c#L36ctrl/pinctrl-coh901.c#L265" id66901.cq29a> =4.a href="+code=*ruct4.a href="+code=gpio_chip" class="sref">gpio_chi6 ode=NULL62 L267" class="line" nam62 L2666501.chip" class="sref">chip">gpio_pinpai;>gpio_pinpai;L298"ass="sref">gpio29a>->.a href="+code=dev" c6u300_gpio_6irec266             ass="sref>,>writel29a>( naml2 L309">430929a>}>g6io_chip29a> *.a href="+c6de=ch669a>{>,>430929a>}>u300_gpio29a> *.a hre6="+co66" cla}029a>>dev29a6lass="sref">to_u300_gpio69a>(.66    rmode29a>;>427129a>        .6 href670uot;#def9a>writel29a>(.ssa href="driversa06" class="lineainctfd. href="+code=boref_base06" class="lineref_base9a>(.ssa href="driversb           .a hb nam9./a>.spa  class="comment">/* Returning4-EINVA6272" id2 6272" class="line" naml2 6272">67u300_/a>.spa  class="comment">/* Returning4-EINVA62351" cla6local_irq_save29a>(.a hr6f="+c67drive, unsighip" class="sref">chip">gpio_pinpai;>gpio_pinpai;L298"ass="sref">chip">gpio_pintabl   return40;>gpio_pintabl inct[]"srass="sref">gpio29a>->.a href="+code=dev" c62 class="6inctrl-coh901.c#L274" id6 L274679a>{>offset29a>,4COHpio_PINRANGEss="line" naml2COHpio_PINRANGEctrl/10, 426)lass="sref">retirq29a>,4.a href="+code=port" 6i901.c#L36IN_REG29a>(.a href="+cod6=offs67901.c#L326" i id2 L290" clasCOHpio_PINRANGEss="line" naml2COHpio_PINRANGEctrl/11, 180)lass="sref">retirq29a>,4.a href="+code=port" 6iode=NULL6class="line" naml2 L276"64276267 class="line"pid2 L290" clasCOHpio_PINRANGEss="line" naml2COHpio_PINRANGEctrl/12, 165),o ace and request muxing,rMS/MMC caref>,ser bee=*ruct4.a href="+code=gpio_chip" class="sref">gpio_chi62/o_input6SK29a> << ((.a hre6="+co67             ="sref">dor29a>COHpio_PINRANGEss="line" naml2COHpio_PINRANGEctrl/13, 179)lass="sref">retirq29a>,4.a href="+code=port" 6i"sref">g6PIN_REG29a>(.a href="+co6e=off679a>{>retirq29a>,4.a href="+code=port" 6ilass="sr6ctrl/pinctrl-coh901.c#L269" id67quot;could no id2 L290" clasCOHpio_PINRANGEss="line" naml2COHpio_PINRANGEctrl/16, 194)lass="sref">retirq29a>,4.a href="+code=port" 6i">dev29a6coh901.c#L281" id2 L281"6class67uest IRQ for GPIO %d, reCOHpio_PINRANGEss="line" naml2COHpio_PINRANGEctrl/17, 193)lass="sref">retirq29a>,4.a href="+code=port" 6c#L282" i62 L282" class="line" nam62 L2868+code=u32" clnctrl/pinctrl-cCOHpio_PINRANGEss="line" naml2COHpio_PINRANGEctrl/18, 192)lass="sref">retirq29a>,4.a href="+code=port" 6c72" id2 6" class="sref">u300_gpio6direc68naml2 L253 .a href="+code=boCOHpio_PINRANGEss="line" naml2COHpio_PINRANGEctrl/19, 191)lass="sref">retirq29a>,4.a href="+code=port" 6c351" cla6gpio_chip29a> *.a href="6code=68>>dor29a>COHpio_PINRANGEss="line" naml2COHpio_PINRANGEctrl/20, 186)lass="sref">retirq29a>,4.a href="+code=port" 6" id2 L286" class="line" naml2 L286">428689a>{>offset29a>,4COHpio_PINRANGEss="line" naml2COHpio_PINRANGEctrl/21, 185)lass="sref">retirq29a>,4.a href="+code=port" 6"901.c#L36f">u300_gpio29a> *.a hre6="+co68901.c#L326" i id2 L290" clasCOHpio_PINRANGEss="line" naml2COHpio_PINRANGEctrl/22, 184)lass="sref">retirq29a>,4.a href="+code=port" 6code=NULL6lass="sref">to_u300_gpio69a>(.68 class="line"pid2 L290" clasCOHpio_PINRANGEss="line" naml2COHpio_PINRANGEctrl/23, 183)lass="sref">retirq29a>,4.a href="+code=port" 6c/o_input6 L287">428729a>        .6 href68             ="sref">dor29a>COHpio_PINRANGEss="line" naml2COHpio_PINRANGEctrl/24, 182)lass="sref">retirq29a>,4.a href="+code=port" 6c"sref">g68" id2 L288" class="line6 naml689a>{>retirq29a>,4.a href="+code=port" 6class="sr6289" class="line" naml2 6289">68" cla}029a>>(.a hr6f="+c68    rmode29a>;>,>chipplatform_device06" class="linerlatform_deviceinctrl-coh901.c#L350"e L340" class="linep" naml2329a>        struct4.a href="+code=u300_gpio"6//o_outpu6IN_REG29a>(.a href="+cod6=offs691t_liass="sref">gpio29a>->.a href="+code=dev" c6a  class=6comment">         * Driv6 mode69f="+code=offship" class="sref">chip29a>);>>chipresource06" class="lineresourceinctrl-coh901.c#L350"memres06" class="linememres nam029a>>,>(.ss0029a>>,>U360_GPI69             ="sref">dor29a>trl/pinctrl-coh901.c#L290" id2 L290" class="line" naml2 L290">429029a>        .a href="+code=local_irq_save" cl6P"sref">g698" id2 L298" class="lin6" nam699a>{>,>430029a>        6     69    rmode29a>;>435029a> " nm_kzalloc  return40;>432129a>  e L340" class="linep" naml2l-coh901.c#L340" id2 L340" class="line" naml2 Lsizeof/hip" class="sref">chip29a>);>430929a>}>l-coh901.c#L323" i id2 L350" class="line" naml22 L350">435029a> NULLss="line" naml2NULLinct"naml2 L309">430929a>}>         * Driv7PULL270>>435029a> ENOMEMss="line" naml2ENOMEM>43129a>        .a href="+code=local_irq_save" cl7inctrl-co7901.c#L304" id2 L304" cl7ss="l70e" nanaml2 L309">430929a>}>offset29a>,>        .a href="+code=local_irq_save" cl7i5ctrl-co79ef="+code=oldmode" clas7(.a h70 class="line"pid2 L290" clas              .a href="+code=port" class="sref"s="sref">offset29a>,>435029a> "sref30329NUM_POReSt29a>,4.a href="+cod30329NUM_POReS4290 *trl-coh901.c#L305" id30329aINS_PER_PORet29a>,4.a href="+cod30329aINS_PER_POReaml229a>        .a href="+code=local_irq_save" cl7i6ctrl-co79E_MASK" class="sref">U37"+cod70             ="sref">dor29a>              .a href="+code=port" class="sref"s="sref">offset29a>,>432129a>  e L340" class="linep" naml2l-coh901.c#L340" id2 L340" class="line" naml229a>        .a href="+code=local_irq_save" cl7i7ctrl-co798" id2 L298" class="lin78" id709a>{>offset29a>,>432129a>  e L340" class="linep" naml2l-coh901.c#L340" id2 L340" class="line" naml229a>        .a href="+code=local_irq_save" cl7i9class="7r L300">430029a>        72 L3170    rmode29a>;>u300_gpio_to_irq29a7(stru71+code=u32" clnctrl/pinctrl-cmemres06" class="linememres nam.ssa href="driversclatform_g29cresource06" class="lineclatform_g29cresourcectrl/-coh901.c#L350"e L340" class="linep" naml2ctrl-coh901.c#L26IORESOURCE_MEMss="line" naml2IORESOURCE_MEMaml2ct0" naml2 L309">430929a>}>c71naml2 L253 .a href="+code=boref="drivers/pinctrl/pinctrl-coh901.c#L340" id2base06" class="linebase9a>(.ssL350">435029a> " nm_ioremapcresource06" class="line" nm_ioremapcresource01.c(ml2 L321">432129a>  e L340" class="linep" naml2l-coh901.c#L340" id2 L340" class="line" naml2 Lnctrl/pinctrl-cmemres06" class="linememres nam" naml2 L309">430929a>}>u300_gpio29a> *.a hre7="+co71>>to_u300_gpio79a>(.71ss="line" naml2 L324"return 901.c#L340" id2PTR_ERRss="line" naml2PTR_ERRctrl/-coh901.c#L350"ref="drivers/pinctrl/pinctrl-coh901.c#L340" id2base06" class="linebase9a>(n naml2 L309">430929a>}>.spa  class="comment">/* Returning4-EINVA795ctrl-co7 class="sref">NULL29a>;>7a hre71 class="line"pid2 L290" clas              .a href="+code=port" class="sref"slk06" class="lineslk9a>(.ssL350">435029a> " nm_slk_g2906" class="line" nm_slk_g29ctrl/-coh901.c#L350"ref="drivers/pinctrl/pinctrl-coh901.c#L340" id2 L340" class="line" naml2 Lnctrl/pinctrl-cNULLss="line" naml2NULLinct" naml2 L309">430929a>}>gpio29a>->.a href="+code=dev" c7civers/pi731829a>        .a href="7code=719a>{>chiper;>430929a>}>434029a>              could notrg29 =offsclock+code=retirq" c) naml2 L309">430929a>}>(.a href7"+cod71    return4-.a href="return 901.c#L340" id2er;>430929a>}>gpio29a>->.a href="7code=72mber" class="./a>.spa  class="comment">/* Returning4-EINVA7la> *.a h7f">p29a>, struct4.a href7"+cod7=u300_/a>.spa  class="comment">/* Returning4-EINVA7llass="sr7s="sref">portno29a>) {><7 href72>>dor29a>er;>430929a>}>gpio29a>->.a href="+code=dev" c7    }>offset29a>,4%er;>434029a>              could notrenabl  =offsclock+code=retirq" c) naml2 L309">430929a>}>430929a>}>found29a>) {>/* Returning4-EINVA7livers/pi7432829a>                7a hre72 L298/a>.spa  class="comment">/* Returning4-EINVA7"lse29a>;7>dev29a>,4.spa  class="s7ring"72quot;could no id2 L290" clas L3_inf="drivers/pinctr L3_inf=ctrl/-coh901.c#L350"ref="drivers/pinctrl/pinctrl-coh901.c#L340" id2 L340" class="line" naml2 /a>.spa  class="comment">/* Returning4-EINVA7"9class="7naml2 L330">433029a>    7     72    return4-.a href="ln40">434029a>              initializ0_gp=offsControll>; COH 4-E>57n/3+code=retirq" c) naml2 L309">430929a>}>433129a>     7  }><73+code=u32" clnctrl/pinctrl-c id2 L350" class="line" naml-coh901.c#L340" id2                 .a h       naml2 L350">435029a> "sref30329PORe_STRIDEss="line" naml2"sref30329PORe_STRIDE9a>( naml2 L309">430929a>}>435029a> "sref30329PXPCRss="line" naml2"sref30329PXPCR9a>( naml2 L309">430929a>}>>dor29a>ref="drivers/pinctrl/pinctrl-coh901.c#L340" id2 o;>435029a> "sref30329PXPDORss="line" naml2"sref30329PXPDOR9a>( naml2 L309">430929a>}>         * The 7ocal 739a>{>offset29a>,4ref="drivers/pinctrl/pinctrl-coh901.c#L340" id2 i;>435029a> "sref30329PXPDIRss="line" naml2"sref30329PXPDIR9a>( naml2 L309">430929a>}>;>435029a> "sref30329PXPERss="line" naml2"sref30329PXPER9a>( naml2 L309">430929a>}>4373 class="line"pid2 L290" clas              .a href="+code=port" class="sref"ic;>435029a> "sref30329PXICRss="line" naml2"sref30329PXICR9a>( naml2 L309">430929a>}>dor29a>              .a href="+code=port" class="sref"ien06" class="lineien naml2 L350">435029a> "sref30329PXIENss="line" naml2"sref30329PXIEN9a>( naml2 L309">430929a>}>port29a>-&7t;.a 739a>{>435029a> "sref30329PXIEVss="line" naml2"sref30329PXIEV9a>( naml2 L309">430929a>}>435029a> "sref30329PXIFRss="line" naml2"sref30329PXIFR9a>( naml2 L309">430929a>}>&7uot;r73    rmode29a>;>port29a>->.a href="7code=74+code=u32" clnctrl/pinctrl-cs="line" naml2 L290">4290.ssL350">435029a> read"line" naml2 L29read"ctrl/-coh901.c#L350"ref="drivers/pinctrl/pinctrl-coh901.c#L340" id2base06" class="linebase9a>( +s port for GPIO "sref30329CRss="line" naml2"sref30329CR9a>() naml2 L309">430929a>}>434229a>}>434029a>              COHpio57n/3 block 3092ion: href=", ode=retirq" c \naml2 L309">430929a>}>>434029a>              numb>; of cores: href=d totall0_gphref=d refs+code=retirq" class="sref">retirq29a>,4.a href="+code=port" 7c  class=7ot;supported but not ava7lable74e" naml2 L304">430429a(/-coh901.c#L350"s="line" naml2 L290">4290.="+coe0x000001FC) -coh-coh 2)lass="sref">retirq29a>,4.a href="+code=port" 7h901.c#L375" id2 L345" class="line7 naml74de=offset" class="sre"(/-coh901.c#L350"s="line" naml2 L290">4290.="+coe0x0000FE00) -coh-coh 9)lass="sref">retirq29a>,4.a href="+code=port" 7h5ctrl-co7ref="+code=chip" class="7ref">74 class="line" naml2 La(/-coh901.c#L350"s="line" naml2 L290">4290.="+coe0x0000FE00) -coh-coh 9) * 8) naml2 L309">430929a>}>434729a> 74             ="sref">dor29a>wass="line" naml2 L29wass="ctrl/-coh901.c#L350""sref30329CR_BLOCK_CLKRQ_ENABLEss="line" naml2"sref30329CR_BLOCK_CLKRQ_ENABLEaml2 /a>.spa  class="comment">/* Returning4-EINVA7" id2 L347" class="line" naml2 L347">434749a>{>() naml2 L309">430929a>}>u300_gpio29a> *.a hre7="+co74quot;could no id2 L290" clas/pinctrl-cdnit_/pinct5272" class=="line/pinctrl-cdnit_/pinct527ctrl/-coh901.c#L350"ref="drivers/pinctrl/pinctr) naml2 L309">430929a>}>to_u300_gpio79a>(.74    rmode29a>;>gpio_chi7acoh901.c7#L351" id2 L342" " class7"line75naml2 L253 .a href="+code=boINIT_LIST_HEADss="line" naml2INIT_LIST_HEAD01.c(ml2 L321">432129a>  ref="drivers/pinctrl/pinctrl-coh901.c#L340" id2e=re_listn4.a href="+code=re_list nam3 naml2 L309">430929a>}>435729a> 75>>gpio29a>->.a href="+code=dev" c7" class="7ine" naml2 L232">423229a7>chip29a>);>gpio29a>->.a href="+code=dev" c7"901.c#L37inctrl/pinctrl-coh905e177s="li75de=offset" class="sre L253 .a href="+code=bokmalloc  return40;>chip29a>);>430929a>}>.spa  class="comment">/* Returning4-EINVA7"347" cla7inctrl-coh901.c#L257" id7 L25775                     rl-c!-coh901.c#L350"eturn4.a href="+code=retirq iass="sref">gpio29a>->.a href="+code=dev" c7" id2 L347a href="+code=readl" cla7s="sr759a>{>offset29a>,4%er;>434029a>              of" of memory+code=retirq" c) naml2 L309">430929a>}>(.a href="+cod7=offs75quot;could not locateeeeeeeee="sref">dor29a>er;>435029a> ENOMEMss="line" naml2ENOMEM>43129a>        .a href="+code=local_irq_save" cl7a">dev29a7029a>                .a 7ref="75    return4-.a href="llllllllgotoe="sref">dor29a>er;_na_eturn4.a href="+coder;_na_etur>43129a>        .a href="+code=local_irq_save" cl7 class="s7ef">U300_PIN_BIT29a>(.a 7ref="76mber" class="sref">nu./a>.spa  class="comment">/* Returning4-EINVA7 -coh901.7lass="sref">writel29a>(.7 href76u300_/a>.spa  class="comment">/* Returning4-EINVA7 351" cla7s="sref">U300_PIN_BIT29a7(.a h76>>offset29a>snp   tfctrl/-coh901.c#L350"eturn4.a href="+code=retirq" class="sref">retirqBITn4.a href="+codqBITaml2 L8 Ln40">434029a>              l/pihref=dode=retirq" cle=offset" class=rortn2 L350" class="lrortn2 nam) naml2 L309">430929a>}>local_irq_restore29a>7.a hr76ss="line" naml2 L324" id2 L290" claseturn4.a href="+code=retirq" class="sref">retirqumb>;n4.a href="+codqumb>;4290.ssL350">435029a> rortn2 L350" class="lrortn2 nam029a>>offset29a>,4eturn4.a href="+code=retirq" class="sref">retir id2 L350" class="line" naml2 L350">435029a>  id2 L350" class="line" nam029a>>.spa  class="comment">/* Returning4-EINVA7u300_gpio_7irec276                     f="drivers/pinceturn4.a href="+code=retirq" class="sref">retirirq>435029a> rlatform_g29cirq>430929a>}>.spa  class="comment">/* Returning4-EINVA7=lass="sr7f">u300_gpio29a> *.a hre7="+co76quot;could not locate901.c#L340" id2 L3_4%d from port %d\n"./spa  ,>434029a>              register IRQ href=d for rort href=s+code=retirq" cl f="drivers/pinceturn4.a href="+code=retirq" class="sref">retirirq>/* Returning4-EINVA7 ">dev29a7lass="sref">to_u300_gpio79a>(.76    return4-.a href="llllllll-coh901.c#L350"eturn4.a href="+code=retirq" class="sref">retirqBITn4.a href="+codqBITaml2) naml2 L309">430929a>}>427129a>        .7 href77mber"naml2 L309">430929a>}>77u300_gpio_port" class-coh901.c#L350"eturn4.a href="+code=retirq" class="sref">retirdomain06" class="linedomain nam.ssL350">435029a> irivdomain_add_"lina;>/* Returning4-EINVA72351" cla7local_irq_save29a>(.a hr7f="+c77>>435029a> "sref30329PINS_PER_PORet29a>,4.a href="+cod30329aINS_PER_POReaml2 /a>.spa  class="comment">/* Returning4-EINVA72 class="7inctrl-coh901.c#L274" id7 L27477e" naml2 L304">430429aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaml2 L321">432129a>  irivdomain_simple_ops06" class="lineirivdomain_simple_opsaml2 /a>.spa  class="comment">/* Returning4-EINVA72901.c#L37IN_REG29a>(.a href="+cod7=offs77de=offset" class="sre L253 .alllllllllllllllllllllllllllllL350">435029a> eturn4.a href="+code=retirq3 naml2 L309">430929a>}>retirdomain06" class="linedomain nam3iass="sref">gpio29a>->.a href="+code=dev" c72/o_input7SK29a> << ((.a hre7="+co77                     llllllllL350">435029a> er;>435029a> ENOMEMss="line" naml2ENOMEM>43129a>        .a href="+code=local_irq_save" cl7i"sref">g7PIN_REG29a>(.a href="+co7e=off779a>{>dor29a>er;_na_domain06" class="lineer;_na_domain>43129a>        .a href="+code=local_irq_save" cl7ilass="sr7ctrl/pinctrl-coh901.c#L279" id77quot;could not locate./a>.spa  class="comment">/* Returning4-EINVA7i">dev29a7coh901.c#L281" id2 L281"7class77    rmode29a>;>nu321">432129a>  irivs29cchained_handl>;n4.a href="+codirivs29cchained_handl>;ctrl/-coh901.c#L350"eturn4.a href="+code=retirq" class="sref">retirirq>;n4.a href="+cod/pinctrl-cdrivhandl>;tirq3 naml2 L309">430929a>}>u300_gpio7direc78u300_gpio_port" class-coh901.c#L350"irivs29chandl>;_data06" class="lineirivs29chandl>;_datactrl/-coh901.c#L350"eturn4.a href="+code=retirq" class="sref">retirirq>430929a>}> *.a href="7code=78>>430929a>}>42878ss="line" naml2 L324" ace and request muxing,rFor each =offspod 2et t>e unique IRQ handl>;=*ruct4.a href="+code=gpio_chip" class="sref">gpio_chi7"901.c#L37f">u300_gpio29a> *.a hre7="+co78de=offset" class="srefor /pinctrl-coh901.r06" class="linei>431 = 0oe=offset" class=r06" class="linei>431 l" cl=offset" class="sref30329aINS_PER_PORet29a>,4.a href="+cod30329aINS_PER_POReaml22e=offset" class=r06" class="linei>431++ iass="sref">gpio29a>->.a href="+code=dev" c7code=NULL7lass="sref">to_u300_gpio79a>(.78 class="line" naml2 Laaaaaaaa>,>435029a> irivcreate_mapp    6" class="lineirivcreate_mapp   ctrl/-coh901.c#L350"eturn4.a href="+code=retirq" class="sref">retirdomain06" class="linedomain nam o id2 L290" clasr06" class="linei>4313 naml2 L309">430929a>}>428729a>        .7 href78     naml2 L309">430929a>}>g78" id2 L288" class="line7 naml789a>{>offset29a>,4Ŷ%d from port %d\n"./spa  ,>434029a>              3032href=d on rort href=srg29s IRQ href=d+code=retirq" class="sref">retirq29a>,4.a href="+code=port" 7class="sr7289" class="line" naml2 7289">78quot;could not locateeeeeeeee/pinctrlf">offset29a>,4              .a href="+code=port" class="sref"s="sref">offset29a>,>retirqumb>;n4.a href="+codqumb>;4290.l" cl" cl3) +s port for GPIO r06" class="linei>431lass="sref">retirq29a>,4.a href="+code=port" 7c">dev29a7local_irq_save29a>(.a hr7f="+c78    return4-.a href="llllllll/pinctrlf">offset29a>,4eturn4.a href="+code=retirq" class="sref">retirqBITn4.a href="+codqBITaml2 La href="driversrrqn2 L350" class="lrrqn2 nam3 naml2 L309">430929a>}>nuuuuuuuuu-coh901.c#L350"irivs29cchip_and_handl>;n4.a href="+codirivs29cchip_and_handl>;n"./spa  ,>432129a>  /pinctrl-cdrii            unsign/pinctrl-cdrii   >431lass="sref">retirq29a>,4.a href="+code=port" 7//o_outpu7IN_REG29a>(.a href="+cod7=offs79u300_gpio_port" class#L326" i.a href="llllllll/pinctrlf">offset29a>,4handl>_simple_irq>430929a>}>         * Driv7 mode79>>430929a>}>430429aaaaaaaa-coh901.c#L350"irivs29cchip_data06" class="lineirivs29cchip_datan"./spa  ,>430929a>}>/* Returning4-EINVA7code=NULL7ref="+code=oldmode" clas7="sre79 clas/a>.spa  class="comment">/* Returning4-EINVA7c/o_input7DE_MASK" class="sref">U370_GPI79                     face and request muxing,rTurns off rrqeforce (test register)efor this rort *ruct4.a href="+code=gpio_chip" class="sref">gpio_chi7P"sref">g798" id2 L298" class="lin7" nam799a>{>chipwass="line" naml2 L29wass="ctrl/0x0, t;./spa  ,>430929a>}>430929a>}>dev29a72 L300">430029a>        7     79    return4-.a href=" port for GPIO list_add_taief="+code=pcr" clist_add_taiectrl/ml2 L321">432129a>  eturn4.a href="+code=retirq" class="sref">retirq              .a hn   >431, ml2 L321">432129a>  ref="drivers/pinctrl/pinctrl-coh901.c#L340" id2e=re_listn4.a href="+code=re_list nam3 naml2 L309">430929a>}>/* Returning4-EINVA8_1XPCR_PI8_N_REG29a>(.a href="+cod8" nam80naml2 L253 .a href="+code=bo L3_4%d from port %d\n"./spa  ,>434029a>              initialized href=d =offsp=res+code=retirq" cl f="drivers/pinceturn2 L350" class="lrortn2 nam) naml2 L309">430929a>}>         * Driv8PULL280>>430929a>}>430929a>}>offset29a>,>435029a> r L340" class="linep" naml2l-coh901.c#L340" id2 L340" class="line" naml2. href="+code=bori_q              .a hri_q   4290 naml2 L309">430929a>}>430929a>}>U38"+cod80             ="sref">dor29a>er;>432129a>                .a href="+code=port" class="sref"s="sref">offset29a>,>430929a>}>{>gpio29a>->.a href="+code=dev" c8i8class="8r2 L299" class="line" na8class80quot;could not locate901.c#L340" id2 L3_er;>434029a>              unabl  to add ef="chip: href=d+code=retirq" cl ="sref">dor29a>er;>430929a>}>430029a>        82 L3180    return4-.a href="gotoe="sref">dor29a>er;_na_s="sref">offset29a>er;_na_s="s4290 naml2 L309">430929a>}>u300_gpio_to_irq29a8(stru81mber" class="./a>.spa  class="comment">/* Returning4-EINVA89a> *.a h8ef="+code=chip" class="s8ef">c81u300_/a>.spa  class="comment">/* Returning4-EINVA892XPCR_PI8f">u300_gpio29a> *.a hre8="+co81>>gpio_chi800_gpio" 8lass="sref">to_u300_gpio89a>(.81irqs q29a> =4.a href="+code=========,rAdd ss="srespod ranges, t>e pod ,ontroll>; must be registereduct4.a href="+code=gpio_chip" class="sref">gpio_chi804ctrl-co8/pinctrl-coh901.c#L315" 8d2 L381901.cq29a> =4.a href="+code=========,rat this rointuct4.a href="+code=gpio_chip" class="sref">gpio_chi805ctrl-co8 class="sref">NULL29a>;>8a hre81 clasq29a> =4.a href="+code=========,ruct4.a href="+code=gpio_chip" class="sref">gpio_chi896ctrl-co801.c#L317" id2 L317" cla8s="li81             for /pinctrl-coh901.r06" class="linei>431 = 0oe=offset" class=r06" class="linei>431 l" cl=offset" class=ARRAY_SIZEss="line" naml2ARRAY_SIZEctrl/-coh901.c#L350"">gpio_pintabl   return40;>gpio_pintabl inct)2e=offset" class=r06" class="linei>431++ iass="sref">gpio29a>->.a href="+code=dev" c8civers/pi831829a>        .a href="8code=819a>{>chip">gpio_pinpai;>gpio_pinpai;L298"l-coh901.c#L350"e40" class="linep>431 = ml2 L321">432129a>  ">gpio_pintabl   return40;>gpio_pintabl inct[=offset" class=r06" class="linei>431] naml2 L309">430929a>}>430929a>}>(.a href8"+cod81    return4-.a href="="sref">dor29a>er;>432129a>                .a href="+code=port" class="sref"s="sref">offset29a>,>434029a>              ref="dri/pinode=retirq" class="sref">retirq29a>,4.a href="+code=port" 8lass="sre8">gpio29a>->.a href="8code=82mber" class="sref">nuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-coh901.c#L350"e40" class="linep>431e=port" class="sref"ritel" class="sref">writel29a>(l f="drivers/pince40" class="linep>431e=port" class="sref"pef_base06" class="lineref_base9a>(, 1) naml2 L309">430929a>}>p29a>, struct4.a href8"+cod82u300_gpio_port" classrl-coh901.c#L323" ier;>430929a>}>portno29a>) {><8 href82>>dor29a>er;_na_range          .a hrer;_na_range4290 naml2 L309">430929a>}>.spa  class="comment">/* Returning4-EINVA8    }>.spa  class="comment">/* Returning4-EINVA8 5ctrl-co8pinctrl-coh901.c#L327" i82 L3282 class="line"pid2 L290" clasrlatform_s29cdrvdata06" class="linerlatform_s29cdrvdatactrl/-coh901.c#L350"e L340" class="linep" naml2ctrl-coh901.c#L26ref="drivers/pinctrl/pinctr) naml2 L309">430929a>}>found29a>) {>430929a>}>;8>dev29a>,4.spa  class="s8ring"828clasnaml2 L309">430929a>}>433029a>    8     82    r="sref">dor29a>er;_na_range          .a hrer;_na_range4290:naml2 L309">430929a>}>433129a>     8  }><83+code=u32" cl>l-coh901.c#L323" i id2chip_remove          .a href="chip_removectrl/ml2 L321">432129a>                .a href="+code=port" class="sref"s="sref">offset29a>,>430929a>}>432129a>  e L340" class="linep" naml2l-coh901.c#L340" id2 L340" class="line" naml2 Ln40">434029a>              failed to remove ef=" ,>430929a>}>>dor29a>er;_na_s="sref">offset29a>er;_na_s="s4290:naml2 L309">430929a>}>         * The 8ocal 839a>{>="sref">dor29a>er;_na_domain06" class="lineer;_na_domain>431:naml2 L309">430929a>}>dor29a>er;_na_eturn4.a href="+coder;_na_etur>431:naml2 L309">430929a>}>4383 class="line"pid2 L290" clas/pinctrl-cfree_eturs06" class="line/pinctrl-cfree_etursctrl/-coh901.c#L350"ref="drivers/pinctrl/pinctr) naml2 L309">430929a>}>dor29a>"lk_disabl _unprepareref">offset29a>,lk_disabl _unpreparectrl/-coh901.c#L350"ref="drivers/pinctrl/pinctrl-coh901.c#L340" id2slk06" class="lineslk9a>() naml2 L309">430929a>}>port29a>-&8t;.a 839a>{>432129a>  e L340" class="linep" naml2l-coh901.c#L340" id2 L340" class="line" naml2 Ln40">434029a>              module ERROR:href=d+code=retirq" cl ="sref">dor29a>er;>430929a>}>430929a>}>&8uot;r83    r./a>.spa  class="comment">/* Returning4-EINVA8lass="sre8">port29a>->.a href="8code=84mber"naml2 L309">430929a>}>434229a>}>chiprlatform_" nice06" class="lineclatform_" niceL298"l-coh901.c#L350"e L340" class="linep" naml23naml2 L309">430929a>}>>gpio29a>->.a href="+code=dev" c8c  class=8ot;supported but not ava8lable84irqs on the phip" class="sref">chip29a>);>435029a> rlatform_g29cdrvdata06" class="linerlatform_g29cdrvdatactrl/-coh901.c#L350"e L340" class="linep" naml2) naml2 L309">430929a>}>,>( naml2 L309">430929a>}>84 clas/a>.spa  class="comment">/* Returning4-EINVA8l6ctrl-co8s="line" naml2 L347">434829a> 84             =ace and request muxing,rTurn off t>e =offsblock ,ruct4.a href="+code=gpio_chip" class="sref">gpio_chi8" id2 L348" class="line" naml2 L348">434849a>{>() naml2 L309">430929a>}>u300_gpio29a> *.a hre8="+co848clasnaml2 L309">430929a>}>to_u300_gpio89a>(.849a>{>432129a>                .a href="+code=port" class="sref"s="sref">offset29a>,>430929a>}>l-coh901.c#L323" ier;>gpio29a>->.a href="+code=dev" c8acoh901.c8#L351" id2 L342" " class8"line85u300_gpio_port" class-coh901.c#L350" L3_er;>434029a>              unabl  to remove ef="chip: href=d+code=retirq" cl ="sref">dor29a>er;>430929a>}>435829a> 85>>430929a>}>423229a8>.spa  class="comment">/* Returning4-EINVA8"901.c#L38inctrl/pinctrl-coh905e178s="li85901.c#L326" i id2 L290" clas/pinctrl-cfree_eturs06" class="line/pinctrl-cfree_etursctrl/-coh901.c#L350"ref="drivers/pinctrl/pinctr) naml2 L309">430929a>}>offset29a>,lk_disabl _unpreparectrl/-coh901.c#L350"ref="drivers/pinctrl/pinctrl-coh901.c#L340" id2slk06" class="lineslk9a>() naml2 L309">430929a>}>>/* Returning4-EINVA8"lse29a>;8IN_REG29a>(.a href="+cod8=offs858clasnaml2 L309">430929a>}>dev29a8029a>                .a 8ref="85    rstatic constphip" class="sref">chipof_" nice_id          .a hrof_" nice_iduot;cpid2 L290" clas/pinctrl-cmatch06" class="line/pinctrl-cmatchinct[].ssass="sref">gpio29a>->.a href="+code=dev" c8 class="s8ef">U300_PIN_BIT29a>(.a 8ref="86mber" class="{ . href="+code=boestpatibl   return40;>tpatibl 9a>(.ss940">434029a>              stericsson,trl-code=deode=retirq" c }lass="sref">retirq29a>,4.a href="+code=port" 8 -coh901.8lass="sref">writel29a>(.8 href86u300_gpio_por{}lass="sref">retirq29a>,4.a href="+code=port" 8 351" cla8s="sref">U300_PIN_BIT29a8(.a h86>>>local_irq_restore29a>8.a hr86ss="l29a>>chiprlatform_"f="dr06" class="lineclatform_"f="druot;cpid2 L290" clas/pinctrl-c"f="dr06" class="line/pinctrl-c"f="dr9a>(.ssass="sref">gpio29a>->.a href="+code=dev" c8 ode=NULL82 L267" class="line" nam82 L2686 class="line". href="+code=bo"f="dr06" class="line"f="dr9a>(.........ssass="sref">gpio29a>->.a href="+code=dev" c8 347" cla8 class="sref">u300_gpio_8irec286                     . href="+code=boqBITn4.a href="+codqBITaml2...ssn40">434029a>              upin-l/pihde=retirq" class="sref">retirq29a>,4.a href="+code=port" 8  id2 L348io_chip29a> *.a href="+c8de=ch869a>{>(.ss901.c#L340" id2/pinctrl-cmatch06" class="line/pinctrl-cmatchinctlass="sref">retirq29a>,4.a href="+code=port" 8 lse29a>;8f">u300_gpio29a> *.a hre8="+co86quot;could no}lass="sref">retirq29a>,4.a href="+code=port" 8 ">dev29a8lass="sref">to_u300_gpio89a>(.86    return4-.. href="+code=boremove          .a hrremovectrl.........ssa href="drivers__exir_sref">offset29a>__exir_sctrl/-coh901.c#L350"/pinctrl-cremove          .a hr/pinctrl-cremovectrl)lass="sref">retirq29a>,4.a href="+code=port" 8ine" naml8 L271">427129a>        .8 href87mber"}029a>>87u300_/a>.spa  class="comment">/* Returning4-EINVA82351" cla8local_irq_save29a>(.a hr8f="+c87>>,>offset29a>__inituot;cpid2 L290" clas/pinctrl-cinitref">offset29a>/pinctrl-cinitctrl/void3naml2 L309">430929a>}>gpio29a>->.a href="+code=dev" c82901.c#L38IN_REG29a>(.a href="+cod8=offs87de=offset" clreturn 901.c#L340" id2clatform_"f="dr_probe06" class="lineclatform_"f="dr_probectrl/ml2 L321">432129a>  /pinctrl-c"f="dr06" class="line/pinctrl-c"f="dr9a>( o id2 L290" clas/pinctrl-cprobe06" class="line/pinctrl-cprobe9a>() naml2 L309">430929a>}>.spa  class="comment">/* Returning4-EINVA82/o_input8SK29a> << ((.a hre8="+co87     naml2 L309">430929a>}>g8PIN_REG29a>(.a href="+co8e=off879a>{>static void430929a>}>gpio29a>->.a href="+code=dev" c82">dev29a8coh901.c#L281" id2 L281"8class879a>{>432129a>  /pinctrl-c"f="dr06" class="line/pinctrl-c"f="dr9a>() naml2 L309">430929a>}>.spa  class="comment">/* Returning4-EINVA8c72" id2 8" class="sref">u300_gpio8direc88u300_/a>.spa  class="comment">/* Returning4-EINVA8c351" cla8gpio_chip29a> *.a href="8code=88>>dor29a>arch_initcal"line" naml2 L29arch_initcal"ctrl/-coh901.c#L350"/pinctrl-cinitref">offset29a>/pinctrl-cinitctrl) naml2 L309">430929a>}>428889a>{>="sref">dor29a>modulecexirn4.a href="+codmodulecexirctrl/-coh901.c#L350"/pinctrl-cexirn4.a href="+cod/pinctrl-cexirctrl) naml2 L309">430929a>}>u300_gpio29a> *.a hre8="+co88" nam/a>.spa  class="comment">/* Returning4-EINVA8code=NULL8lass="sref">to_u300_gpio89a>(.88 clas-coh901.c#L350"MODULE_AUTHORss="line" naml2MODULE_AUTHORctrl/-40">434029a>              Linus Wal"eij.l" clinus.wal"eij@stericsson.com-coh-de=retirq" c) naml2 L309">430929a>}>428729a>        .8 href88     -coh901.c#L350"MODULE_DESCRIPTIONss="line" naml2MODULE_DESCRIPTIONctrl/-40">434029a>              ST-Ericsson AB COH 4-E>335/COH 4-E>57n/3 =offs">4309-de=retirq" c) naml2 L309">430929a>}>g88" id2 L288" class="line8 naml889a>{>-coh901.c#L350"MODULE_LICENSEss="line" naml2MODULE_LICENSEctrl/-40">434029a>              GPL-de=retirq" c) naml2 L309">430929a>}>88quot;





The original LXR software by t>e aml2 L309http://sourceforge.net/projects/lxr0>LXR est unity9a>( othis experi muxal 3092ion by aml2 L309mailto:lxr@linux.no">lxr@linux.no9a>(.


lxr.linux.no kindly hosted by aml2 L309http://www.redpill-linpro.no">Redpill Linpro AS9a>( oprovid>; of Linux consult0_gpand operations sernices sef=e 1995.