linux/drivers/mfd/sm501.c
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   1/* linux/drivers/mfd/sm501.c
   2 *
   3 * Copyright (C) 2006 Simtec Electronics
   4 *      Ben Dooks <ben@simtec.co.uk>
   5 *      Vincent Sanders <vince@simtec.co.uk>
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 *
  11 * SM501 MFD driver
  12*/
  13
  14#include <linux/kernel.h>
  15#include <linux/module.h>
  16#include <linux/delay.h>
  17#include <linux/init.h>
  18#include <linux/list.h>
  19#include <linux/device.h>
  20#include <linux/platform_device.h>
  21#include <linux/pci.h>
  22#include <linux/i2c-gpio.h>
  23#include <linux/slab.h>
  24
  25#include <linux/sm501.h>
  26#include <linux/sm501-regs.h>
  27#include <linux/serial_8250.h>
  28
  29#include <linux/io.h>
  30
  31struct sm501_device {
  32        struct list_head                list;
  33        struct platform_device          pdev;
  34};
  35
  36struct sm501_gpio;
  37
  38#ifdef CONFIG_MFD_SM501_GPIO
  39#include <linux/gpio.h>
  40
  41struct sm501_gpio_chip {
  42        struct gpio_chip        gpio;
  43        struct sm501_gpio       *ourgpio;       /* to get back to parent. */
  44        void __iomem            *regbase;
  45        void __iomem            *control;       /* address of control reg. */
  46};
  47
  48struct sm501_gpio {
  49        struct sm501_gpio_chip  low;
  50        struct sm501_gpio_chip  high;
  51        spinlock_t              lock;
  52
  53        unsigned int             registered : 1;
  54        void __iomem            *regs;
  55        struct resource         *regs_res;
  56};
  57#else
  58struct sm501_gpio {
  59        /* no gpio support, empty definition for sm501_devdata. */
  60};
  61#endif
  62
  63struct sm501_devdata {
  64        spinlock_t                       reg_lock;
  65        struct mutex                     clock_lock;
  66        struct list_head                 devices;
  67        struct sm501_gpio                gpio;
  68
  69        struct device                   *dev;
  70        struct resource                 *io_res;
  71        struct resource                 *mem_res;
  72        struct resource                 *regs_claim;
  73        struct sm501_platdata           *platdata;
  74
  75
  76        unsigned int                     in_suspend;
  77        unsigned long                    pm_misc;
  78
  79        int                              unit_power[20];
  80        unsigned int                     pdev_id;
  81        unsigned int                     irq;
  82        void __iomem                    *regs;
  83        unsigned int                     rev;
  84};
  85
  86
  87#define MHZ (1000 * 1000)
  88
  89#ifdef DEBUG
  90static const unsigned int div_tab[] = {
  91        [0]             = 1,
  92        [1]             = 2,
  93        [2]             = 4,
  94        [3]             = 8,
  95        [4]             = 16,
  96        [5]             = 32,
  97        [6]             = 64,
  98        [7]             = 128,
  99        [8]             = 3,
 100        [9]             = 6,
 101        [10]            = 12,
 102        [11]            = 24,
 103        [12]            = 48,
 104        [13]            = 96,
 105        [14]            = 192,
 106        [15]            = 384,
 107        [16]            = 5,
 108        [17]            = 10,
 109        [18]            = 20,
 110        [19]            = 40,
 111        [20]            = 80,
 112        [21]            = 160,
 113        [22]            = 320,
 114        [23]            = 604,
 115};
 116
 117static unsigned long decode_div(unsigned long pll2, unsigned long val,
 118                                unsigned int lshft, unsigned int selbit,
 119                                unsigned long mask)
 120{
 121        if (val & selbit)
 122                pll2 = 288 * MHZ;
 123
 124        return pll2 / div_tab[(val >> lshft) & mask];
 125}
 126
 127#define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
 128
 129/* sm501_dump_clk
 130 *
 131 * Print out the current clock configuration for the device
 132*/
 133
 134static void sm501_dump_clk(struct sm501_devdata *sm)
 135{
 136        unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING);
 137        unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
 138        unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
 139        unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
 140        unsigned long sdclk0, sdclk1;
 141        unsigned long pll2 = 0;
 142
 143        switch (misct & 0x30) {
 144        case 0x00:
 145                pll2 = 336 * MHZ;
 146                break;
 147        case 0x10:
 148                pll2 = 288 * MHZ;
 149                break;
 150        case 0x20:
 151                pll2 = 240 * MHZ;
 152                break;
 153        case 0x30:
 154                pll2 = 192 * MHZ;
 155                break;
 156        }
 157
 158        sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
 159        sdclk0 /= div_tab[((misct >> 8) & 0xf)];
 160
 161        sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
 162        sdclk1 /= div_tab[((misct >> 16) & 0xf)];
 163
 164        dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
 165                misct, pm0, pm1);
 166
 167        dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
 168                fmt_freq(pll2), sdclk0, sdclk1);
 169
 170        dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
 171
 172        dev_dbg(sm->dev, "PM0[%c]: "
 173                 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
 174                 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
 175                 (pmc & 3 ) == 0 ? '*' : '-',
 176                 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
 177                 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
 178                 fmt_freq(decode_div(pll2, pm0, 8,  1<<12, 15)),
 179                 fmt_freq(decode_div(pll2, pm0, 0,  1<<4,  15)));
 180
 181        dev_dbg(sm->dev, "PM1[%c]: "
 182                "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
 183                "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
 184                (pmc & 3 ) == 1 ? '*' : '-',
 185                fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
 186                fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
 187                fmt_freq(decode_div(pll2, pm1, 8,  1<<12, 15)),
 188                fmt_freq(decode_div(pll2, pm1, 0,  1<<4,  15)));
 189}
 190
 191static void sm501_dump_regs(struct sm501_devdata *sm)
 192{
 193        void __iomem *regs = sm->regs;
 194
 195        dev_info(sm->dev, "System Control   %08x\n",
 196                        smc501_readl(regs + SM501_SYSTEM_CONTROL));
 197        dev_info(sm->dev, "Misc Control     %08x\n",
 198                        smc501_readl(regs + SM501_MISC_CONTROL));
 199        dev_info(sm->dev, "GPIO Control Low %08x\n",
 200                        smc501_readl(regs + SM501_GPIO31_0_CONTROL));
 201        dev_info(sm->dev, "GPIO Control Hi  %08x\n",
 202                        smc501_readl(regs + SM501_GPIO63_32_CONTROL));
 203        dev_info(sm->dev, "DRAM Control     %08x\n",
 204                        smc501_readl(regs + SM501_DRAM_CONTROL));
 205        dev_info(sm->dev, "Arbitration Ctrl %08x\n",
 206                        smc501_readl(regs + SM501_ARBTRTN_CONTROL));
 207        dev_info(sm->dev, "Misc Timing      %08x\n",
 208                        smc501_readl(regs + SM501_MISC_TIMING));
 209}
 210
 211static void sm501_dump_gate(struct sm501_devdata *sm)
 212{
 213        dev_info(sm->dev, "CurrentGate      %08x\n",
 214                        smc501_readl(sm->regs + SM501_CURRENT_GATE));
 215        dev_info(sm->dev, "CurrentClock     %08x\n",
 216                        smc501_readl(sm->regs + SM501_CURRENT_CLOCK));
 217        dev_info(sm->dev, "PowerModeControl %08x\n",
 218                        smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL));
 219}
 220
 221#else
 222static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
 223static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
 224static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
 225#endif
 226
 227/* sm501_sync_regs
 228 *
 229 * ensure the
 230*/
 231
 232static void sm501_sync_regs(struct sm501_devdata *sm)
 233{
 234        smc501_readl(sm->regs);
 235}
 236
 237static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
 238{
 239        /* during suspend/resume, we are currently not allowed to sleep,
 240         * so change to using mdelay() instead of msleep() if we
 241         * are in one of these paths */
 242
 243        if (sm->in_suspend)
 244                mdelay(delay);
 245        else
 246                msleep(delay);
 247}
 248
 249/* sm501_misc_control
 250 *
 251 * alters the miscellaneous control parameters
 252*/
 253
 254int sm501_misc_control(struct device *dev,
 255                       unsigned long set, unsigned long clear)
 256{
 257        struct sm501_devdata *sm = dev_get_drvdata(dev);
 258        unsigned long misc;
 259        unsigned long save;
 260        unsigned long to;
 261
 262        spin_lock_irqsave(&sm->reg_lock, save);
 263
 264        misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
 265        to = (misc & ~clear) | set;
 266
 267        if (to != misc) {
 268                smc501_writel(to, sm->regs + SM501_MISC_CONTROL);
 269                sm501_sync_regs(sm);
 270
 271                dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
 272        }
 273
 274        spin_unlock_irqrestore(&sm->reg_lock, save);
 275        return to;
 276}
 277
 278EXPORT_SYMBOL_GPL(sm501_misc_control);
 279
 280/* sm501_modify_reg
 281 *
 282 * Modify a register in the SM501 which may be shared with other
 283 * drivers.
 284*/
 285
 286unsigned long sm501_modify_reg(struct device *dev,
 287                               unsigned long reg,
 288                               unsigned long set,
 289                               unsigned long clear)
 290{
 291        struct sm501_devdata *sm = dev_get_drvdata(dev);
 292        unsigned long data;
 293        unsigned long save;
 294
 295        spin_lock_irqsave(&sm->reg_lock, save);
 296
 297        data = smc501_readl(sm->regs + reg);
 298        data |= set;
 299        data &= ~clear;
 300
 301        smc501_writel(data, sm->regs + reg);
 302        sm501_sync_regs(sm);
 303
 304        spin_unlock_irqrestore(&sm->reg_lock, save);
 305
 306        return data;
 307}
 308
 309EXPORT_SYMBOL_GPL(sm501_modify_reg);
 310
 311/* sm501_unit_power
 312 *
 313 * alters the power active gate to set specific units on or off
 314 */
 315
 316int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
 317{
 318        struct sm501_devdata *sm = dev_get_drvdata(dev);
 319        unsigned long mode;
 320        unsigned long gate;
 321        unsigned long clock;
 322
 323        mutex_lock(&sm->clock_lock);
 324
 325        mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
 326        gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
 327        clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
 328
 329        mode &= 3;              /* get current power mode */
 330
 331        if (unit >= ARRAY_SIZE(sm->unit_power)) {
 332                dev_err(dev, "%s: bad unit %d\n", __func__, unit);
 333                goto already;
 334        }
 335
 336        dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
 337                sm->unit_power[unit], to);
 338
 339        if (to == 0 && sm->unit_power[unit] == 0) {
 340                dev_err(sm->dev, "unit %d is already shutdown\n", unit);
 341                goto already;
 342        }
 343
 344        sm->unit_power[unit] += to ? 1 : -1;
 345        to = sm->unit_power[unit] ? 1 : 0;
 346
 347        if (to) {
 348                if (gate & (1 << unit))
 349                        goto already;
 350                gate |= (1 << unit);
 351        } else {
 352                if (!(gate & (1 << unit)))
 353                        goto already;
 354                gate &= ~(1 << unit);
 355        }
 356
 357        switch (mode) {
 358        case 1:
 359                smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
 360                smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
 361                mode = 0;
 362                break;
 363        case 2:
 364        case 0:
 365                smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
 366                smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
 367                mode = 1;
 368                break;
 369
 370        default:
 371                gate = -1;
 372                goto already;
 373        }
 374
 375        smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
 376        sm501_sync_regs(sm);
 377
 378        dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
 379                gate, clock, mode);
 380
 381        sm501_mdelay(sm, 16);
 382
 383 already:
 384        mutex_unlock(&sm->clock_lock);
 385        return gate;
 386}
 387
 388EXPORT_SYMBOL_GPL(sm501_unit_power);
 389
 390/* clock value structure. */
 391struct sm501_clock {
 392        unsigned long mclk;
 393        int divider;
 394        int shift;
 395        unsigned int m, n, k;
 396};
 397
 398/* sm501_calc_clock
 399 *
 400 * Calculates the nearest discrete clock frequency that
 401 * can be achieved with the specified input clock.
 402 *   the maximum divisor is 3 or 5
 403 */
 404
 405static int sm501_calc_clock(unsigned long freq,
 406                            struct sm501_clock *clock,
 407                            int max_div,
 408                            unsigned long mclk,
 409                            long *best_diff)
 410{
 411        int ret = 0;
 412        int divider;
 413        int shift;
 414        long diff;
 415
 416        /* try dividers 1 and 3 for CRT and for panel,
 417           try divider 5 for panel only.*/
 418
 419        for (divider = 1; divider <= max_div; divider += 2) {
 420                /* try all 8 shift values.*/
 421                for (shift = 0; shift < 8; shift++) {
 422                        /* Calculate difference to requested clock */
 423                        diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;
 424                        if (diff < 0)
 425                                diff = -diff;
 426
 427                        /* If it is less than the current, use it */
 428                        if (diff < *best_diff) {
 429                                *best_diff = diff;
 430
 431                                clock->mclk = mclk;
 432                                clock->divider = divider;
 433                                clock->shift = shift;
 434                                ret = 1;
 435                        }
 436                }
 437        }
 438
 439        return ret;
 440}
 441
 442/* sm501_calc_pll
 443 *
 444 * Calculates the nearest discrete clock frequency that can be
 445 * achieved using the programmable PLL.
 446 *   the maximum divisor is 3 or 5
 447 */
 448
 449static unsigned long sm501_calc_pll(unsigned long freq,
 450                                        struct sm501_clock *clock,
 451                                        int max_div)
 452{
 453        unsigned long mclk;
 454        unsigned int m, n, k;
 455        long best_diff = 999999999;
 456
 457        /*
 458         * The SM502 datasheet doesn't specify the min/max values for M and N.
 459         * N = 1 at least doesn't work in practice.
 460         */
 461        for (m = 2; m <= 255; m++) {
 462                for (n = 2; n <= 127; n++) {
 463                        for (k = 0; k <= 1; k++) {
 464                                mclk = (24000000UL * m / n) >> k;
 465
 466                                if (sm501_calc_clock(freq, clock, max_div,
 467                                                     mclk, &best_diff)) {
 468                                        clock->m = m;
 469                                        clock->n = n;
 470                                        clock->k = k;
 471                                }
 472                        }
 473                }
 474        }
 475
 476        /* Return best clock. */
 477        return clock->mclk / (clock->divider << clock->shift);
 478}
 479
 480/* sm501_select_clock
 481 *
 482 * Calculates the nearest discrete clock frequency that can be
 483 * achieved using the 288MHz and 336MHz PLLs.
 484 *   the maximum divisor is 3 or 5
 485 */
 486
 487static unsigned long sm501_select_clock(unsigned long freq,
 488                                        struct sm501_clock *clock,
 489                                        int max_div)
 490{
 491        unsigned long mclk;
 492        long best_diff = 999999999;
 493
 494        /* Try 288MHz and 336MHz clocks. */
 495        for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
 496                sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
 497        }
 498
 499        /* Return best clock. */
 500        return clock->mclk / (clock->divider << clock->shift);
 501}
 502
 503/* sm501_set_clock
 504 *
 505 * set one of the four clock sources to the closest available frequency to
 506 *  the one specified
 507*/
 508
 509unsigned long sm501_set_clock(struct device *dev,
 510                              int clksrc,
 511                              unsigned long req_freq)
 512{
 513        struct sm501_devdata *sm = dev_get_drvdata(dev);
 514        unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
 515        unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
 516        unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
 517        unsigned char reg;
 518        unsigned int pll_reg = 0;
 519        unsigned long sm501_freq; /* the actual frequency achieved */
 520
 521        struct sm501_clock to;
 522
 523        /* find achivable discrete frequency and setup register value
 524         * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
 525         * has an extra bit for the divider */
 526
 527        switch (clksrc) {
 528        case SM501_CLOCK_P2XCLK:
 529                /* This clock is divided in half so to achieve the
 530                 * requested frequency the value must be multiplied by
 531                 * 2. This clock also has an additional pre divisor */
 532
 533                if (sm->rev >= 0xC0) {
 534                        /* SM502 -> use the programmable PLL */
 535                        sm501_freq = (sm501_calc_pll(2 * req_freq,
 536                                                     &to, 5) / 2);
 537                        reg = to.shift & 0x07;/* bottom 3 bits are shift */
 538                        if (to.divider == 3)
 539                                reg |= 0x08; /* /3 divider required */
 540                        else if (to.divider == 5)
 541                                reg |= 0x10; /* /5 divider required */
 542                        reg |= 0x40; /* select the programmable PLL */
 543                        pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
 544                } else {
 545                        sm501_freq = (sm501_select_clock(2 * req_freq,
 546                                                         &to, 5) / 2);
 547                        reg = to.shift & 0x07;/* bottom 3 bits are shift */
 548                        if (to.divider == 3)
 549                                reg |= 0x08; /* /3 divider required */
 550                        else if (to.divider == 5)
 551                                reg |= 0x10; /* /5 divider required */
 552                        if (to.mclk != 288000000)
 553                                reg |= 0x20; /* which mclk pll is source */
 554                }
 555                break;
 556
 557        case SM501_CLOCK_V2XCLK:
 558                /* This clock is divided in half so to achieve the
 559                 * requested frequency the value must be multiplied by 2. */
 560
 561                sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
 562                reg=to.shift & 0x07;    /* bottom 3 bits are shift */
 563                if (to.divider == 3)
 564                        reg |= 0x08;    /* /3 divider required */
 565                if (to.mclk != 288000000)
 566                        reg |= 0x10;    /* which mclk pll is source */
 567                break;
 568
 569        case SM501_CLOCK_MCLK:
 570        case SM501_CLOCK_M1XCLK:
 571                /* These clocks are the same and not further divided */
 572
 573                sm501_freq = sm501_select_clock( req_freq, &to, 3);
 574                reg=to.shift & 0x07;    /* bottom 3 bits are shift */
 575                if (to.divider == 3)
 576                        reg |= 0x08;    /* /3 divider required */
 577                if (to.mclk != 288000000)
 578                        reg |= 0x10;    /* which mclk pll is source */
 579                break;
 580
 581        default:
 582                return 0; /* this is bad */
 583        }
 584
 585        mutex_lock(&sm->clock_lock);
 586
 587        mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
 588        gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
 589        clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
 590
 591        clock = clock & ~(0xFF << clksrc);
 592        clock |= reg<<clksrc;
 593
 594        mode &= 3;      /* find current mode */
 595
 596        switch (mode) {
 597        case 1:
 598                smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
 599                smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
 600                mode = 0;
 601                break;
 602        case 2:
 603        case 0:
 604                smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
 605                smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
 606                mode = 1;
 607                break;
 608
 609        default:
 610                mutex_unlock(&sm->clock_lock);
 611                return -1;
 612        }
 613
 614        smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
 615
 616        if (pll_reg)
 617                smc501_writel(pll_reg,
 618                                sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
 619
 620        sm501_sync_regs(sm);
 621
 622        dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
 623                gate, clock, mode);
 624
 625        sm501_mdelay(sm, 16);
 626        mutex_unlock(&sm->clock_lock);
 627
 628        sm501_dump_clk(sm);
 629
 630        return sm501_freq;
 631}
 632
 633EXPORT_SYMBOL_GPL(sm501_set_clock);
 634
 635/* sm501_find_clock
 636 *
 637 * finds the closest available frequency for a given clock
 638*/
 639
 640unsigned long sm501_find_clock(struct device *dev,
 641                               int clksrc,
 642                               unsigned long req_freq)
 643{
 644        struct sm501_devdata *sm = dev_get_drvdata(dev);
 645        unsigned long sm501_freq; /* the frequency achieveable by the 501 */
 646        struct sm501_clock to;
 647
 648        switch (clksrc) {
 649        case SM501_CLOCK_P2XCLK:
 650                if (sm->rev >= 0xC0) {
 651                        /* SM502 -> use the programmable PLL */
 652                        sm501_freq = (sm501_calc_pll(2 * req_freq,
 653                                                     &to, 5) / 2);
 654                } else {
 655                        sm501_freq = (sm501_select_clock(2 * req_freq,
 656                                                         &to, 5) / 2);
 657                }
 658                break;
 659
 660        case SM501_CLOCK_V2XCLK:
 661                sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
 662                break;
 663
 664        case SM501_CLOCK_MCLK:
 665        case SM501_CLOCK_M1XCLK:
 666                sm501_freq = sm501_select_clock(req_freq, &to, 3);
 667                break;
 668
 669        default:
 670                sm501_freq = 0;         /* error */
 671        }
 672
 673        return sm501_freq;
 674}
 675
 676EXPORT_SYMBOL_GPL(sm501_find_clock);
 677
 678static struct sm501_device *to_sm_device(struct platform_device *pdev)
 679{
 680        return container_of(pdev, struct sm501_device, pdev);
 681}
 682
 683/* sm501_device_release
 684 *
 685 * A release function for the platform devices we create to allow us to
 686 * free any items we allocated
 687*/
 688
 689static void sm501_device_release(struct device *dev)
 690{
 691        kfree(to_sm_device(to_platform_device(dev)));
 692}
 693
 694/* sm501_create_subdev
 695 *
 696 * Create a skeleton platform device with resources for passing to a
 697 * sub-driver
 698*/
 699
 700static struct platform_device *
 701sm501_create_subdev(struct sm501_devdata *sm, char *name,
 702                    unsigned int res_count, unsigned int platform_data_size)
 703{
 704        struct sm501_device *smdev;
 705
 706        smdev = kzalloc(sizeof(struct sm501_device) +
 707                        (sizeof(struct resource) * res_count) +
 708                        platform_data_size, GFP_KERNEL);
 709        if (!smdev)
 710                return NULL;
 711
 712        smdev->pdev.dev.release = sm501_device_release;
 713
 714        smdev->pdev.name = name;
 715        smdev->pdev.id = sm->pdev_id;
 716        smdev->pdev.dev.parent = sm->dev;
 717
 718        if (res_count) {
 719                smdev->pdev.resource = (struct resource *)(smdev+1);
 720                smdev->pdev.num_resources = res_count;
 721        }
 722        if (platform_data_size)
 723                smdev->pdev.dev.platform_data = (void *)(smdev+1);
 724
 725        return &smdev->pdev;
 726}
 727
 728/* sm501_register_device
 729 *
 730 * Register a platform device created with sm501_create_subdev()
 731*/
 732
 733static int sm501_register_device(struct sm501_devdata *sm,
 734                                 struct platform_device *pdev)
 735{
 736        struct sm501_device *smdev = to_sm_device(pdev);
 737        int ptr;
 738        int ret;
 739
 740        for (ptr = 0; ptr < pdev->num_resources; ptr++) {
 741                printk(KERN_DEBUG "%s[%d] %pR\n",
 742                       pdev->name, ptr, &pdev->resource[ptr]);
 743        }
 744
 745        ret = platform_device_register(pdev);
 746
 747        if (ret >= 0) {
 748                dev_dbg(sm->dev, "registered %s\n", pdev->name);
 749                list_add_tail(&smdev->list, &sm->devices);
 750        } else
 751                dev_err(sm->dev, "error registering %s (%d)\n",
 752                        pdev->name, ret);
 753
 754        return ret;
 755}
 756
 757/* sm501_create_subio
 758 *
 759 * Fill in an IO resource for a sub device
 760*/
 761
 762static void sm501_create_subio(struct sm501_devdata *sm,
 763                               struct resource *res,
 764                               resource_size_t offs,
 765                               resource_size_t size)
 766{
 767        res->flags = IORESOURCE_MEM;
 768        res->parent = sm->io_res;
 769        res->start = sm->io_res->start + offs;
 770        res->end = res->start + size - 1;
 771}
 772
 773/* sm501_create_mem
 774 *
 775 * Fill in an MEM resource for a sub device
 776*/
 777
 778static void sm501_create_mem(struct sm501_devdata *sm,
 779                             struct resource *res,
 780                             resource_size_t *offs,
 781                             resource_size_t size)
 782{
 783        *offs -= size;          /* adjust memory size */
 784
 785        res->flags = IORESOURCE_MEM;
 786        res->parent = sm->mem_res;
 787        res->start = sm->mem_res->start + *offs;
 788        res->end = res->start + size - 1;
 789}
 790
 791/* sm501_create_irq
 792 *
 793 * Fill in an IRQ resource for a sub device
 794*/
 795
 796static void sm501_create_irq(struct sm501_devdata *sm,
 797                             struct resource *res)
 798{
 799        res->flags = IORESOURCE_IRQ;
 800        res->parent = NULL;
 801        res->start = res->end = sm->irq;
 802}
 803
 804static int sm501_register_usbhost(struct sm501_devdata *sm,
 805                                  resource_size_t *mem_avail)
 806{
 807        struct platform_device *pdev;
 808
 809        pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
 810        if (!pdev)
 811                return -ENOMEM;
 812
 813        sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
 814        sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
 815        sm501_create_irq(sm, &pdev->resource[2]);
 816
 817        return sm501_register_device(sm, pdev);
 818}
 819
 820static void sm501_setup_uart_data(struct sm501_devdata *sm,
 821                                  struct plat_serial8250_port *uart_data,
 822                                  unsigned int offset)
 823{
 824        uart_data->membase = sm->regs + offset;
 825        uart_data->mapbase = sm->io_res->start + offset;
 826        uart_data->iotype = UPIO_MEM;
 827        uart_data->irq = sm->irq;
 828        uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
 829        uart_data->regshift = 2;
 830        uart_data->uartclk = (9600 * 16);
 831}
 832
 833static int sm501_register_uart(struct sm501_devdata *sm, int devices)
 834{
 835        struct platform_device *pdev;
 836        struct plat_serial8250_port *uart_data;
 837
 838        pdev = sm501_create_subdev(sm, "serial8250", 0,
 839                                   sizeof(struct plat_serial8250_port) * 3);
 840        if (!pdev)
 841                return -ENOMEM;
 842
 843        uart_data = dev_get_platdata(&pdev->dev);
 844
 845        if (devices & SM501_USE_UART0) {
 846                sm501_setup_uart_data(sm, uart_data++, 0x30000);
 847                sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
 848                sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
 849                sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
 850        }
 851        if (devices & SM501_USE_UART1) {
 852                sm501_setup_uart_data(sm, uart_data++, 0x30020);
 853                sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
 854                sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
 855                sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
 856        }
 857
 858        pdev->id = PLAT8250_DEV_SM501;
 859
 860        return sm501_register_device(sm, pdev);
 861}
 862
 863static int sm501_register_display(struct sm501_devdata *sm,
 864                                  resource_size_t *mem_avail)
 865{
 866        struct platform_device *pdev;
 867
 868        pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
 869        if (!pdev)
 870                return -ENOMEM;
 871
 872        sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
 873        sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
 874        sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
 875        sm501_create_irq(sm, &pdev->resource[3]);
 876
 877        return sm501_register_device(sm, pdev);
 878}
 879
 880#ifdef CONFIG_MFD_SM501_GPIO
 881
 882static inline struct sm501_gpio_chip *to_sm501_gpio(struct gpio_chip *gc)
 883{
 884        return container_of(gc, struct sm501_gpio_chip, gpio);
 885}
 886
 887static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
 888{
 889        return container_of(gpio, struct sm501_devdata, gpio);
 890}
 891
 892static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
 893
 894{
 895        struct sm501_gpio_chip *smgpio = to_sm501_gpio(chip);
 896        unsigned long result;
 897
 898        result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
 899        result >>= offset;
 900
 901        return result & 1UL;
 902}
 903
 904static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip,
 905                                   unsigned long bit)
 906{
 907        unsigned long ctrl;
 908
 909        /* check and modify if this pin is not set as gpio. */
 910
 911        if (smc501_readl(smchip->control) & bit) {
 912                dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev,
 913                         "changing mode of gpio, bit %08lx\n", bit);
 914
 915                ctrl = smc501_readl(smchip->control);
 916                ctrl &= ~bit;
 917                smc501_writel(ctrl, smchip->control);
 918
 919                sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio));
 920        }
 921}
 922
 923static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 924
 925{
 926        struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
 927        struct sm501_gpio *smgpio = smchip->ourgpio;
 928        unsigned long bit = 1 << offset;
 929        void __iomem *regs = smchip->regbase;
 930        unsigned long save;
 931        unsigned long val;
 932
 933        dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
 934                __func__, chip, offset);
 935
 936        spin_lock_irqsave(&smgpio->lock, save);
 937
 938        val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
 939        if (value)
 940                val |= bit;
 941        smc501_writel(val, regs);
 942
 943        sm501_sync_regs(sm501_gpio_to_dev(smgpio));
 944        sm501_gpio_ensure_gpio(smchip, bit);
 945
 946        spin_unlock_irqrestore(&smgpio->lock, save);
 947}
 948
 949static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
 950{
 951        struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
 952        struct sm501_gpio *smgpio = smchip->ourgpio;
 953        void __iomem *regs = smchip->regbase;
 954        unsigned long bit = 1 << offset;
 955        unsigned long save;
 956        unsigned long ddr;
 957
 958        dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
 959                __func__, chip, offset);
 960
 961        spin_lock_irqsave(&smgpio->lock, save);
 962
 963        ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
 964        smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
 965
 966        sm501_sync_regs(sm501_gpio_to_dev(smgpio));
 967        sm501_gpio_ensure_gpio(smchip, bit);
 968
 969        spin_unlock_irqrestore(&smgpio->lock, save);
 970
 971        return 0;
 972}
 973
 974static int sm501_gpio_output(struct gpio_chip *chip,
 975                             unsigned offset, int value)
 976{
 977        struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
 978        struct sm501_gpio *smgpio = smchip->ourgpio;
 979        unsigned long bit = 1 << offset;
 980        void __iomem *regs = smchip->regbase;
 981        unsigned long save;
 982        unsigned long val;
 983        unsigned long ddr;
 984
 985        dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
 986                __func__, chip, offset, value);
 987
 988        spin_lock_irqsave(&smgpio->lock, save);
 989
 990        val = smc501_readl(regs + SM501_GPIO_DATA_LOW);
 991        if (value)
 992                val |= bit;
 993        else
 994                val &= ~bit;
 995        smc501_writel(val, regs);
 996
 997        ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
 998        smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
 999
1000        sm501_sync_regs(sm501_gpio_to_dev(smgpio));
1001        smc501_writel(val, regs + SM501_GPIO_DATA_LOW);
1002
1003        sm501_sync_regs(sm501_gpio_to_dev(smgpio));
1004        spin_unlock_irqrestore(&smgpio->lock, save);
1005
1006        return 0;
1007}
1008
1009static struct gpio_chip gpio_chip_template = {
1010        .ngpio                  = 32,
1011        .direction_input        = sm501_gpio_input,
1012        .direction_output       = sm501_gpio_output,
1013        .set                    = sm501_gpio_set,
1014        .get                    = sm501_gpio_get,
1015};
1016
1017static int sm501_gpio_register_chip(struct sm501_devdata *sm,
1018                                              struct sm501_gpio *gpio,
1019                                              struct sm501_gpio_chip *chip)
1020{
1021        struct sm501_platdata *pdata = sm->platdata;
1022        struct gpio_chip *gchip = &chip->gpio;
1023        int base = pdata->gpio_base;
1024
1025        chip->gpio = gpio_chip_template;
1026
1027        if (chip == &gpio->high) {
1028                if (base > 0)
1029                        base += 32;
1030                chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
1031                chip->control = sm->regs + SM501_GPIO63_32_CONTROL;
1032                gchip->label  = "SM501-HIGH";
1033        } else {
1034                chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
1035                chip->control = sm->regs + SM501_GPIO31_0_CONTROL;
1036                gchip->label  = "SM501-LOW";
1037        }
1038
1039        gchip->base   = base;
1040        chip->ourgpio = gpio;
1041
1042        return gpiochip_add(gchip);
1043}
1044
1045static int sm501_register_gpio(struct sm501_devdata *sm)
1046{
1047        struct sm501_gpio *gpio = &sm->gpio;
1048        resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1049        int ret;
1050        int tmp;
1051
1052        dev_dbg(sm->dev, "registering gpio block %08llx\n",
1053                (unsigned long long)iobase);
1054
1055        spin_lock_init(&gpio->lock);
1056
1057        gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
1058        if (gpio->regs_res == NULL) {
1059                dev_err(sm->dev, "gpio: failed to request region\n");
1060                return -ENXIO;
1061        }
1062
1063        gpio->regs = ioremap(iobase, 0x20);
1064        if (gpio->regs == NULL) {
1065                dev_err(sm->dev, "gpio: failed to remap registers\n");
1066                ret = -ENXIO;
1067                goto err_claimed;
1068        }
1069
1070        /* Register both our chips. */
1071
1072        ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
1073        if (ret) {
1074                dev_err(sm->dev, "failed to add low chip\n");
1075                goto err_mapped;
1076        }
1077
1078        ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
1079        if (ret) {
1080                dev_err(sm->dev, "failed to add high chip\n");
1081                goto err_low_chip;
1082        }
1083
1084        gpio->registered = 1;
1085
1086        return 0;
1087
1088 err_low_chip:
1089        tmp = gpiochip_remove(&gpio->low.gpio);
1090        if (tmp) {
1091                dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n");
1092                return ret;
1093        }
1094
1095 err_mapped:
1096        iounmap(gpio->regs);
1097
1098 err_claimed:
1099        release_resource(gpio->regs_res);
1100        kfree(gpio->regs_res);
1101
1102        return ret;
1103}
1104
1105static void sm501_gpio_remove(struct sm501_devdata *sm)
1106{
1107        struct sm501_gpio *gpio = &sm->gpio;
1108        int ret;
1109
1110        if (!sm->gpio.registered)
1111                return;
1112
1113        ret = gpiochip_remove(&gpio->low.gpio);
1114        if (ret)
1115                dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n");
1116
1117        ret = gpiochip_remove(&gpio->high.gpio);
1118        if (ret)
1119                dev_err(sm->dev, "cannot remove high chip, cannot tidy up\n");
1120
1121        iounmap(gpio->regs);
1122        release_resource(gpio->regs_res);
1123        kfree(gpio->regs_res);
1124}
1125
1126static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
1127{
1128        struct sm501_gpio *gpio = &sm->gpio;
1129        int base = (pin < 32) ? gpio->low.gpio.base : gpio->high.gpio.base;
1130
1131        return (pin % 32) + base;
1132}
1133
1134static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1135{
1136        return sm->gpio.registered;
1137}
1138#else
1139static inline int sm501_register_gpio(struct sm501_devdata *sm)
1140{
1141        return 0;
1142}
1143
1144static inline void sm501_gpio_remove(struct sm501_devdata *sm)
1145{
1146}
1147
1148static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
1149{
1150        return -1;
1151}
1152
1153static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1154{
1155        return 0;
1156}
1157#endif
1158
1159static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
1160                                            struct sm501_platdata_gpio_i2c *iic)
1161{
1162        struct i2c_gpio_platform_data *icd;
1163        struct platform_device *pdev;
1164
1165        pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
1166                                   sizeof(struct i2c_gpio_platform_data));
1167        if (!pdev)
1168                return -ENOMEM;
1169
1170        icd = dev_get_platdata(&pdev->dev);
1171
1172        /* We keep the pin_sda and pin_scl fields relative in case the
1173         * same platform data is passed to >1 SM501.
1174         */
1175
1176        icd->sda_pin = sm501_gpio_pin2nr(sm, iic->pin_sda);
1177        icd->scl_pin = sm501_gpio_pin2nr(sm, iic->pin_scl);
1178        icd->timeout = iic->timeout;
1179        icd->udelay = iic->udelay;
1180
1181        /* note, we can't use either of the pin numbers, as the i2c-gpio
1182         * driver uses the platform.id field to generate the bus number
1183         * to register with the i2c core; The i2c core doesn't have enough
1184         * entries to deal with anything we currently use.
1185        */
1186
1187        pdev->id = iic->bus_num;
1188
1189        dev_info(sm->dev, "registering i2c-%d: sda=%d (%d), scl=%d (%d)\n",
1190                 iic->bus_num,
1191                 icd->sda_pin, iic->pin_sda, icd->scl_pin, iic->pin_scl);
1192
1193        return sm501_register_device(sm, pdev);
1194}
1195
1196static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
1197                                   struct sm501_platdata *pdata)
1198{
1199        struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
1200        int index;
1201        int ret;
1202
1203        for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
1204                ret = sm501_register_gpio_i2c_instance(sm, iic);
1205                if (ret < 0)
1206                        return ret;
1207        }
1208
1209        return 0;
1210}
1211
1212/* sm501_dbg_regs
1213 *
1214 * Debug attribute to attach to parent device to show core registers
1215*/
1216
1217static ssize_t sm501_dbg_regs(struct device *dev,
1218                              struct device_attribute *attr, char *buff)
1219{
1220        struct sm501_devdata *sm = dev_get_drvdata(dev) ;
1221        unsigned int reg;
1222        char *ptr = buff;
1223        int ret;
1224
1225        for (reg = 0x00; reg < 0x70; reg += 4) {
1226                ret = sprintf(ptr, "%08x = %08x\n",
1227                              reg, smc501_readl(sm->regs + reg));
1228                ptr += ret;
1229        }
1230
1231        return ptr - buff;
1232}
1233
1234
1235static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL);
1236
1237/* sm501_init_reg
1238 *
1239 * Helper function for the init code to setup a register
1240 *
1241 * clear the bits which are set in r->mask, and then set
1242 * the bits set in r->set.
1243*/
1244
1245static inline void sm501_init_reg(struct sm501_devdata *sm,
1246                                  unsigned long reg,
1247                                  struct sm501_reg_init *r)
1248{
1249        unsigned long tmp;
1250
1251        tmp = smc501_readl(sm->regs + reg);
1252        tmp &= ~r->mask;
1253        tmp |= r->set;
1254        smc501_writel(tmp, sm->regs + reg);
1255}
1256
1257/* sm501_init_regs
1258 *
1259 * Setup core register values
1260*/
1261
1262static void sm501_init_regs(struct sm501_devdata *sm,
1263                            struct sm501_initdata *init)
1264{
1265        sm501_misc_control(sm->dev,
1266                           init->misc_control.set,
1267                           init->misc_control.mask);
1268
1269        sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
1270        sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
1271        sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
1272
1273        if (init->m1xclk) {
1274                dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
1275                sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
1276        }
1277
1278        if (init->mclk) {
1279                dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
1280                sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1281        }
1282
1283}
1284
1285/* Check the PLL sources for the M1CLK and M1XCLK
1286 *
1287 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1288 * there is a risk (see errata AB-5) that the SM501 will cease proper
1289 * function. If this happens, then it is likely the SM501 will
1290 * hang the system.
1291*/
1292
1293static int sm501_check_clocks(struct sm501_devdata *sm)
1294{
1295        unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
1296        unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
1297        unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
1298
1299        return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
1300}
1301
1302static unsigned int sm501_mem_local[] = {
1303        [0]     = 4*1024*1024,
1304        [1]     = 8*1024*1024,
1305        [2]     = 16*1024*1024,
1306        [3]     = 32*1024*1024,
1307        [4]     = 64*1024*1024,
1308        [5]     = 2*1024*1024,
1309};
1310
1311/* sm501_init_dev
1312 *
1313 * Common init code for an SM501
1314*/
1315
1316static int sm501_init_dev(struct sm501_devdata *sm)
1317{
1318        struct sm501_initdata *idata;
1319        struct sm501_platdata *pdata;
1320        resource_size_t mem_avail;
1321        unsigned long dramctrl;
1322        unsigned long devid;
1323        int ret;
1324
1325        mutex_init(&sm->clock_lock);
1326        spin_lock_init(&sm->reg_lock);
1327
1328        INIT_LIST_HEAD(&sm->devices);
1329
1330        devid = smc501_readl(sm->regs + SM501_DEVICEID);
1331
1332        if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
1333                dev_err(sm->dev, "incorrect device id %08lx\n", devid);
1334                return -EINVAL;
1335        }
1336
1337        /* disable irqs */
1338        smc501_writel(0, sm->regs + SM501_IRQ_MASK);
1339
1340        dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL);
1341        mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
1342
1343        dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1344                 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
1345
1346        sm->rev = devid & SM501_DEVICEID_REVMASK;
1347
1348        sm501_dump_gate(sm);
1349
1350        ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
1351        if (ret)
1352                dev_err(sm->dev, "failed to create debug regs file\n");
1353
1354        sm501_dump_clk(sm);
1355
1356        /* check to see if we have some device initialisation */
1357
1358        pdata = sm->platdata;
1359        idata = pdata ? pdata->init : NULL;
1360
1361        if (idata) {
1362                sm501_init_regs(sm, idata);
1363
1364                if (idata->devices & SM501_USE_USB_HOST)
1365                        sm501_register_usbhost(sm, &mem_avail);
1366                if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
1367                        sm501_register_uart(sm, idata->devices);
1368                if (idata->devices & SM501_USE_GPIO)
1369                        sm501_register_gpio(sm);
1370        }
1371
1372        if (pdata && pdata->gpio_i2c != NULL && pdata->gpio_i2c_nr > 0) {
1373                if (!sm501_gpio_isregistered(sm))
1374                        dev_err(sm->dev, "no gpio available for i2c gpio.\n");
1375                else
1376                        sm501_register_gpio_i2c(sm, pdata);
1377        }
1378
1379        ret = sm501_check_clocks(sm);
1380        if (ret) {
1381                dev_err(sm->dev, "M1X and M clocks sourced from different "
1382                                        "PLLs\n");
1383                return -EINVAL;
1384        }
1385
1386        /* always create a framebuffer */
1387        sm501_register_display(sm, &mem_avail);
1388
1389        return 0;
1390}
1391
1392static int sm501_plat_probe(struct platform_device *dev)
1393{
1394        struct sm501_devdata *sm;
1395        int ret;
1396
1397        sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1398        if (sm == NULL) {
1399                dev_err(&dev->dev, "no memory for device data\n");
1400                ret = -ENOMEM;
1401                goto err1;
1402        }
1403
1404        sm->dev = &dev->dev;
1405        sm->pdev_id = dev->id;
1406        sm->platdata = dev_get_platdata(&dev->dev);
1407
1408        ret = platform_get_irq(dev, 0);
1409        if (ret < 0) {
1410                dev_err(&dev->dev, "failed to get irq resource\n");
1411                goto err_res;
1412        }
1413        sm->irq = ret;
1414
1415        sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1416        sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1417
1418        if (sm->io_res == NULL || sm->mem_res == NULL) {
1419                dev_err(&dev->dev, "failed to get IO resource\n");
1420                ret = -ENOENT;
1421                goto err_res;
1422        }
1423
1424        sm->regs_claim = request_mem_region(sm->io_res->start,
1425                                            0x100, "sm501");
1426
1427        if (sm->regs_claim == NULL) {
1428                dev_err(&dev->dev, "cannot claim registers\n");
1429                ret = -EBUSY;
1430                goto err_res;
1431        }
1432
1433        platform_set_drvdata(dev, sm);
1434
1435        sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
1436
1437        if (sm->regs == NULL) {
1438                dev_err(&dev->dev, "cannot remap registers\n");
1439                ret = -EIO;
1440                goto err_claim;
1441        }
1442
1443        return sm501_init_dev(sm);
1444
1445 err_claim:
1446        release_resource(sm->regs_claim);
1447        kfree(sm->regs_claim);
1448 err_res:
1449        kfree(sm);
1450 err1:
1451        return ret;
1452
1453}
1454
1455#ifdef CONFIG_PM
1456
1457/* power management support */
1458
1459static void sm501_set_power(struct sm501_devdata *sm, int on)
1460{
1461        struct sm501_platdata *pd = sm->platdata;
1462
1463        if (pd == NULL)
1464                return;
1465
1466        if (pd->get_power) {
1467                if (pd->get_power(sm->dev) == on) {
1468                        dev_dbg(sm->dev, "is already %d\n", on);
1469                        return;
1470                }
1471        }
1472
1473        if (pd->set_power) {
1474                dev_dbg(sm->dev, "setting power to %d\n", on);
1475
1476                pd->set_power(sm->dev, on);
1477                sm501_mdelay(sm, 10);
1478        }
1479}
1480
1481static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1482{
1483        struct sm501_devdata *sm = platform_get_drvdata(pdev);
1484
1485        sm->in_suspend = 1;
1486        sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
1487
1488        sm501_dump_regs(sm);
1489
1490        if (sm->platdata) {
1491                if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
1492                        sm501_set_power(sm, 0);
1493        }
1494
1495        return 0;
1496}
1497
1498static int sm501_plat_resume(struct platform_device *pdev)
1499{
1500        struct sm501_devdata *sm = platform_get_drvdata(pdev);
1501
1502        sm501_set_power(sm, 1);
1503
1504        sm501_dump_regs(sm);
1505        sm501_dump_gate(sm);
1506        sm501_dump_clk(sm);
1507
1508        /* check to see if we are in the same state as when suspended */
1509
1510        if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
1511                dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
1512                smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
1513
1514                /* our suspend causes the controller state to change,
1515                 * either by something attempting setup, power loss,
1516                 * or an external reset event on power change */
1517
1518                if (sm->platdata && sm->platdata->init) {
1519                        sm501_init_regs(sm, sm->platdata->init);
1520                }
1521        }
1522
1523        /* dump our state from resume */
1524
1525        sm501_dump_regs(sm);
1526        sm501_dump_clk(sm);
1527
1528        sm->in_suspend = 0;
1529
1530        return 0;
1531}
1532#else
1533#define sm501_plat_suspend NULL
1534#define sm501_plat_resume NULL
1535#endif
1536
1537/* Initialisation data for PCI devices */
1538
1539static struct sm501_initdata sm501_pci_initdata = {
1540        .gpio_high      = {
1541                .set    = 0x3F000000,           /* 24bit panel */
1542                .mask   = 0x0,
1543        },
1544        .misc_timing    = {
1545                .set    = 0x010100,             /* SDRAM timing */
1546                .mask   = 0x1F1F00,
1547        },
1548        .misc_control   = {
1549                .set    = SM501_MISC_PNL_24BIT,
1550                .mask   = 0,
1551        },
1552
1553        .devices        = SM501_USE_ALL,
1554
1555        /* Errata AB-3 says that 72MHz is the fastest available
1556         * for 33MHZ PCI with proper bus-mastering operation */
1557
1558        .mclk           = 72 * MHZ,
1559        .m1xclk         = 144 * MHZ,
1560};
1561
1562static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1563        .flags          = (SM501FB_FLAG_USE_INIT_MODE |
1564                           SM501FB_FLAG_USE_HWCURSOR |
1565                           SM501FB_FLAG_USE_HWACCEL |
1566                           SM501FB_FLAG_DISABLE_AT_EXIT),
1567};
1568
1569static struct sm501_platdata_fb sm501_fb_pdata = {
1570        .fb_route       = SM501_FB_OWN,
1571        .fb_crt         = &sm501_pdata_fbsub,
1572        .fb_pnl         = &sm501_pdata_fbsub,
1573};
1574
1575static struct sm501_platdata sm501_pci_platdata = {
1576        .init           = &sm501_pci_initdata,
1577        .fb             = &sm501_fb_pdata,
1578        .gpio_base      = -1,
1579};
1580
1581static int sm501_pci_probe(struct pci_dev *dev,
1582                                     const struct pci_device_id *id)
1583{
1584        struct sm501_devdata *sm;
1585        int err;
1586
1587        sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1588        if (sm == NULL) {
1589                dev_err(&dev->dev, "no memory for device data\n");
1590                err = -ENOMEM;
1591                goto err1;
1592        }
1593
1594        /* set a default set of platform data */
1595        dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1596
1597        /* set a hopefully unique id for our child platform devices */
1598        sm->pdev_id = 32 + dev->devfn;
1599
1600        pci_set_drvdata(dev, sm);
1601
1602        err = pci_enable_device(dev);
1603        if (err) {
1604                dev_err(&dev->dev, "cannot enable device\n");
1605                goto err2;
1606        }
1607
1608        sm->dev = &dev->dev;
1609        sm->irq = dev->irq;
1610
1611#ifdef __BIG_ENDIAN
1612        /* if the system is big-endian, we most probably have a
1613         * translation in the IO layer making the PCI bus little endian
1614         * so make the framebuffer swapped pixels */
1615
1616        sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1617#endif
1618
1619        /* check our resources */
1620
1621        if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1622                dev_err(&dev->dev, "region #0 is not memory?\n");
1623                err = -EINVAL;
1624                goto err3;
1625        }
1626
1627        if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1628                dev_err(&dev->dev, "region #1 is not memory?\n");
1629                err = -EINVAL;
1630                goto err3;
1631        }
1632
1633        /* make our resources ready for sharing */
1634
1635        sm->io_res = &dev->resource[1];
1636        sm->mem_res = &dev->resource[0];
1637
1638        sm->regs_claim = request_mem_region(sm->io_res->start,
1639                                            0x100, "sm501");
1640        if (sm->regs_claim == NULL) {
1641                dev_err(&dev->dev, "cannot claim registers\n");
1642                err= -EBUSY;
1643                goto err3;
1644        }
1645
1646        sm->regs = pci_ioremap_bar(dev, 1);
1647
1648        if (sm->regs == NULL) {
1649                dev_err(&dev->dev, "cannot remap registers\n");
1650                err = -EIO;
1651                goto err4;
1652        }
1653
1654        sm501_init_dev(sm);
1655        return 0;
1656
1657 err4:
1658        release_resource(sm->regs_claim);
1659        kfree(sm->regs_claim);
1660 err3:
1661        pci_disable_device(dev);
1662 err2:
1663        pci_set_drvdata(dev, NULL);
1664        kfree(sm);
1665 err1:
1666        return err;
1667}
1668
1669static void sm501_remove_sub(struct sm501_devdata *sm,
1670                             struct sm501_device *smdev)
1671{
1672        list_del(&smdev->list);
1673        platform_device_unregister(&smdev->pdev);
1674}
1675
1676static void sm501_dev_remove(struct sm501_devdata *sm)
1677{
1678        struct sm501_device *smdev, *tmp;
1679
1680        list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1681                sm501_remove_sub(sm, smdev);
1682
1683        device_remove_file(sm->dev, &dev_attr_dbg_regs);
1684
1685        sm501_gpio_remove(sm);
1686}
1687
1688static void sm501_pci_remove(struct pci_dev *dev)
1689{
1690        struct sm501_devdata *sm = pci_get_drvdata(dev);
1691
1692        sm501_dev_remove(sm);
1693        iounmap(sm->regs);
1694
1695        release_resource(sm->regs_claim);
1696        kfree(sm->regs_claim);
1697
1698        pci_set_drvdata(dev, NULL);
1699        pci_disable_device(dev);
1700}
1701
1702static int sm501_plat_remove(struct platform_device *dev)
1703{
1704        struct sm501_devdata *sm = platform_get_drvdata(dev);
1705
1706        sm501_dev_remove(sm);
1707        iounmap(sm->regs);
1708
1709        release_resource(sm->regs_claim);
1710        kfree(sm->regs_claim);
1711
1712        return 0;
1713}
1714
1715static DEFINE_PCI_DEVICE_TABLE(sm501_pci_tbl) = {
1716        { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1717        { 0, },
1718};
1719
1720MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1721
1722static struct pci_driver sm501_pci_driver = {
1723        .name           = "sm501",
1724        .id_table       = sm501_pci_tbl,
1725        .probe          = sm501_pci_probe,
1726        .remove         = sm501_pci_remove,
1727};
1728
1729MODULE_ALIAS("platform:sm501");
1730
1731static struct of_device_id of_sm501_match_tbl[] = {
1732        { .compatible = "smi,sm501", },
1733        { /* end */ }
1734};
1735
1736static struct platform_driver sm501_plat_driver = {
1737        .driver         = {
1738                .name   = "sm501",
1739                .owner  = THIS_MODULE,
1740                .of_match_table = of_sm501_match_tbl,
1741        },
1742        .probe          = sm501_plat_probe,
1743        .remove         = sm501_plat_remove,
1744        .suspend        = sm501_plat_suspend,
1745        .resume         = sm501_plat_resume,
1746};
1747
1748static int __init sm501_base_init(void)
1749{
1750        platform_driver_register(&sm501_plat_driver);
1751        return pci_register_driver(&sm501_pci_driver);
1752}
1753
1754static void __exit sm501_base_exit(void)
1755{
1756        platform_driver_unregister(&sm501_plat_driver);
1757        pci_unregister_driver(&sm501_pci_driver);
1758}
1759
1760module_init(sm501_base_init);
1761module_exit(sm501_base_exit);
1762
1763MODULE_DESCRIPTION("SM501 Core Driver");
1764MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1765MODULE_LICENSE("GPL v2");
1766
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