linux/drivers/mfd/max8998-irq.c
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   1/*
   2 * Interrupt controller support for MAX8998
   3 *
   4 * Copyright (C) 2010 Samsung Electronics Co.Ltd
   5 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
   6 *
   7 * This program is free software; you can redistribute  it and/or modify it
   8 * under  the terms of  the GNU General  Public License as published by the
   9 * Free Software Foundation;  either version 2 of the  License, or (at your
  10 * option) any later version.
  11 *
  12 */
  13
  14#include <linux/device.h>
  15#include <linux/interrupt.h>
  16#include <linux/irq.h>
  17#include <linux/irqdomain.h>
  18#include <linux/mfd/max8998-private.h>
  19
  20struct max8998_irq_data {
  21        int reg;
  22        int mask;
  23};
  24
  25static struct max8998_irq_data max8998_irqs[] = {
  26        [MAX8998_IRQ_DCINF] = {
  27                .reg = 1,
  28                .mask = MAX8998_IRQ_DCINF_MASK,
  29        },
  30        [MAX8998_IRQ_DCINR] = {
  31                .reg = 1,
  32                .mask = MAX8998_IRQ_DCINR_MASK,
  33        },
  34        [MAX8998_IRQ_JIGF] = {
  35                .reg = 1,
  36                .mask = MAX8998_IRQ_JIGF_MASK,
  37        },
  38        [MAX8998_IRQ_JIGR] = {
  39                .reg = 1,
  40                .mask = MAX8998_IRQ_JIGR_MASK,
  41        },
  42        [MAX8998_IRQ_PWRONF] = {
  43                .reg = 1,
  44                .mask = MAX8998_IRQ_PWRONF_MASK,
  45        },
  46        [MAX8998_IRQ_PWRONR] = {
  47                .reg = 1,
  48                .mask = MAX8998_IRQ_PWRONR_MASK,
  49        },
  50        [MAX8998_IRQ_WTSREVNT] = {
  51                .reg = 2,
  52                .mask = MAX8998_IRQ_WTSREVNT_MASK,
  53        },
  54        [MAX8998_IRQ_SMPLEVNT] = {
  55                .reg = 2,
  56                .mask = MAX8998_IRQ_SMPLEVNT_MASK,
  57        },
  58        [MAX8998_IRQ_ALARM1] = {
  59                .reg = 2,
  60                .mask = MAX8998_IRQ_ALARM1_MASK,
  61        },
  62        [MAX8998_IRQ_ALARM0] = {
  63                .reg = 2,
  64                .mask = MAX8998_IRQ_ALARM0_MASK,
  65        },
  66        [MAX8998_IRQ_ONKEY1S] = {
  67                .reg = 3,
  68                .mask = MAX8998_IRQ_ONKEY1S_MASK,
  69        },
  70        [MAX8998_IRQ_TOPOFFR] = {
  71                .reg = 3,
  72                .mask = MAX8998_IRQ_TOPOFFR_MASK,
  73        },
  74        [MAX8998_IRQ_DCINOVPR] = {
  75                .reg = 3,
  76                .mask = MAX8998_IRQ_DCINOVPR_MASK,
  77        },
  78        [MAX8998_IRQ_CHGRSTF] = {
  79                .reg = 3,
  80                .mask = MAX8998_IRQ_CHGRSTF_MASK,
  81        },
  82        [MAX8998_IRQ_DONER] = {
  83                .reg = 3,
  84                .mask = MAX8998_IRQ_DONER_MASK,
  85        },
  86        [MAX8998_IRQ_CHGFAULT] = {
  87                .reg = 3,
  88                .mask = MAX8998_IRQ_CHGFAULT_MASK,
  89        },
  90        [MAX8998_IRQ_LOBAT1] = {
  91                .reg = 4,
  92                .mask = MAX8998_IRQ_LOBAT1_MASK,
  93        },
  94        [MAX8998_IRQ_LOBAT2] = {
  95                .reg = 4,
  96                .mask = MAX8998_IRQ_LOBAT2_MASK,
  97        },
  98};
  99
 100static inline struct max8998_irq_data *
 101irq_to_max8998_irq(struct max8998_dev *max8998, int irq)
 102{
 103        struct irq_data *data = irq_get_irq_data(irq);
 104        return &max8998_irqs[data->hwirq];
 105}
 106
 107static void max8998_irq_lock(struct irq_data *data)
 108{
 109        struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
 110
 111        mutex_lock(&max8998->irqlock);
 112}
 113
 114static void max8998_irq_sync_unlock(struct irq_data *data)
 115{
 116        struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
 117        int i;
 118
 119        for (i = 0; i < ARRAY_SIZE(max8998->irq_masks_cur); i++) {
 120                /*
 121                 * If there's been a change in the mask write it back
 122                 * to the hardware.
 123                 */
 124                if (max8998->irq_masks_cur[i] != max8998->irq_masks_cache[i]) {
 125                        max8998->irq_masks_cache[i] = max8998->irq_masks_cur[i];
 126                        max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i,
 127                                        max8998->irq_masks_cur[i]);
 128                }
 129        }
 130
 131        mutex_unlock(&max8998->irqlock);
 132}
 133
 134static void max8998_irq_unmask(struct irq_data *data)
 135{
 136        struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
 137        struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998,
 138                                                               data->irq);
 139
 140        max8998->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
 141}
 142
 143static void max8998_irq_mask(struct irq_data *data)
 144{
 145        struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
 146        struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998,
 147                                                               data->irq);
 148
 149        max8998->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
 150}
 151
 152static struct irq_chip max8998_irq_chip = {
 153        .name = "max8998",
 154        .irq_bus_lock = max8998_irq_lock,
 155        .irq_bus_sync_unlock = max8998_irq_sync_unlock,
 156        .irq_mask = max8998_irq_mask,
 157        .irq_unmask = max8998_irq_unmask,
 158};
 159
 160static irqreturn_t max8998_irq_thread(int irq, void *data)
 161{
 162        struct max8998_dev *max8998 = data;
 163        u8 irq_reg[MAX8998_NUM_IRQ_REGS];
 164        int ret;
 165        int i;
 166
 167        ret = max8998_bulk_read(max8998->i2c, MAX8998_REG_IRQ1,
 168                        MAX8998_NUM_IRQ_REGS, irq_reg);
 169        if (ret < 0) {
 170                dev_err(max8998->dev, "Failed to read interrupt register: %d\n",
 171                                ret);
 172                return IRQ_NONE;
 173        }
 174
 175        /* Apply masking */
 176        for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++)
 177                irq_reg[i] &= ~max8998->irq_masks_cur[i];
 178
 179        /* Report */
 180        for (i = 0; i < MAX8998_IRQ_NR; i++) {
 181                if (irq_reg[max8998_irqs[i].reg - 1] & max8998_irqs[i].mask) {
 182                        irq = irq_find_mapping(max8998->irq_domain, i);
 183                        if (WARN_ON(!irq)) {
 184                                disable_irq_nosync(max8998->irq);
 185                                return IRQ_NONE;
 186                        }
 187                        handle_nested_irq(irq);
 188                }
 189        }
 190
 191        return IRQ_HANDLED;
 192}
 193
 194int max8998_irq_resume(struct max8998_dev *max8998)
 195{
 196        if (max8998->irq && max8998->irq_domain)
 197                max8998_irq_thread(max8998->irq, max8998);
 198        return 0;
 199}
 200
 201static int max8998_irq_domain_map(struct irq_domain *d, unsigned int irq,
 202                                        irq_hw_number_t hw)
 203{
 204        struct max8997_dev *max8998 = d->host_data;
 205
 206        irq_set_chip_data(irq, max8998);
 207        irq_set_chip_and_handler(irq, &max8998_irq_chip, handle_edge_irq);
 208        irq_set_nested_thread(irq, 1);
 209#ifdef CONFIG_ARM
 210        set_irq_flags(irq, IRQF_VALID);
 211#else
 212        irq_set_noprobe(irq);
 213#endif
 214        return 0;
 215}
 216
 217static struct irq_domain_ops max8998_irq_domain_ops = {
 218        .map = max8998_irq_domain_map,
 219};
 220
 221int max8998_irq_init(struct max8998_dev *max8998)
 222{
 223        int i;
 224        int ret;
 225        struct irq_domain *domain;
 226
 227        if (!max8998->irq) {
 228                dev_warn(max8998->dev,
 229                         "No interrupt specified, no interrupts\n");
 230                return 0;
 231        }
 232
 233        mutex_init(&max8998->irqlock);
 234
 235        /* Mask the individual interrupt sources */
 236        for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++) {
 237                max8998->irq_masks_cur[i] = 0xff;
 238                max8998->irq_masks_cache[i] = 0xff;
 239                max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i, 0xff);
 240        }
 241
 242        max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM1, 0xff);
 243        max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM2, 0xff);
 244
 245        domain = irq_domain_add_simple(NULL, MAX8998_IRQ_NR,
 246                        max8998->irq_base, &max8998_irq_domain_ops, max8998);
 247        if (!domain) {
 248                dev_err(max8998->dev, "could not create irq domain\n");
 249                return -ENODEV;
 250        }
 251        max8998->irq_domain = domain;
 252
 253        ret = request_threaded_irq(max8998->irq, NULL, max8998_irq_thread,
 254                                   IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
 255                                   "max8998-irq", max8998);
 256        if (ret) {
 257                dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
 258                        max8998->irq, ret);
 259                return ret;
 260        }
 261
 262        if (!max8998->ono)
 263                return 0;
 264
 265        ret = request_threaded_irq(max8998->ono, NULL, max8998_irq_thread,
 266                                   IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
 267                                   IRQF_ONESHOT, "max8998-ono", max8998);
 268        if (ret)
 269                dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
 270                        max8998->ono, ret);
 271
 272        return 0;
 273}
 274
 275void max8998_irq_exit(struct max8998_dev *max8998)
 276{
 277        if (max8998->ono)
 278                free_irq(max8998->ono, max8998);
 279
 280        if (max8998->irq)
 281                free_irq(max8998->irq, max8998);
 282}
 283
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