linux/drivers/irqchip/irq-nvic.c
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   1/*
   2 * drivers/irq/irq-nvic.c
   3 *
   4 * Copyright (C) 2008 ARM Limited, All Rights Reserved.
   5 * Copyright (C) 2013 Pengutronix
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 *
  11 * Support for the Nested Vectored Interrupt Controller found on the
  12 * ARMv7-M CPUs (Cortex-M3/M4)
  13 */
  14#define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
  15
  16#include <linux/init.h>
  17#include <linux/kernel.h>
  18#include <linux/slab.h>
  19#include <linux/err.h>
  20#include <linux/io.h>
  21#include <linux/of.h>
  22#include <linux/of_address.h>
  23#include <linux/irq.h>
  24#include <linux/irqdomain.h>
  25
  26#include <asm/v7m.h>
  27#include <asm/exception.h>
  28
  29#include "irqchip.h"
  30
  31#define NVIC_ISER               0x000
  32#define NVIC_ICER               0x080
  33#define NVIC_IPR                0x300
  34
  35#define NVIC_MAX_BANKS          16
  36/*
  37 * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
  38 * 16 irqs.
  39 */
  40#define NVIC_MAX_IRQ            ((NVIC_MAX_BANKS - 1) * 32 + 16)
  41
  42static struct irq_domain *nvic_irq_domain;
  43
  44asmlinkage void __exception_irq_entry
  45nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs)
  46{
  47        unsigned int irq = irq_linear_revmap(nvic_irq_domain, hwirq);
  48
  49        handle_IRQ(irq, regs);
  50}
  51
  52static void nvic_eoi(struct irq_data *d)
  53{
  54        /*
  55         * This is a no-op as end of interrupt is signaled by the exception
  56         * return sequence.
  57         */
  58}
  59
  60static int __init nvic_of_init(struct device_node *node,
  61                               struct device_node *parent)
  62{
  63        unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  64        unsigned int irqs, i, ret, numbanks;
  65        void __iomem *nvic_base;
  66
  67        numbanks = (readl_relaxed(V7M_SCS_ICTR) &
  68                    V7M_SCS_ICTR_INTLINESNUM_MASK) + 1;
  69
  70        nvic_base = of_iomap(node, 0);
  71        if (!nvic_base) {
  72                pr_warn("unable to map nvic registers\n");
  73                return -ENOMEM;
  74        }
  75
  76        irqs = numbanks * 32;
  77        if (irqs > NVIC_MAX_IRQ)
  78                irqs = NVIC_MAX_IRQ;
  79
  80        nvic_irq_domain =
  81                irq_domain_add_linear(node, irqs, &irq_generic_chip_ops, NULL);
  82        if (!nvic_irq_domain) {
  83                pr_warn("Failed to allocate irq domain\n");
  84                return -ENOMEM;
  85        }
  86
  87        ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, 1,
  88                                             "nvic_irq", handle_fasteoi_irq,
  89                                             clr, 0, IRQ_GC_INIT_MASK_CACHE);
  90        if (ret) {
  91                pr_warn("Failed to allocate irq chips\n");
  92                irq_domain_remove(nvic_irq_domain);
  93                return ret;
  94        }
  95
  96        for (i = 0; i < numbanks; ++i) {
  97                struct irq_chip_generic *gc;
  98
  99                gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i);
 100                gc->reg_base = nvic_base + 4 * i;
 101                gc->chip_types[0].regs.enable = NVIC_ISER;
 102                gc->chip_types[0].regs.disable = NVIC_ICER;
 103                gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
 104                gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
 105                gc->chip_types[0].chip.irq_eoi = nvic_eoi;
 106
 107                /* disable interrupts */
 108                writel_relaxed(~0, gc->reg_base + NVIC_ICER);
 109        }
 110
 111        /* Set priority on all interrupts */
 112        for (i = 0; i < irqs; i += 4)
 113                writel_relaxed(0, nvic_base + NVIC_IPR + i);
 114
 115        return 0;
 116}
 117IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);
 118
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