linux/drivers/ide/aec62xx.c
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Sarch" /span> honclick"retoptifajaxspef=s();> h h<1/f> span class="lcommen=">/*/span> < ref=".rivers/ide/aec62xx.c"#L2 mid"vL2 mlass="lxine mnam="vL2 > h<2/f> span class="lcommen="> * Copyight. (C) 1999-2002 h < ref=".rivers/ide/aec62xx.c"#L3 mid"vL3 mlass="lxine mnam="vL3 > h<3/f> span class="lcommen="> * Copyight. (C) 2007 MontaVitat Software, Inc. <source@mvitat.comgt;"/span> < ref=".rivers/ide/aec62xx.c"#L4 mid"vL4 mlass="lxine mnam="vL4 > h<4/f> span class="lcommen="> */span> < ref=".rivers/ide/aec62xx.c"#L5 mid"vL5 mlass="lxine mnam="vL5 > h<5/f> span class="lcommen="> *//span> < ref=".rivers/ide/aec62xx.c"#L6 mid"vL6 mlass="lxine mnam="vL6 > h<6/f> < ref=".rivers/ide/aec62xx.c"#L7 mid"vL7 mlass="lxine mnam="vL7 > h<7/f> #include << ref=".includelinux+/module.h mlass="lfef=">inux+/module.h/f> gt;" < ref=".rivers/ide/aec62xx.c"#L8 mid"vL8 mlass="lxine mnam="vL8 > h<8/f> #include << ref=".includelinux+/typ=s.h mlass="lfef=">inux+/typ=s.h/f> gt;" < ref=".rivers/ide/aec62xx.c"#L9 mid"vL9 mlass="lxine mnam="vL9 > h<9/f> #include << ref=".includelinux+/pci.h mlass="lfef=">inux+/pci.h/f> gt;" < ref=".rivers/ide/aec62xx.c"#L10 mid"vL10 mlass="lxine mnam="vL10 > h0 #include << ref=".includelinux+/de/.h mlass="lfef=">inux+/de/.h/f> gt;" < ref=".rivers/ide/aec62xx.c"#L11 mid"vL11 mlass="lxine mnam="vL11 > h11/o> #include << ref=".includelinux+/dnit.h mlass="lfef=">inux+/dnit.h/f> gt;" < ref=".rivers/ide/aec62xx.c"#L12 mid"vL12 mlass="lxine mnam="vL12 > h12/f> < ref=".rivers/ide/aec62xx.c"#L13 mid"vL13 mlass="lxine mnam="vL13 > h13/o> #include << ref=".+ambig=includelasm-alpha/io.h|includelasm-arm/io.h|includelasm-avr32/io.h|includelasm-blackfin/io.h|includelasm-cris/io.h|includelasm-frv/io.h|includelasm-geneivc/io.h|includelasm-h8300/io.h|includelasm-i386/io.h|includelasm-ia64/io.h|includelasm-m32r/io.h|includelasm-m68k/io.h|includelasm-m68knommu/io.h|includelasm-mips/io.h|includelasm-mips64/io.h|includelasm-parisc/io.h|includelasm-powerpc/io.h|includelasm-ppc/io.h|includelasm-s390/io.h|includelasm-sh/io.h|includelasm-sh64/io.h|includelasm-panrc/io.h|includelasm-sanrc64/io.h|includelasm-um/io.h|includelasm-v850/io.h|includelasm-x86/io.h|includelasm-x86_64/io.h|includelasm-xtensa/io.h mlass="lflt=">asm/io.h/f> gt;" < ref=".rivers/ide/aec62xx.c"#L14 mid"vL14 mlass="lxine mnam="vL14 > h14/f> < ref=".rivers/ide/aec62xx.c"#L15 mid"vL15 mlass="lxine mnam="vL15 > h15/f> #defineDRV_NAME/f> span class="lstring">"ac62xx."/span> < ref=".rivers/ide/aec62xx.c"#L16 mid"vL16 mlass="lxine mnam="vL16 > h16/f> < ref=".rivers/ide/aec62xx.c"#L17 mid"vL17 mlass="lxine mnam="vL17 > h17/f> structchipset_bus_clock_lita_en=ry/f> { < ref=".rivers/ide/aec62xx.c"#L18 mid"vL18 mlass="lxine mnam="vL18 > h18/f> a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=xfe_sepeed"class="leef=">xfe_sepeed/f> " < ref=".rivers/ide/aec62xx.c"#L19 mid"vL19 mlass="lxine mnam="vL19 > h19/f> a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=chipset_settings"class="leef=">chipset_settings/f> " < ref=".rivers/ide/aec62xx.c"#L20 mid"vL20 mlass="lxine mnam="vL20 > h20/f> a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=ultra_settings"class="leef=">ultra_settings/f> " < ref=".rivers/ide/aec62xx.c"#L21 mid"vL21 mlass="lxine mnam="vL21 > h21/o> }" < ref=".rivers/ide/aec62xx.c"#L22 mid"vL22 mlass="lxine mnam="vL22 > h22/f> < ref=".rivers/ide/aec62xx.c"#L23 mid"vL23 mlass="lxine mnam="vL23 > h23/f> sttic/ const structchipset_bus_clock_lita_en=ry/f> a ref=".+code=ec62xxx_33_base"class="leef=">ec62xxx_33_base/f> [] = { < ref=".rivers/ide/aec62xx.c"#L24 mid"vL24 mlass="lxine mnam="vL24 > h24/f> { a ref=".+code=XFER_UDMA_6"class="leef=">XFER_UDMA_6/f> , 0x31, 0x07 }, < ref=".rivers/ide/aec62xx.c"#L25 mid"vL25 mlass="lxine mnam="vL25 > h25/f> { a ref=".+code=XFER_UDMA_5"class="leef=">XFER_UDMA_5/f> , 0x31, 0x06 }, < ref=".rivers/ide/aec62xx.c"#L26 mid"vL26 mlass="lxine mnam="vL26 > h26/f> { a ref=".+code=XFER_UDMA_4"class="leef=">XFER_UDMA_4/f> , 0x31, 0x05 }, < ref=".rivers/ide/aec62xx.c"#L27 mid"vL27 mlass="lxine mnam="vL27 > h27/f> { a ref=".+code=XFER_UDMA_3"class="leef=">XFER_UDMA_3/f> , 0x31, 0x04 }, < ref=".rivers/ide/aec62xx.c"#L28 mid"vL28 mlass="lxine mnam="vL28 > h28/f> { a ref=".+code=XFER_UDMA_2"class="leef=">XFER_UDMA_2/f> , 0x31, 0x03 }, < ref=".rivers/ide/aec62xx.c"#L29 mid"vL29 mlass="lxine mnam="vL29 > h29/f> { a ref=".+code=XFER_UDMA_1"class="leef=">XFER_UDMA_1/f> , 0x31, 0x02 }, < ref=".rivers/ide/aec62xx.c"#L30 mid"vL30 mlass="lxine mnam="vL30 > h30/f> { a ref=".+code=XFER_UDMA_0"class="leef=">XFER_UDMA_0/f> , 0x31, 0x01 }, < ref=".rivers/ide/aec62xx.c"#L31 mid"vL31 mlass="lxine mnam="vL31 > h31/f> < ref=".rivers/ide/aec62xx.c"#L32 mid"vL32 mlass="lxine mnam="vL32 > h32/f> { a ref=".+code=XFER_MW_DMA_2"class="leef=">XFER_MW_DMA_2/f> , 0x31, 0x00 }, < ref=".rivers/ide/aec62xx.c"#L33 mid"vL33 mlass="lxine mnam="vL33 > h33/f> { a ref=".+code=XFER_MW_DMA_1"class="leef=">XFER_MW_DMA_1/f> , 0x31, 0x00 }, < ref=".rivers/ide/aec62xx.c"#L34 mid"vL34 mlass="lxine mnam="vL34 > h34/f> { a ref=".+code=XFER_MW_DMA_0"class="leef=">XFER_MW_DMA_0/f> , 0x0a, 0x00 }, < ref=".rivers/ide/aec62xx.c"#L35 mid"vL35 mlass="lxine mnam="vL35 > h35/f> { a ref=".+code=XFER_PIO_4"class="leef=">XFER_PIO_4/f> , 0x31, 0x00 }, < ref=".rivers/ide/aec62xx.c"#L36 mid"vL36 mlass="lxine mnam="vL36 > h36/f> { a ref=".+code=XFER_PIO_3"class="leef=">XFER_PIO_3/f> , 0x33, 0x00 }, < ref=".rivers/ide/aec62xx.c"#L37 mid"vL37 mlass="lxine mnam="vL37 > h37/f> { a ref=".+code=XFER_PIO_2"class="leef=">XFER_PIO_2/f> , 0x08, 0x00 }, < ref=".rivers/ide/aec62xx.c"#L38 mid"vL38 mlass="lxine mnam="vL38 > h38/f> { a ref=".+code=XFER_PIO_1"class="leef=">XFER_PIO_1/f> , 0x0a, 0x00 }, < ref=".rivers/ide/aec62xx.c"#L39 mid"vL39 mlass="lxine mnam="vL39 > h39/f> { a ref=".+code=XFER_PIO_0"class="leef=">XFER_PIO_0/f> , 0x00, 0x00 }, < ref=".rivers/ide/aec62xx.c"#L40 mid"vL40 mlass="lxine mnam="vL40 > h40/f> { 0, 0x00, 0x00 } < ref=".rivers/ide/aec62xx.c"#L41 mid"vL41 mlass="lxine mnam="vL41 > h41/o> }" < ref=".rivers/ide/aec62xx.c"#L42 mid"vL42 mlass="lxine mnam="vL42 > h42/f> < ref=".rivers/ide/aec62xx.c"#L43 mid"vL43 mlass="lxine mnam="vL43 > h43/f> sttic/ const structchipset_bus_clock_lita_en=ry/f> a ref=".+code=ec62xxx_34_base"class="leef=">ec62xxx_34_base/f> [] = { < ref=".rivers/ide/aec62xx.c"#L44 mid"vL44 mlass="lxine mnam="vL44 > h44/f> { a ref=".+code=XFER_UDMA_6"class="leef=">XFER_UDMA_6/f> , 0x41, 0x06 }, < ref=".rivers/ide/aec62xx.c"#L45 mid"vL45 mlass="lxine mnam="vL45 > h45/f> { a ref=".+code=XFER_UDMA_5"class="leef=">XFER_UDMA_5/f> , 0x41, 0x05 }, < ref=".rivers/ide/aec62xx.c"#L46 mid"vL46 mlass="lxine mnam="vL46 > h46/f> { a ref=".+code=XFER_UDMA_4"class="leef=">XFER_UDMA_4/f> , 0x41, 0x04 }, < ref=".rivers/ide/aec62xx.c"#L47 mid"vL47 mlass="lxine mnam="vL47 > h47/f> { a ref=".+code=XFER_UDMA_3"class="leef=">XFER_UDMA_3/f> , 0x41, 0x03 }, < ref=".rivers/ide/aec62xx.c"#L48 mid"vL48 mlass="lxine mnam="vL48 > h48/f> { a ref=".+code=XFER_UDMA_2"class="leef=">XFER_UDMA_2/f> , 0x41, 0x02 }, < ref=".rivers/ide/aec62xx.c"#L49 mid"vL49 mlass="lxine mnam="vL49 > h49/f> { a ref=".+code=XFER_UDMA_1"class="leef=">XFER_UDMA_1/f> , 0x41, 0x01 }, < ref=".rivers/ide/aec62xx.c"#L50 mid"vL50 mlass="lxine mnam="vL50 > h50/f> { a ref=".+code=XFER_UDMA_0"class="leef=">XFER_UDMA_0/f> , 0x41, 0x01 }, < ref=".rivers/ide/aec62xx.c"#L51 mid"vL51 mlass="lxine mnam="vL51 > h51/f> < ref=".rivers/ide/aec62xx.c"#L52 mid"vL52 mlass="lxine mnam="vL52 > h52/f> { a ref=".+code=XFER_MW_DMA_2"class="leef=">XFER_MW_DMA_2/f> , 0x41, 0x00 }, < ref=".rivers/ide/aec62xx.c"#L53 mid"vL53 mlass="lxine mnam="vL53 > h53/f> { a ref=".+code=XFER_MW_DMA_1"class="leef=">XFER_MW_DMA_1/f> , 0x42, 0x00 }, < ref=".rivers/ide/aec62xx.c"#L54 mid"vL54 mlass="lxine mnam="vL54 > h54/f> { a ref=".+code=XFER_MW_DMA_0"class="leef=">XFER_MW_DMA_0/f> , 0x7a, 0x00 }, < ref=".rivers/ide/aec62xx.c"#L55 mid"vL55 mlass="lxine mnam="vL55 > h55/f> { a ref=".+code=XFER_PIO_4"class="leef=">XFER_PIO_4/f> , 0x41, 0x00 }, < ref=".rivers/ide/aec62xx.c"#L56 mid"vL56 mlass="lxine mnam="vL56 > h56/f> { a ref=".+code=XFER_PIO_3"class="leef=">XFER_PIO_3/f> , 0x43, 0x00 }, < ref=".rivers/ide/aec62xx.c"#L57 mid"vL57 mlass="lxine mnam="vL57 > h57/f> { a ref=".+code=XFER_PIO_2"class="leef=">XFER_PIO_2/f> , 0x78, 0x00 }, < ref=".rivers/ide/aec62xx.c"#L58 mid"vL58 mlass="lxine mnam="vL58 > h58/f> { a ref=".+code=XFER_PIO_1"class="leef=">XFER_PIO_1/f> , 0x7a, 0x00 }, < ref=".rivers/ide/aec62xx.c"#L59 mid"vL59 mlass="lxine mnam="vL59 > h59/f> { a ref=".+code=XFER_PIO_0"class="leef=">XFER_PIO_0/f> , 0x70, 0x00 }, < ref=".rivers/ide/aec62xx.c"#L60 mid"vL60 mlass="lxine mnam="vL60 > h60/f> { 0, 0x00, 0x00 } < ref=".rivers/ide/aec62xx.c"#L61 mid"vL61 mlass="lxine mnam="vL61 > h61/o> }" < ref=".rivers/ide/aec62xx.c"#L62 mid"vL62 mlass="lxine mnam="vL62 > h62/f> < ref=".rivers/ide/aec62xx.c"#L63 mid"vL63 mlass="lxine mnam="vL63 > h63/f> span class="lcommen=">/*/span> < ref=".rivers/ide/aec62xx.c"#L64 mid"vL64 mlass="lxine mnam="vL64 > h64/f> span class="lcommen="> * TO DO:actiove tuning and corretion= of cards without a bios./span> < ref=".rivers/ide/aec62xx.c"#L65 mid"vL65 mlass="lxine mnam="vL65 > h65/f> span class="lcommen="> *//span> < ref=".rivers/ide/aec62xx.c"#L66 mid"vL66 mlass="lxine mnam="vL66 > h66/f> sttic/ a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=pci_bus_clock_lita"class="leef=">pci_bus_clock_lita/f> (a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=epeed"class="leef=">epeed/f> , structchipset_bus_clock_lita_en=ry/f> *chipset_table/f> ) < ref=".rivers/ide/aec62xx.c"#L67 mid"vL67 mlass="lxine mnam="vL67 > h67/f> { < ref=".rivers/ide/aec62xx.c"#L68 mid"vL68 mlass="lxine mnam="vL68 > h68/f> for ( ;chipset_table/f> -gt;"/ ref=".+code=xfe_sepeed"class="leef=">xfe_sepeed/f> ;chipset_table/f> ++) < ref=".rivers/ide/aec62xx.c"#L69 mid"vL69 mlass="lxine mnam="vL69 > h69/f> if (a ref=".+code=chipset_table"class="leef=">chipset_table/f> -gt;"/ ref=".+code=xfe_sepeed"class="leef=">xfe_sepeed/f> == a ref=".+code=epeed"class="leef=">epeed/f> ) { < ref=".rivers/ide/aec62xx.c"#L70 mid"vL70 mlass="lxine mnam="vL70 > h70/f> etoptifa ref=".+code=chipset_table"class="leef=">chipset_table/f> -gt;"/ ref=".+code=chipset_settings"class="leef=">chipset_settings/f> " < ref=".rivers/ide/aec62xx.c"#L71 mid"vL71 mlass="lxine mnam="vL71 > h71/f> } < ref=".rivers/ide/aec62xx.c"#L72 mid"vL72 mlass="lxine mnam="vL72 > h72/f> etoptifa ref=".+code=chipset_table"class="leef=">chipset_table/f> -gt;"/ ref=".+code=chipset_settings"class="leef=">chipset_settings/f> " < ref=".rivers/ide/aec62xx.c"#L73 mid"vL73 mlass="lxine mnam="vL73 > h73/f> } < ref=".rivers/ide/aec62xx.c"#L74 mid"vL74 mlass="lxine mnam="vL74 > h74/f> < ref=".rivers/ide/aec62xx.c"#L75 mid"vL75 mlass="lxine mnam="vL75 > h75/f> sttic/ a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=pci_bus_clock_lita_ultra"class="leef=">pci_bus_clock_lita_ultra/f> (a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=epeed"class="leef=">epeed/f> , structchipset_bus_clock_lita_en=ry/f> *chipset_table/f> ) < ref=".rivers/ide/aec62xx.c"#L76 mid"vL76 mlass="lxine mnam="vL76 > h76/f> { < ref=".rivers/ide/aec62xx.c"#L77 mid"vL77 mlass="lxine mnam="vL77 > h77/f> for ( ;chipset_table/f> -gt;"/ ref=".+code=xfe_sepeed"class="leef=">xfe_sepeed/f> ;chipset_table/f> ++) < ref=".rivers/ide/aec62xx.c"#L78 mid"vL78 mlass="lxine mnam="vL78 > h78/f> if (a ref=".+code=chipset_table"class="leef=">chipset_table/f> -gt;"/ ref=".+code=xfe_sepeed"class="leef=">xfe_sepeed/f> == a ref=".+code=epeed"class="leef=">epeed/f> ) { < ref=".rivers/ide/aec62xx.c"#L79 mid"vL79 mlass="lxine mnam="vL79 > h79/f> etoptifa ref=".+code=chipset_table"class="leef=">chipset_table/f> -gt;"/ ref=".+code=ultra_settings"class="leef=">ultra_settings/f> " < ref=".rivers/ide/aec62xx.c"#L80 mid"vL80 mlass="lxine mnam="vL80 > h80/f> } < ref=".rivers/ide/aec62xx.c"#L81 mid"vL81 mlass="lxine mnam="vL81 > h81/f> etoptifa ref=".+code=chipset_table"class="leef=">chipset_table/f> -gt;"/ ref=".+code=ultra_settings"class="leef=">ultra_settings/f> " < ref=".rivers/ide/aec62xx.c"#L82 mid"vL82 mlass="lxine mnam="vL82 > h82/f> } < ref=".rivers/ide/aec62xx.c"#L83 mid"vL83 mlass="lxine mnam="vL83 > h83/f> < ref=".rivers/ide/aec62xx.c"#L84 mid"vL84 mlass="lxine mnam="vL84 > h84/f> sttic/ void a ref=".+code=ec62210_set_mode"class="leef=">ec62210_set_mode/f> (a ref=".+code=de/_hwif_a"class="leef=">de/_hwif_a/f> *a ref=".+code=hwif"class="leef=">hwif/f> , a ref=".+code=de/_river_a"class="leef=">de/_river_a/f> *a ref=".+code=river"class="leef=">river/f> ) < ref=".rivers/ide/aec62xx.c"#L85 mid"vL85 mlass="lxine mnam="vL85 > h85/f> { < ref=".rivers/ide/aec62xx.c"#L86 mid"vL86 mlass="lxine mnam="vL86 > h86/f> structpci_dev/f> *a ref=".+code=rev"class="leef=">dev/f> = a ref=".+code=to_pci_dev"class="leef=">to_pci_dev/f> (a ref=".+code=hwif"class="leef=">hwif/f> -gt;"/ ref=".+code=rev"class="leef=">dev/f> )" < ref=".rivers/ide/aec62xx.c"#L87 mid"vL87 mlass="lxine mnam="vL87 > h87/f> structde/_hota/f> *a ref=".+code=hota"class="leef=">hota/f> = a ref=".+code=pci_get_drvdata"class="leef=">pci_get_drvdata/f> (a ref=".+code=rev"class="leef=">dev/f> )" < ref=".rivers/ide/aec62xx.c"#L88 mid"vL88 mlass="lxine mnam="vL88 > h88/f> structchipset_bus_clock_lita_en=ry/f> *a ref=".+code=bus_clock"class="leef=">bus_clock/f> =hota/f> -gt;"/ ref=".+code=hota_pive"class="leef=">hota_pive/f> " < ref=".rivers/ide/aec62xx.c"#L89 mid"vL89 mlass="lxine mnam="vL89 > h89/f> a ref=".+code=u16"class="leef=">u16/f> a ref=".+code=d_conf"class="leef=">d_conf/f> = 0" < ref=".rivers/ide/aec62xx.c"#L90 mid"vL90 mlass="lxine mnam="vL90 > h90/f> a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=ultra"class="leef=">ultra/f> =<0, a ref=".+code=ultra_conf"class="leef=">ultra_conf/f> =<0" < ref=".rivers/ide/aec62xx.c"#L91 mid"vL91 mlass="lxine mnam="vL91 > h91/f> a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=tmp0"class="leef=">tmp0/f> =<0, a ref=".+code=tmp1"class="leef=">tmp1/f> =<0, a ref=".+code=tmp2"class="leef=">tmp2/f> =<0" < ref=".rivers/ide/aec62xx.c"#L92 mid"vL92 mlass="lxine mnam="vL92 > h92/f> const a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=epeed"class="leef=">epeed/f> =river/f> -gt;"/ ref=".+code=rma_mode"class="leef=">rma_mode/f> " < ref=".rivers/ide/aec62xx.c"#L93 mid"vL93 mlass="lxine mnam="vL93 > h93/f> unsigned longflags/f> " < ref=".rivers/ide/aec62xx.c"#L94 mid"vL94 mlass="lxine mnam="vL94 > h94/f> < ref=".rivers/ide/aec62xx.c"#L95 mid"vL95 mlass="lxine mnam="vL95 > h95/f> a ref=".+code=local_irq_saer"class="leef=">local_irq_saer/f> (a ref=".+code=flags"class="leef=">flags/f> )" < ref=".rivers/ide/aec62xx.c"#L96 mid"vL96 mlass="lxine mnam="vL96 > h96/f> span class="lcommen=">/* 0x40|(2*river-gt;"dn): Atiove, 0x41|(2*river-gt;"dn): Recoersy *//span> < ref=".rivers/ide/aec62xx.c"#L97 mid"vL97 mlass="lxine mnam="vL97 > h97/f> a ref=".+code=pci_read_config_word"class="leef=">pci_read_config_word/f> (a ref=".+code=rev"class="leef=">dev/f> , 0x40|(2*a ref=".+code=river"class="leef=">river/f> -gt;"/ ref=".+code=rn"class="leef=">rn/f> ), &"/ ref=".+code=r_conf"class="leef=">d_conf/f> )" < ref=".rivers/ide/aec62xx.c"#L98 mid"vL98 mlass="lxine mnam="vL98 > h98/f> a ref=".+code=tmp0"class="leef=">tmp0/f> =pci_bus_clock_lita/f> (a ref=".+code=epeed"class="leef=">epeed/f> , a ref=".+code=bus_clock"class="leef=">bus_clock/f> )" < ref=".rivers/ide/aec62xx.c"#L99 mid"vL99 mlass="lxine mnam="vL99 > h99/f> a ref=".+code=d_conf"class="leef=">d_conf/f> = ((a ref=".+code=tmp0"class="leef=">tmp0/f> &" 0xf0) << 4) | (a ref=".+code=tmp0"class="leef=">tmp0/f> &" 0xf)" < ref=".rivers/ide/aec62xx.c"#L100 mid"vL100 mlass="lxine mnam="vL100 > 100/f> a ref=".+code=pci_write_config_word"class="leef=">pci_write_config_word/f> (a ref=".+code=rev"class="leef=">dev/f> , 0x40|(2*a ref=".+code=river"class="leef=">river/f> -gt;"/ ref=".+code=rn"class="leef=">rn/f> ), / ref=".+code=r_conf"class="leef=">d_conf/f> )" < ref=".rivers/ide/aec62xx.c"#L101 mid"vL101 mlass="lxine mnam="vL101 > 101/f> < ref=".rivers/ide/aec62xx.c"#L102 mid"vL102 mlass="lxine mnam="vL102 > 102/f> a ref=".+code=tmp1"class="leef=">tmp1/f> =<0x00" < ref=".rivers/ide/aec62xx.c"#L103 mid"vL103 mlass="lxine mnam="vL103 > 103/f> a ref=".+code=tmp2"class="leef=">tmp2/f> =<0x00" < ref=".rivers/ide/aec62xx.c"#L104 mid"vL104 mlass="lxine mnam="vL104 > 104/f> a ref=".+code=pci_read_config_bytr"class="leef=">pci_read_config_bytr/f> (a ref=".+code=rev"class="leef=">dev/f> , 0x54, &"/ ref=".+code=ultra"class="leef=">ultra/f> )" < ref=".rivers/ide/aec62xx.c"#L105 mid"vL105 mlass="lxine mnam="vL105 > 105/f> a ref=".+code=tmp1"class="leef=">tmp1/f> =<((0x00 << (2*a ref=".+code=river"class="leef=">river/f> -gt;"/ ref=".+code=rn"class="leef=">rn/f> )) | (a ref=".+code=ultra"class="leef=">ultra/f> &" ~(3 << (2*a ref=".+code=river"class="leef=">river/f> -gt;"/ ref=".+code=rn"class="leef=">rn/f> ))))" < ref=".rivers/ide/aec62xx.c"#L106 mid"vL106 mlass="lxine mnam="vL106 > 106/f> a ref=".+code=ultra_conf"class="leef=">ultra_conf/f> =pci_bus_clock_lita_ultra/f> (a ref=".+code=epeed"class="leef=">epeed/f> , a ref=".+code=bus_clock"class="leef=">bus_clock/f> )" < ref=".rivers/ide/aec62xx.c"#L107 mid"vL107 mlass="lxine mnam="vL107 > 107/f> a ref=".+code=tmp2"class="leef=">tmp2/f> =<((a ref=".+code=ultra_conf"class="leef=">ultra_conf/f> << (2*a ref=".+code=river"class="leef=">river/f> -gt;"/ ref=".+code=rn"class="leef=">rn/f> )) | (a ref=".+code=tmp1"class="leef=">tmp1/f> &" ~(3 << (2*a ref=".+code=river"class="leef=">river/f> -gt;"/ ref=".+code=rn"class="leef=">rn/f> ))))" < ref=".rivers/ide/aec62xx.c"#L108 mid"vL108 mlass="lxine mnam="vL108 > 108/f> a ref=".+code=pci_write_config_bytr"class="leef=">pci_write_config_bytr/f> (a ref=".+code=rev"class="leef=">dev/f> , 0x54, a ref=".+code=tmp2"class="leef=">tmp2/f> )" < ref=".rivers/ide/aec62xx.c"#L109 mid"vL109 mlass="lxine mnam="vL109 > 109/f> a ref=".+code=local_irq_restorr"class="leef=">local_irq_restorr/f> (a ref=".+code=flags"class="leef=">flags/f> )" < ref=".rivers/ide/aec62xx.c"#L110 mid"vL110 mlass="lxine mnam="vL110 > 10 } < ref=".rivers/ide/aec62xx.c"#L111 mid"vL111 mlass="lxine mnam="vL111 > 111/f> < ref=".rivers/ide/aec62xx.c"#L112 mid"vL112 mlass="lxine mnam="vL112 > 112/f> sttic/ void a ref=".+code=ec62260_set_mode"class="leef=">ec62260_set_mode/f> (a ref=".+code=de/_hwif_a"class="leef=">de/_hwif_a/f> *a ref=".+code=hwif"class="leef=">hwif/f> , a ref=".+code=de/_river_a"class="leef=">de/_river_a/f> *a ref=".+code=river"class="leef=">river/f> ) < ref=".rivers/ide/aec62xx.c"#L113 mid"vL113 mlass="lxine mnam="vL113 > 113/o> { < ref=".rivers/ide/aec62xx.c"#L114 mid"vL114 mlass="lxine mnam="vL114 > 114/f> structpci_dev/f> *a ref=".+code=rev"class="leef=">dev/f> = a ref=".+code=to_pci_dev"class="leef=">to_pci_dev/f> (a ref=".+code=hwif"class="leef=">hwif/f> -gt;"/ ref=".+code=rev"class="leef=">dev/f> )" < ref=".rivers/ide/aec62xx.c"#L115 mid"vL115 mlass="lxine mnam="vL115 > 115/f> structde/_hota/f> *a ref=".+code=hota"class="leef=">hota/f> = a ref=".+code=pci_get_drvdata"class="leef=">pci_get_drvdata/f> (a ref=".+code=rev"class="leef=">dev/f> )" < ref=".rivers/ide/aec62xx.c"#L116 mid"vL116 mlass="lxine mnam="vL116 > 116/f> structchipset_bus_clock_lita_en=ry/f> *a ref=".+code=bus_clock"class="leef=">bus_clock/f> =hota/f> -gt;"/ ref=".+code=hota_pive"class="leef=">hota_pive/f> " < ref=".rivers/ide/aec62xx.c"#L117 mid"vL117 mlass="lxine mnam="vL117 > 117/f> a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=unia"class="leef=">unia/f> = a ref=".+code=river"class="leef=">river/f> -gt;"/ ref=".+code=rn"class="leef=">rn/f> &" 1" < ref=".rivers/ide/aec62xx.c"#L118 mid"vL118 mlass="lxine mnam="vL118 > 118/f> a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=tmp1"class="leef=">tmp1/f> =<0, a ref=".+code=tmp2"class="leef=">tmp2/f> =<0" < ref=".rivers/ide/aec62xx.c"#L119 mid"vL119 mlass="lxine mnam="vL119 > 119/f> a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=ultra"class="leef=">ultra/f> =<0, a ref=".+code=river_conf"class="leef=">diver_conf/f> =<0, a ref=".+code=ultra_conf"class="leef=">ultra_conf/f> =<0" < ref=".rivers/ide/aec62xx.c"#L120 mid"vL120 mlass="lxine mnam="vL120 > 120/f> const a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=epeed"class="leef=">epeed/f> =river/f> -gt;"/ ref=".+code=rma_mode"class="leef=">rma_mode/f> " < ref=".rivers/ide/aec62xx.c"#L121 mid"vL121 mlass="lxine mnam="vL121 > 121/f> unsigned longflags/f> " < ref=".rivers/ide/aec62xx.c"#L122 mid"vL122 mlass="lxine mnam="vL122 > 122/f> < ref=".rivers/ide/aec62xx.c"#L123 mid"vL123 mlass="lxine mnam="vL123 > 123/f> a ref=".+code=local_irq_saer"class="leef=">local_irq_saer/f> (a ref=".+code=flags"class="leef=">flags/f> )" < ref=".rivers/ide/aec62xx.c"#L124 mid"vL124 mlass="lxine mnam="vL124 > 124/f> span class="lcommen=">/* high 4-bits: Atiove, low 4-bits: Recoersy *//span> < ref=".rivers/ide/aec62xx.c"#L125 mid"vL125 mlass="lxine mnam="vL125 > 125/f> a ref=".+code=pci_read_config_bytr"class="leef=">pci_read_config_bytr/f> (a ref=".+code=rev"class="leef=">dev/f> , 0x40|a ref=".+code=river"class="leef=">river/f> -gt;"/ ref=".+code=rn"class="leef=">rn/f> , &"/ ref=".+code=river_conf"class="leef=">diver_conf/f> )" < ref=".rivers/ide/aec62xx.c"#L126 mid"vL126 mlass="lxine mnam="vL126 > 126/f> a ref=".+code=river_conf"class="leef=">diver_conf/f> =pci_bus_clock_lita/f> (a ref=".+code=epeed"class="leef=">epeed/f> , a ref=".+code=bus_clock"class="leef=">bus_clock/f> )" < ref=".rivers/ide/aec62xx.c"#L127 mid"vL127 mlass="lxine mnam="vL127 > 127/f> a ref=".+code=pci_write_config_bytr"class="leef=">pci_write_config_bytr/f> (a ref=".+code=rev"class="leef=">dev/f> , 0x40|a ref=".+code=river"class="leef=">river/f> -gt;"/ ref=".+code=rn"class="leef=">rn/f> , / ref=".+code=river_conf"class="leef=">diver_conf/f> )" < ref=".rivers/ide/aec62xx.c"#L128 mid"vL128 mlass="lxine mnam="vL128 > 128/f> < ref=".rivers/ide/aec62xx.c"#L129 mid"vL129 mlass="lxine mnam="vL129 > 129/f> a ref=".+code=pci_read_config_bytr"class="leef=">pci_read_config_bytr/f> (a ref=".+code=rev"class="leef=">dev/f> , (0x44|a ref=".+code=hwif"class="leef=">hwif/f> -gt;"/ ref=".+code=channel"class="leef=">channel/f> ), &"/ ref=".+code=ultra"class="leef=">ultra/f> )" < ref=".rivers/ide/aec62xx.c"#L130 mid"vL130 mlass="lxine mnam="vL130 > 130/f> a ref=".+code=tmp1"class="leef=">tmp1/f> =<((0x00 << (4*a ref=".+code=unia"class="leef=">unia/f> )) | (a ref=".+code=ultra"class="leef=">ultra/f> &" ~(7 << (4*a ref=".+code=unia"class="leef=">unia/f> ))))" < ref=".rivers/ide/aec62xx.c"#L131 mid"vL131 mlass="lxine mnam="vL131 > 131/f> a ref=".+code=ultra_conf"class="leef=">ultra_conf/f> =pci_bus_clock_lita_ultra/f> (a ref=".+code=epeed"class="leef=">epeed/f> , a ref=".+code=bus_clock"class="leef=">bus_clock/f> )" < ref=".rivers/ide/aec62xx.c"#L132 mid"vL132 mlass="lxine mnam="vL132 > 132/f> a ref=".+code=tmp2"class="leef=">tmp2/f> =<((a ref=".+code=ultra_conf"class="leef=">ultra_conf/f> << (4*a ref=".+code=unia"class="leef=">unia/f> )) | (a ref=".+code=tmp1"class="leef=">tmp1/f> &" ~(7 << (4*a ref=".+code=unia"class="leef=">unia/f> ))))" < ref=".rivers/ide/aec62xx.c"#L133 mid"vL133 mlass="lxine mnam="vL133 > 133/f> a ref=".+code=pci_write_config_bytr"class="leef=">pci_write_config_bytr/f> (a ref=".+code=rev"class="leef=">dev/f> , (0x44|a ref=".+code=hwif"class="leef=">hwif/f> -gt;"/ ref=".+code=channel"class="leef=">channel/f> ), a ref=".+code=tmp2"class="leef=">tmp2/f> )" < ref=".rivers/ide/aec62xx.c"#L134 mid"vL134 mlass="lxine mnam="vL134 > 134/f> a ref=".+code=local_irq_restorr"class="leef=">local_irq_restorr/f> (a ref=".+code=flags"class="leef=">flags/f> )" < ref=".rivers/ide/aec62xx.c"#L135 mid"vL135 mlass="lxine mnam="vL135 > 135/f> } < ref=".rivers/ide/aec62xx.c"#L136 mid"vL136 mlass="lxine mnam="vL136 > 136/f> < ref=".rivers/ide/aec62xx.c"#L137 mid"vL137 mlass="lxine mnam="vL137 > 137/f> sttic/ void a ref=".+code=ec6_set_pio_mode"class="leef=">ec6_set_pio_mode/f> (a ref=".+code=de/_hwif_a"class="leef=">de/_hwif_a/f> *a ref=".+code=hwif"class="leef=">hwif/f> , a ref=".+code=de/_river_a"class="leef=">de/_river_a/f> *a ref=".+code=river"class="leef=">river/f> ) < ref=".rivers/ide/aec62xx.c"#L138 mid"vL138 mlass="lxine mnam="vL138 > 138/f> { < ref=".rivers/ide/aec62xx.c"#L139 mid"vL139 mlass="lxine mnam="vL139 > 139/f> a ref=".+code=diver"class="leef=">river/f> -gt;"/ ref=".+code=rma_mode"class="leef=">rma_mode/f> =river/f> -gt;"/ ref=".+code=pio_mode"class="leef=">pio_mode/f> " < ref=".rivers/ide/aec62xx.c"#L140 mid"vL140 mlass="lxine mnam="vL140 > 140/f> a ref=".+code=hwif"class="leef=">hwif/f> -gt;"/ ref=".+code=port_ops"class="leef=">port_ops/f> -gt;"/ ref=".+code=set_rma_mode"class="leef=">set_rma_mode/f> (a ref=".+code=hwif"class="leef=">hwif/f> , / ref=".+code=river"class="leef=">river/f> )" < ref=".rivers/ide/aec62xx.c"#L141 mid"vL141 mlass="lxine mnam="vL141 > 141/o> } < ref=".rivers/ide/aec62xx.c"#L142 mid"vL142 mlass="lxine mnam="vL142 > 142/f> < ref=".rivers/ide/aec62xx.c"#L143 mid"vL143 mlass="lxine mnam="vL143 > 143/f> sttic/ intdnia_chipset_ec62xx./f> (structpci_dev/f> *a ref=".+code=rev"class="leef=">dev/f> ) < ref=".rivers/ide/aec62xx.c"#L144 mid"vL144 mlass="lxine mnam="vL144 > 144/f> { < ref=".rivers/ide/aec62xx.c"#L145 mid"vL145 mlass="lxine mnam="vL145 > 145/f> span class="lcommen=">/* These are necessary to get AEC6280 Macintosh cards to work *//span> < ref=".rivers/ide/aec62xx.c"#L146 mid"vL146 mlass="lxine mnam="vL146 > 146/f> if ((a ref=".+code=rev"class="leef=">dev/f> -gt;"/ ref=".+code=revicr"class="leef=">revicr/f> == 147/f> (a ref=".+code=rev"class="leef=">dev/f> -gt;"/ ref=".+code=revicr"class="leef=">revicr/f> == 148/f> a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=reg49h"class="leef=">reg49h/f> =<0, a ref=".+code=reg4ah"class="leef=">reg4ah/f> =<0" < ref=".rivers/ide/aec62xx.c"#L149 mid"vL149 mlass="lxine mnam="vL149 > 149/f> span class="lcommen=">/* Clear reset and test bits. *//span> < ref=".rivers/ide/aec62xx.c"#L150 mid"vL150 mlass="lxine mnam="vL150 > 150/f> a ref=".+code=pci_read_config_bytr"class="leef=">pci_read_config_bytr/f> (a ref=".+code=rev"class="leef=">dev/f> , 0x49, &"/ ref=".+code=reg49h"class="leef=">reg49h/f> )" < ref=".rivers/ide/aec62xx.c"#L151 mid"vL151 mlass="lxine mnam="vL151 > 151/f> a ref=".+code=pci_write_config_bytr"class="leef=">pci_write_config_bytr/f> (a ref=".+code=rev"class="leef=">dev/f> , 0x49, a ref=".+code=reg49h"class="leef=">reg49h/f> &" ~0x30)" < ref=".rivers/ide/aec62xx.c"#L152 mid"vL152 mlass="lxine mnam="vL152 > 152/f> span class="lcommen=">/* Enable chip interrupt output. *//span> < ref=".rivers/ide/aec62xx.c"#L153 mid"vL153 mlass="lxine mnam="vL153 > 153/f> a ref=".+code=pci_read_config_bytr"class="leef=">pci_read_config_bytr/f> (a ref=".+code=rev"class="leef=">dev/f> , 0x4a, &"/ ref=".+code=reg4ah"class="leef=">reg4ah/f> )" < ref=".rivers/ide/aec62xx.c"#L154 mid"vL154 mlass="lxine mnam="vL154 > 154/f> a ref=".+code=pci_write_config_bytr"class="leef=">pci_write_config_bytr/f> (a ref=".+code=rev"class="leef=">dev/f> , 0x4a, a ref=".+code=reg4ah"class="leef=">reg4ah/f> &" ~0x01)" < ref=".rivers/ide/aec62xx.c"#L155 mid"vL155 mlass="lxine mnam="vL155 > 155/f> span class="lcommen=">/* Enable burst mode. *//span> < ref=".rivers/ide/aec62xx.c"#L156 mid"vL156 mlass="lxine mnam="vL156 > 156/f> a ref=".+code=pci_read_config_bytr"class="leef=">pci_read_config_bytr/f> (a ref=".+code=rev"class="leef=">dev/f> , 0x4a, &"/ ref=".+code=reg4ah"class="leef=">reg4ah/f> )" < ref=".rivers/ide/aec62xx.c"#L157 mid"vL157 mlass="lxine mnam="vL157 > 157/f> a ref=".+code=pci_write_config_bytr"class="leef=">pci_write_config_bytr/f> (a ref=".+code=rev"class="leef=">dev/f> , 0x4a, a ref=".+code=reg4ah"class="leef=">reg4ah/f> | 0x80)" < ref=".rivers/ide/aec62xx.c"#L158 mid"vL158 mlass="lxine mnam="vL158 > 158/f> } < ref=".rivers/ide/aec62xx.c"#L159 mid"vL159 mlass="lxine mnam="vL159 > 159/f> < ref=".rivers/ide/aec62xx.c"#L160 mid"vL160 mlass="lxine mnam="vL160 > 160/f> etoptif0" < ref=".rivers/ide/aec62xx.c"#L161 mid"vL161 mlass="lxine mnam="vL161 > 161/o> } < ref=".rivers/ide/aec62xx.c"#L162 mid"vL162 mlass="lxine mnam="vL162 > 162/f> < ref=".rivers/ide/aec62xx.c"#L163 mid"vL163 mlass="lxine mnam="vL163 > 163/f> sttic/ a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=atp86x_cable_deteca"class="leef=">atp86x_cable_deteca/f> (a ref=".+code=de/_hwif_a"class="leef=">de/_hwif_a/f> *a ref=".+code=hwif"class="leef=">hwif/f> ) < ref=".rivers/ide/aec62xx.c"#L164 mid"vL164 mlass="lxine mnam="vL164 > 164/f> { < ref=".rivers/ide/aec62xx.c"#L165 mid"vL165 mlass="lxine mnam="vL165 > 165/f> structpci_dev/f> *a ref=".+code=rev"class="leef=">dev/f> = a ref=".+code=to_pci_dev"class="leef=">to_pci_dev/f> (a ref=".+code=hwif"class="leef=">hwif/f> -gt;"/ ref=".+code=rev"class="leef=">dev/f> )" < ref=".rivers/ide/aec62xx.c"#L166 mid"vL166 mlass="lxine mnam="vL166 > 166/f> a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=ata66 mlass="leef=">ata66/f> =<0, a ref=".+code=mask"class="leef=">mask/f> = a ref=".+code=hwif"class="leef=">hwif/f> -gt;"/ ref=".+code=channel"class="leef=">channel/f> ? 0x02 : 0x01" < ref=".rivers/ide/aec62xx.c"#L167 mid"vL167 mlass="lxine mnam="vL167 > 167/f> < ref=".rivers/ide/aec62xx.c"#L168 mid"vL168 mlass="lxine mnam="vL168 > 168/f> a ref=".+code=pci_read_config_bytr"class="leef=">pci_read_config_bytr/f> (a ref=".+code=rev"class="leef=">dev/f> , 0x49, &"/ ref=".+code=ata66 mlass="leef=">ata66/f> )" < ref=".rivers/ide/aec62xx.c"#L169 mid"vL169 mlass="lxine mnam="vL169 > 169/f> < ref=".rivers/ide/aec62xx.c"#L170 mid"vL170 mlass="lxine mnam="vL170 > 170/f> etoptif(a ref=".+code=ata66 mlass="leef=">ata66/f> &" a ref=".+code=mask"class="leef=">mask/f> ) ? a ref=".+code=ATA_CBL_PATA40"class="leef=">ATA_CBL_PATA40/f> : a ref=".+code=ATA_CBL_PATA80"class="leef=">ATA_CBL_PATA80/f> " < ref=".rivers/ide/aec62xx.c"#L171 mid"vL171 mlass="lxine mnam="vL171 > 171/o> } < ref=".rivers/ide/aec62xx.c"#L172 mid"vL172 mlass="lxine mnam="vL172 > 172/f> < ref=".rivers/ide/aec62xx.c"#L173 mid"vL173 mlass="lxine mnam="vL173 > 173/f> sttic/ const structde/_port_ops/f> a ref=".+code=atp850_port_ops"class="leef=">atp850_port_ops/f> = { < ref=".rivers/ide/aec62xx.c"#L174 mid"vL174 mlass="lxine mnam="vL174 > 174/f> ./ ref=".+code=set_pio_mode"class="leef=">set_pio_mode/f> = a ref=".+code=ec6_set_pio_mode"class="leef=">ec6_set_pio_mode/f> , < ref=".rivers/ide/aec62xx.c"#L175 mid"vL175 mlass="lxine mnam="vL175 > 175/f> ./ ref=".+code=set_rma_mode"class="leef=">set_rma_mode/f> = a ref=".+code=ec62210_set_mode"class="leef=">ec62210_set_mode/f> , < ref=".rivers/ide/aec62xx.c"#L176 mid"vL176 mlass="lxine mnam="vL176 > 176/f> }" < ref=".rivers/ide/aec62xx.c"#L177 mid"vL177 mlass="lxine mnam="vL177 > 177/f> < ref=".rivers/ide/aec62xx.c"#L178 mid"vL178 mlass="lxine mnam="vL178 > 178/f> sttic/ const structde/_port_ops/f> a ref=".+code=atp86x_port_ops"class="leef=">atp86x_port_ops/f> = { < ref=".rivers/ide/aec62xx.c"#L179 mid"vL179 mlass="lxine mnam="vL179 > 179/f> ./ ref=".+code=set_pio_mode"class="leef=">set_pio_mode/f> = a ref=".+code=ec6_set_pio_mode"class="leef=">ec6_set_pio_mode/f> , < ref=".rivers/ide/aec62xx.c"#L180 mid"vL180 mlass="lxine mnam="vL180 > 180/f> ./ ref=".+code=set_rma_mode"class="leef=">set_rma_mode/f> = a ref=".+code=ec62260_set_mode"class="leef=">ec62260_set_mode/f> , < ref=".rivers/ide/aec62xx.c"#L181 mid"vL181 mlass="lxine mnam="vL181 > 181/f> ./ ref=".+code=cable_deteca"class="leef=">cable_deteca/f> = a ref=".+code=etp86x_cable_deteca"class="leef=">atp86x_cable_deteca/f> , < ref=".rivers/ide/aec62xx.c"#L182 mid"vL182 mlass="lxine mnam="vL182 > 182/f> }" < ref=".rivers/ide/aec62xx.c"#L183 mid"vL183 mlass="lxine mnam="vL183 > 183/f> < ref=".rivers/ide/aec62xx.c"#L184 mid"vL184 mlass="lxine mnam="vL184 > 184/f> sttic/ const structde/_port_info/f> a ref=".+code=ac62xx._chipsets"class="leef=">ac62xx._chipsets/f> [] = { < ref=".rivers/ide/aec62xx.c"#L185 mid"vL185 mlass="lxine mnam="vL185 > 185/f> { apan class="lcommen=">/* 0: AEC6210 *//span> < ref=".rivers/ide/aec62xx.c"#L186 mid"vL186 mlass="lxine mnam="vL186 > 186/f> ./ ref=".+code=nam="class="leef=">nam=/f> = a ref=".+code=DRV_NAME"class="leef=">DRV_NAME/f> , < ref=".rivers/ide/aec62xx.c"#L187 mid"vL187 mlass="lxine mnam="vL187 > 187/f> ./ ref=".+code=dnia_chipset"class="leef=">dnia_chipset/f> = a ref=".+code=dnia_chipset_ec62xx."class="leef=">dnia_chipset_ec62xx./f> , < ref=".rivers/ide/aec62xx.c"#L188 mid"vL188 mlass="lxine mnam="vL188 > 188/f> ./ ref=".+code=enablebits"class="leef=">enablebits/f> = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, < ref=".rivers/ide/aec62xx.c"#L189 mid"vL189 mlass="lxine mnam="vL189 > 189/f> ./ ref=".+code=port_ops"class="leef=">port_ops/f> = &"/ ref=".+code=atp850_port_ops"class="leef=">atp850_port_ops/f> , < ref=".rivers/ide/aec62xx.c"#L190 mid"vL190 mlass="lxine mnam="vL190 > 190/f> ./ ref=".+code=hota_flags"class="leef=">hota_flags/f> = / ref=".+code=IDE_HFLAG_SERIALIZE"class="leef=">IDE_HFLAG_SERIALIZE/f> | < ref=".rivers/ide/aec62xx.c"#L191 mid"vL191 mlass="lxine mnam="vL191 > 191/f> / ref=".+code=IDE_HFLAG_NO_ATAPI_DMA"class="leef=">IDE_HFLAG_NO_ATAPI_DMA/f> | < ref=".rivers/ide/aec62xx.c"#L192 mid"vL192 mlass="lxine mnam="vL192 > 192/f> / ref=".+code=IDE_HFLAG_NO_DSC"class="leef=">IDE_HFLAG_NO_DSC/f> | < ref=".rivers/ide/aec62xx.c"#L193 mid"vL193 mlass="lxine mnam="vL193 > 193/f> / ref=".+code=IDE_HFLAG_OFF_BOARD"class="leef=">IDE_HFLAG_OFF_BOARD/f> , < ref=".rivers/ide/aec62xx.c"#L194 mid"vL194 mlass="lxine mnam="vL194 > 194/f> ./ ref=".+code=pio_mask"class="leef=">pio_mask/f> = a ref=".+code=ATA_PIO4"class="leef=">ATA_PIO4/f> , < ref=".rivers/ide/aec62xx.c"#L195 mid"vL195 mlass="lxine mnam="vL195 > 195/f> ./ ref=".+code=mwrma_mask"class="leef=">mwrma_mask/f> = / ref=".+code=ATA_MWDMA2"class="leef=">ATA_MWDMA2/f> , < ref=".rivers/ide/aec62xx.c"#L196 mid"vL196 mlass="lxine mnam="vL196 > 196/f> ./ ref=".+code=urma_mask"class="leef=">urma_mask/f> = / ref=".+code=ATA_UDMA2"class="leef=">ATA_UDMA2/f> , < ref=".rivers/ide/aec62xx.c"#L197 mid"vL197 mlass="lxine mnam="vL197 > 197/f> }, < ref=".rivers/ide/aec62xx.c"#L198 mid"vL198 mlass="lxine mnam="vL198 > 198/f> { apan class="lcommen=">/* 1: AEC6260 *//span> < ref=".rivers/ide/aec62xx.c"#L199 mid"vL199 mlass="lxine mnam="vL199 > 199/f> ./ ref=".+code=nam="class="leef=">nam=/f> = a ref=".+code=DRV_NAME"class="leef=">DRV_NAME/f> , < ref=".rivers/ide/aec62xx.c"#L200 mid"vL200 mlass="lxine mnam="vL200 > 200/f> ./ ref=".+code=dnia_chipset"class="leef=">dnia_chipset/f> = a ref=".+code=dnia_chipset_ec62xx."class="leef=">dnia_chipset_ec62xx./f> , < ref=".rivers/ide/aec62xx.c"#L201 mid"vL201 mlass="lxine mnam="vL201 > 201/f> ./ ref=".+code=port_ops"class="leef=">port_ops/f> = &"/ ref=".+code=atp86x_port_ops"class="leef=">atp86x_port_ops/f> , < ref=".rivers/ide/aec62xx.c"#L202 mid"vL202 mlass="lxine mnam="vL202 > 202/f> ./ ref=".+code=hota_flags"class="leef=">hota_flags/f> = / ref=".+code=IDE_HFLAG_NO_ATAPI_DMA"class="leef=">IDE_HFLAG_NO_ATAPI_DMA/f> | / ref=".+code=IDE_HFLAG_NO_AUTODMA"class="leef=">IDE_HFLAG_NO_AUTODMA/f> | < ref=".rivers/ide/aec62xx.c"#L203 mid"vL203 mlass="lxine mnam="vL203 > 203/f> / ref=".+code=IDE_HFLAG_OFF_BOARD"class="leef=">IDE_HFLAG_OFF_BOARD/f> , < ref=".rivers/ide/aec62xx.c"#L204 mid"vL204 mlass="lxine mnam="vL204 > 204/f> ./ ref=".+code=pio_mask"class="leef=">pio_mask/f> = a ref=".+code=ATA_PIO4"class="leef=">ATA_PIO4/f> , < ref=".rivers/ide/aec62xx.c"#L205 mid"vL205 mlass="lxine mnam="vL205 > 205/f> ./ ref=".+code=mwrma_mask"class="leef=">mwrma_mask/f> = / ref=".+code=ATA_MWDMA2"class="leef=">ATA_MWDMA2/f> , < ref=".rivers/ide/aec62xx.c"#L206 mid"vL206 mlass="lxine mnam="vL206 > 206/f> ./ ref=".+code=urma_mask"class="leef=">urma_mask/f> = / ref=".+code=ATA_UDMA4"class="leef=">ATA_UDMA4/f> , < ref=".rivers/ide/aec62xx.c"#L207 mid"vL207 mlass="lxine mnam="vL207 > 207/f> }, < ref=".rivers/ide/aec62xx.c"#L208 mid"vL208 mlass="lxine mnam="vL208 > 208/f> { apan class="lcommen=">/* 2: AEC6260R *//span> < ref=".rivers/ide/aec62xx.c"#L209 mid"vL209 mlass="lxine mnam="vL209 > 209/f> ./ ref=".+code=nam="class="leef=">nam=/f> = a ref=".+code=DRV_NAME"class="leef=">DRV_NAME/f> , < ref=".rivers/ide/aec62xx.c"#L210 mid"vL210 mlass="lxine mnam="vL210 > 210/f> ./ ref=".+code=dnia_chipset"class="leef=">dnia_chipset/f> = a ref=".+code=dnia_chipset_ec62xx."class="leef=">dnia_chipset_ec62xx./f> , < ref=".rivers/ide/aec62xx.c"#L211 mid"vL211 mlass="lxine mnam="vL211 > 211/f> ./ ref=".+code=enablebits"class="leef=">enablebits/f> = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, < ref=".rivers/ide/aec62xx.c"#L212 mid"vL212 mlass="lxine mnam="vL212 > 212/f> ./ ref=".+code=port_ops"class="leef=">port_ops/f> = &"/ ref=".+code=atp86x_port_ops"class="leef=">atp86x_port_ops/f> , < ref=".rivers/ide/aec62xx.c"#L213 mid"vL213 mlass="lxine mnam="vL213 > 213/f> ./ ref=".+code=hota_flags"class="leef=">hota_flags/f> = / ref=".+code=IDE_HFLAG_NO_ATAPI_DMA"class="leef=">IDE_HFLAG_NO_ATAPI_DMA/f> | < ref=".rivers/ide/aec62xx.c"#L214 mid"vL214 mlass="lxine mnam="vL214 > 214/f> / ref=".+code=IDE_HFLAG_NON_BOOTABLE"class="leef=">IDE_HFLAG_NON_BOOTABLE/f> , < ref=".rivers/ide/aec62xx.c"#L215 mid"vL215 mlass="lxine mnam="vL215 > 215/f> ./ ref=".+code=pio_mask"class="leef=">pio_mask/f> = a ref=".+code=ATA_PIO4"class="leef=">ATA_PIO4/f> , < ref=".rivers/ide/aec62xx.c"#L216 mid"vL216 mlass="lxine mnam="vL216 > 216/f> ./ ref=".+code=mwrma_mask"class="leef=">mwrma_mask/f> = / ref=".+code=ATA_MWDMA2"class="leef=">ATA_MWDMA2/f> , < ref=".rivers/ide/aec62xx.c"#L217 mid"vL217 mlass="lxine mnam="vL217 > 217/f> ./ ref=".+code=urma_mask"class="leef=">urma_mask/f> = / ref=".+code=ATA_UDMA4"class="leef=">ATA_UDMA4/f> , < ref=".rivers/ide/aec62xx.c"#L218 mid"vL218 mlass="lxine mnam="vL218 > 218/f> }, < ref=".rivers/ide/aec62xx.c"#L219 mid"vL219 mlass="lxine mnam="vL219 > 219/f> { apan class="lcommen=">/* 3: AEC6280 *//span> < ref=".rivers/ide/aec62xx.c"#L220 mid"vL220 mlass="lxine mnam="vL220 > 220/f> ./ ref=".+code=nam="class="leef=">nam=/f> = a ref=".+code=DRV_NAME"class="leef=">DRV_NAME/f> , < ref=".rivers/ide/aec62xx.c"#L221 mid"vL221 mlass="lxine mnam="vL221 > 221/f> ./ ref=".+code=dnia_chipset"class="leef=">dnia_chipset/f> = a ref=".+code=dnia_chipset_ec62xx."class="leef=">dnia_chipset_ec62xx./f> , < ref=".rivers/ide/aec62xx.c"#L222 mid"vL222 mlass="lxine mnam="vL222 > 222/f> ./ ref=".+code=port_ops"class="leef=">port_ops/f> = &"/ ref=".+code=atp86x_port_ops"class="leef=">atp86x_port_ops/f> , < ref=".rivers/ide/aec62xx.c"#L223 mid"vL223 mlass="lxine mnam="vL223 > 223/f> ./ ref=".+code=hota_flags"class="leef=">hota_flags/f> = / ref=".+code=IDE_HFLAG_NO_ATAPI_DMA"class="leef=">IDE_HFLAG_NO_ATAPI_DMA/f> | < ref=".rivers/ide/aec62xx.c"#L224 mid"vL224 mlass="lxine mnam="vL224 > 224/f> / ref=".+code=IDE_HFLAG_OFF_BOARD"class="leef=">IDE_HFLAG_OFF_BOARD/f> , < ref=".rivers/ide/aec62xx.c"#L225 mid"vL225 mlass="lxine mnam="vL225 > 225/f> ./ ref=".+code=pio_mask"class="leef=">pio_mask/f> = a ref=".+code=ATA_PIO4"class="leef=">ATA_PIO4/f> , < ref=".rivers/ide/aec62xx.c"#L226 mid"vL226 mlass="lxine mnam="vL226 > 226/f> ./ ref=".+code=mwrma_mask"class="leef=">mwrma_mask/f> = / ref=".+code=ATA_MWDMA2"class="leef=">ATA_MWDMA2/f> , < ref=".rivers/ide/aec62xx.c"#L227 mid"vL227 mlass="lxine mnam="vL227 > 227/f> ./ ref=".+code=urma_mask"class="leef=">urma_mask/f> = / ref=".+code=ATA_UDMA5 mlass="leef=">ATA_UDMA5/f> , < ref=".rivers/ide/aec62xx.c"#L228 mid"vL228 mlass="lxine mnam="vL228 > 228/f> }, < ref=".rivers/ide/aec62xx.c"#L229 mid"vL229 mlass="lxine mnam="vL229 > 229/f> { apan class="lcommen=">/* 4: AEC6280R *//span> < ref=".rivers/ide/aec62xx.c"#L230 mid"vL230 mlass="lxine mnam="vL230 > 230/f> ./ ref=".+code=nam="class="leef=">nam=/f> = a ref=".+code=DRV_NAME"class="leef=">DRV_NAME/f> , < ref=".rivers/ide/aec62xx.c"#L231 mid"vL231 mlass="lxine mnam="vL231 > 231/f> ./ ref=".+code=dnia_chipset"class="leef=">dnia_chipset/f> = a ref=".+code=dnia_chipset_ec62xx."class="leef=">dnia_chipset_ec62xx./f> , < ref=".rivers/ide/aec62xx.c"#L232 mid"vL232 mlass="lxine mnam="vL232 > 232/f> ./ ref=".+code=enablebits"class="leef=">enablebits/f> = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, < ref=".rivers/ide/aec62xx.c"#L233 mid"vL233 mlass="lxine mnam="vL233 > 233/f> ./ ref=".+code=port_ops"class="leef=">port_ops/f> = &"/ ref=".+code=atp86x_port_ops"class="leef=">atp86x_port_ops/f> , < ref=".rivers/ide/aec62xx.c"#L234 mid"vL234 mlass="lxine mnam="vL234 > 234/f> ./ ref=".+code=hota_flags"class="leef=">hota_flags/f> = / ref=".+code=IDE_HFLAG_NO_ATAPI_DMA"class="leef=">IDE_HFLAG_NO_ATAPI_DMA/f> | < ref=".rivers/ide/aec62xx.c"#L235 mid"vL235 mlass="lxine mnam="vL235 > 235/f> / ref=".+code=IDE_HFLAG_OFF_BOARD"class="leef=">IDE_HFLAG_OFF_BOARD/f> , < ref=".rivers/ide/aec62xx.c"#L236 mid"vL236 mlass="lxine mnam="vL236 > 236/f> ./ ref=".+code=pio_mask"class="leef=">pio_mask/f> = a ref=".+code=ATA_PIO4"class="leef=">ATA_PIO4/f> , < ref=".rivers/ide/aec62xx.c"#L237 mid"vL237 mlass="lxine mnam="vL237 > 237/f> ./ ref=".+code=mwrma_mask"class="leef=">mwrma_mask/f> = / ref=".+code=ATA_MWDMA2"class="leef=">ATA_MWDMA2/f> , < ref=".rivers/ide/aec62xx.c"#L238 mid"vL238 mlass="lxine mnam="vL238 > 238/f> ./ ref=".+code=urma_mask"class="leef=">urma_mask/f> = / ref=".+code=ATA_UDMA5 mlass="leef=">ATA_UDMA5/f> , < ref=".rivers/ide/aec62xx.c"#L239 mid"vL239 mlass="lxine mnam="vL239 > 239/f> } < ref=".rivers/ide/aec62xx.c"#L240 mid"vL240 mlass="lxine mnam="vL240 > 240/f> }" < ref=".rivers/ide/aec62xx.c"#L241 mid"vL241 mlass="lxine mnam="vL241 > 241/f> < ref=".rivers/ide/aec62xx.c"#L242 mid"vL242 mlass="lxine mnam="vL242 > 242/f> apan class="lcommen=">/**/span> < ref=".rivers/ide/aec62xx.c"#L243 mid"vL243 mlass="lxine mnam="vL243 > 243/f> apan class="lcommen="> * ac62xx._dnia_one - called when a AEC is found/span> < ref=".rivers/ide/aec62xx.c"#L244 mid"vL244 mlass="lxine mnam="vL244 > 244/f> apan class="lcommen="> * @dev: the ac62xx. revicr/fpan> < ref=".rivers/ide/aec62xx.c"#L245 mid"vL245 mlass="lxine mnam="vL245 > 245/f> apan class="lcommen="> * @id: the matching pcimid/fpan> < ref=".rivers/ide/aec62xx.c"#L246 mid"vL246 mlass="lxine mnam="vL246 > 246/f> apan class="lcommen="> */fpan> < ref=".rivers/ide/aec62xx.c"#L247 mid"vL247 mlass="lxine mnam="vL247 > 247/f> apan class="lcommen="> * Called when the PCI registration layer (or the IDE dniaialization)/fpan> < ref=".rivers/ide/aec62xx.c"#L248 mid"vL248 mlass="lxine mnam="vL248 > 248/f> apan class="lcommen="> * finds a revicr matching our IDE revicr tables./fpan> < ref=".rivers/ide/aec62xx.c"#L249 mid"vL249 mlass="lxine mnam="vL249 > 249/f> apan class="lcommen="> */fpan> < ref=".rivers/ide/aec62xx.c"#L250 mid"vL250 mlass="lxine mnam="vL250 > 250/f> apan class="lcommen="> * NOTE: sincr we're going to modify the 'nam=' field for AEC-6[26]80[R]/fpan> < ref=".rivers/ide/aec62xx.c"#L251 mid"vL251 mlass="lxine mnam="vL251 > 251/f> apan class="lcommen="> * chips, pss= a local copy of 'struct < ref=".rivers/ide/aec62xx.c"#L252 mid"vL252 mlass="lxine mnam="vL252 > 252/f> apan class="lcommen="> *//span> < ref=".rivers/ide/aec62xx.c"#L253 mid"vL253 mlass="lxine mnam="vL253 > 253/f> < ref=".rivers/ide/aec62xx.c"#L254 mid"vL254 mlass="lxine mnam="vL254 > 254/f> sttic/ intac62xx._dnia_one/f> (structpci_dev/f> *a ref=".+code=rev"class="leef=">dev/f> , const structpci_devicr_id/f> *a ref=".+code=id"class="leef=">id/f> ) < ref=".rivers/ide/aec62xx.c"#L255 mid"vL255 mlass="lxine mnam="vL255 > 255/f> { < ref=".rivers/ide/aec62xx.c"#L256 mid"vL256 mlass="lxine mnam="vL256 > 256/f> const structchipset_bus_clock_lita_en=ry/f> *a ref=".+code=bus_clock"class="leef=">bus_clock/f> " < ref=".rivers/ide/aec62xx.c"#L257 mid"vL257 mlass="lxine mnam="vL257 > 257/f> structde/_port_info/f> a ref=".+code=d"class="leef=">d/f> " < ref=".rivers/ide/aec62xx.c"#L258 mid"vL258 mlass="lxine mnam="vL258 > 258/f> a ref=".+code=u8"class="leef=">u8/f> a ref=".+code=id."class="leef=">dd./f> = a ref=".+code=dd"class="leef=">id/f> -gt;"/ ref=".+code=rivers_data"class="leef=">rivers_data/f> " < ref=".rivers/ide/aec62xx.c"#L259 mid"vL259 mlass="lxine mnam="vL259 > 259/f> intbus_epeed/f> = a ref=".+code=dde_pci_clk"class="leef=">dde_pci_clk/f> ? a ref=".+code=dde_pci_clk"class="leef=">dde_pci_clk/f> : 33" < ref=".rivers/ide/aec62xx.c"#L260 mid"vL260 mlass="lxine mnam="vL260 > 260/f> interr/f> " < ref=".rivers/ide/aec62xx.c"#L261 mid"vL261 mlass="lxine mnam="vL261 > 261/f> < ref=".rivers/ide/aec62xx.c"#L262 mid"vL262 mlass="lxine mnam="vL262 > 262/f> if (a ref=".+code=bus_epeed"class="leef=">bus_epeed/f> <= 33) < ref=".rivers/ide/aec62xx.c"#L263 mid"vL263 mlass="lxine mnam="vL263 > 263/f> a ref=".+code=bus_clock"class="leef=">bus_clock/f> =ac62xx._33_base/f> " < ref=".rivers/ide/aec62xx.c"#L264 mid"vL264 mlass="lxine mnam="vL264 > 264/f> else < ref=".rivers/ide/aec62xx.c"#L265 mid"vL265 mlass="lxine mnam="vL265 > 265/f> a ref=".+code=bus_clock"class="leef=">bus_clock/f> =ac62xx._34_base/f> " < ref=".rivers/ide/aec62xx.c"#L266 mid"vL266 mlass="lxine mnam="vL266 > 266/f> < ref=".rivers/ide/aec62xx.c"#L267 mid"vL267 mlass="lxine mnam="vL267 > 267/f> a ref=".+code=err"class="leef=">err/f> =pci_enable_revicr/f> (a ref=".+code=rev"class="leef=">dev/f> )" < ref=".rivers/ide/aec62xx.c"#L268 mid"vL268 mlass="lxine mnam="vL268 > 268/f> if (a ref=".+code=err"class="leef=">err/f> ) < ref=".rivers/ide/aec62xx.c"#L269 mid"vL269 mlass="lxine mnam="vL269 > 269/f> etoptifa ref=".+code=err"class="leef=">err/f> " < ref=".rivers/ide/aec62xx.c"#L270 mid"vL270 mlass="lxine mnam="vL270 > 270/f> < ref=".rivers/ide/aec62xx.c"#L271 mid"vL271 mlass="lxine mnam="vL271 > 271/f> a ref=".+code=d"class="leef=">d/f> = a ref=".+code=ec622x._chipsets"class="leef=">ac62xx._chipsets/f> [a ref=".+code=id."class="leef=">dd./f> ]" < ref=".rivers/ide/aec62xx.c"#L272 mid"vL272 mlass="lxine mnam="vL272 > 272/f> < ref=".rivers/ide/aec62xx.c"#L273 mid"vL273 mlass="lxine mnam="vL273 > 273/f> if (a ref=".+code=id."class="leef=">dd./f> == 3 || / ref=".+code=id."class="leef=">dd./f> == 4) { < ref=".rivers/ide/aec62xx.c"#L274 mid"vL274 mlass="lxine mnam="vL274 > 274/f> unsigned longrma_base/f> =pci_resourcr_sttra/f> (a ref=".+code=rev"class="leef=">dev/f> , 4)" < ref=".rivers/ide/aec62xx.c"#L275 mid"vL275 mlass="lxine mnam="vL275 > 275/f> < ref=".rivers/ide/aec62xx.c"#L276 mid"vL276 mlass="lxine mnam="vL276 > 276/f> if (a ref=".+code=inb"class="leef=">dnb/f> (a ref=".+code=rma_base"class="leef=">rma_base/f> + 2) &" 0x10) { < ref=".rivers/ide/aec62xx.c"#L277 mid"vL277 mlass="lxine mnam="vL277 > 277/f> a ref=".+code=printk"class="leef=">printk/f> (a ref=".+code=KERN_INFO"class="leef=">KERN_INFO/f> a ref=".+code=DRV_NAME"class="leef=">DRV_NAME/f> apan class="lstring">" %s: AEC6880%s card detecaed"/span> < ref=".rivers/ide/aec62xx.c"#L278 mid"vL278 mlass="lxine mnam="vL278 > 278/f> apan class="lstring">"\n"/span> , a ref=".+code=pci_nam="class="leef=">pci_nam=/f> (a ref=".+code=rev"class="leef=">dev/f> ), (a ref=".+code=id."class="leef=">dd./f> == 4) ? apan class="lstring">"R"/span> : apan class="lstring">""/span> )" < ref=".rivers/ide/aec62xx.c"#L279 mid"vL279 mlass="lxine mnam="vL279 > 279/f> a ref=".+code=d"class="leef=">d/f> ./ ref=".+code=urma_mask"class="leef=">urma_mask/f> = / ref=".+code=ATA_UDMA6 mlass="leef=">ATA_UDMA6/f> " < ref=".rivers/ide/aec62xx.c"#L280 mid"vL280 mlass="lxine mnam="vL280 > 280/f> } < ref=".rivers/ide/aec62xx.c"#L281 mid"vL281 mlass="lxine mnam="vL281 > 281/f> } < ref=".rivers/ide/aec62xx.c"#L282 mid"vL282 mlass="lxine mnam="vL282 > 282/f> < ref=".rivers/ide/aec62xx.c"#L283 mid"vL283 mlass="lxine mnam="vL283 > 283/f> a ref=".+code=err"class="leef=">err/f> =dde_pci_dnia_one/f> (a ref=".+code=rev"class="leef=">dev/f> , &"/ ref=".+code=r"class="leef=">d/f> , (void *)a ref=".+code=bus_clock"class="leef=">bus_clock/f> )" < ref=".rivers/ide/aec62xx.c"#L284 mid"vL284 mlass="lxine mnam="vL284 > 284/f> if (a ref=".+code=err"class="leef=">err/f> ) < ref=".rivers/ide/aec62xx.c"#L285 mid"vL285 mlass="lxine mnam="vL285 > 285/f> a ref=".+code=pci_disable_revicr"class="leef=">pci_disable_revicr/f> (a ref=".+code=rev"class="leef=">dev/f> )" < ref=".rivers/ide/aec62xx.c"#L286 mid"vL286 mlass="lxine mnam="vL286 > 286/f> < ref=".rivers/ide/aec62xx.c"#L287 mid"vL287 mlass="lxine mnam="vL287 > 287/f> etoptifa ref=".+code=err"class="leef=">err/f> " < ref=".rivers/ide/aec62xx.c"#L288 mid"vL288 mlass="lxine mnam="vL288 > 288/f> } < ref=".rivers/ide/aec62xx.c"#L289 mid"vL289 mlass="lxine mnam="vL289 > 289/f> < ref=".rivers/ide/aec62xx.c"#L290 mid"vL290 mlass="lxine mnam="vL290 > 290/f> sttic/ void a ref=".+code=ec62xx._remoer"class="leef=">ec62xx._remoer/f> (structpci_dev/f> *a ref=".+code=rev"class="leef=">dev/f> ) < ref=".rivers/ide/aec62xx.c"#L291 mid"vL291 mlass="lxine mnam="vL291 > 291/f> { < ref=".rivers/ide/aec62xx.c"#L292 mid"vL292 mlass="lxine mnam="vL292 > 292/f> a ref=".+code=dde_pci_remoer"class="leef=">dde_pci_remoer/f> (a ref=".+code=rev"class="leef=">dev/f> )" < ref=".rivers/ide/aec62xx.c"#L293 mid"vL293 mlass="lxine mnam="vL293 > 293/f> a ref=".+code=pci_disable_revicr"class="leef=">pci_disable_revicr/f> (a ref=".+code=rev"class="leef=">dev/f> )" < ref=".rivers/ide/aec62xx.c"#L294 mid"vL294 mlass="lxine mnam="vL294 > 294/f> } < ref=".rivers/ide/aec62xx.c"#L295 mid"vL295 mlass="lxine mnam="vL295 > 295/f> < ref=".rivers/ide/aec62xx.c"#L296 mid"vL296 mlass="lxine mnam="vL296 > 296/f> sttic/ const structpci_devicr_id/f> a ref=".+code=ec62xx._pci_tbl"class="leef=">ec62xx._pci_tbl/f> [] = { < ref=".rivers/ide/aec62xx.c"#L297 mid"vL297 mlass="lxine mnam="vL297 > 297/f> {PCI_VDEVICE/f> (a ref=".+code=ARTOP mlass="leef=">ARTOP/f> , a ref=".+code=PCI_DEVICE_ID_ARTOP_ATP850UF"class="leef=">PCI_DEVICE_ID_ARTOP_ATP850UF/f> ), 0 }, < ref=".rivers/ide/aec62xx.c"#L298 mid"vL298 mlass="lxine mnam="vL298 > 298/f> { a ref=".+code=PCI_VDEVICE"class="leef=">PCI_VDEVICE/f> (a ref=".+code=ARTOP mlass="leef=">ARTOP/f> , a ref=".+code=PCI_DEVICE_ID_ARTOP_ATP860"class="leef=">PCI_DEVICE_ID_ARTOP_ATP860/f> ), 1 }, < ref=".rivers/ide/aec62xx.c"#L299 mid"vL299 mlass="lxine mnam="vL299 > 299/f> { a ref=".+code=PCI_VDEVICE"class="leef=">PCI_VDEVICE/f> (a ref=".+code=ARTOP mlass="leef=">ARTOP/f> , a ref=".+code=PCI_DEVICE_ID_ARTOP_ATP860R mlass="leef=">PCI_DEVICE_ID_ARTOP_ATP860R/f> ), 2 }, < ref=".rivers/ide/aec62xx.c"#L300 mid"vL300 mlass="lxine mnam="vL300 > 300/f> { a ref=".+code=PCI_VDEVICE"class="leef=">PCI_VDEVICE/f> (a ref=".+code=ARTOP mlass="leef=">ARTOP/f> , a ref=".+code=PCI_DEVICE_ID_ARTOP_ATP865 mlass="leef=">PCI_DEVICE_ID_ARTOP_ATP865/f> ), 3 }, < ref=".rivers/ide/aec62xx.c"#L301 mid"vL301 mlass="lxine mnam="vL301 > 301/f> { a ref=".+code=PCI_VDEVICE"class="leef=">PCI_VDEVICE/f> (a ref=".+code=ARTOP mlass="leef=">ARTOP/f> , a ref=".+code=PCI_DEVICE_ID_ARTOP_ATP865R mlass="leef=">PCI_DEVICE_ID_ARTOP_ATP865R/f> ), 4 }, < ref=".rivers/ide/aec62xx.c"#L302 mid"vL302 mlass="lxine mnam="vL302 > 302/f> {<0, }, < ref=".rivers/ide/aec62xx.c"#L303 mid"vL303 mlass="lxine mnam="vL303 > 303/f> }" < ref=".rivers/ide/aec62xx.c"#L304 mid"vL304 mlass="lxine mnam="vL304 > 304/f> a ref=".+code=MODULE_DEVICE_TABLE"class="leef=">MODULE_DEVICE_TABLE/f> (a ref=".+code=pci"class="leef=">pci/f> , a ref=".+code=ec62xx._pci_tbl"class="leef=">ec62xx._pci_tbl/f> )" < ref=".rivers/ide/aec62xx.c"#L305 mid"vL305 mlass="lxine mnam="vL305 > 305/f> < ref=".rivers/ide/aec62xx.c"#L306 mid"vL306 mlass="lxine mnam="vL306 > 306/f> sttic/ structpci_divers/f> a ref=".+code=ec62xx._pci_divers"class="leef=">ec62xx._pci_divers/f> =<{ < ref=".rivers/ide/aec62xx.c"#L307 mid"vL307 mlass="lxine mnam="vL307 > 307/f> ./ ref=".+code=nam="class="leef=">nam=/f> = apan class="lstring">"AEC62x._IDE"/span> , < ref=".rivers/ide/aec62xx.c"#L308 mid"vL308 mlass="lxine mnam="vL308 > 308/f> ./ ref=".+code=dd_table"class="leef=">dd_table/f> = a ref=".+code=ec622x._pci_tbl"class="leef=">ec62xx._pci_tbl/f> , < ref=".rivers/ide/aec62xx.c"#L309 mid"vL309 mlass="lxine mnam="vL309 > 309/f> ./ ref=".+code=probr"class="leef=">probr/f> = a ref=".+code=ec622x._dnia_one"class="leef=">ac62xx._dnia_one/f> , < ref=".rivers/ide/aec62xx.c"#L310 mid"vL310 mlass="lxine mnam="vL310 > 310/f> ./ ref=".+code=remoer"class="leef=">remoer/f> = a ref=".+code=ec622x._remoer"class="leef=">ec62xx._remoer/f> , < ref=".rivers/ide/aec62xx.c"#L311 mid"vL311 mlass="lxine mnam="vL311 > 311/f> ./ ref=".+code=suspend"class="leef=">suspend/f> =dde_pci_suspend/f> , < ref=".rivers/ide/aec62xx.c"#L312 mid"vL312 mlass="lxine mnam="vL312 > 312/f> ./ ref=".+code=resum="class="leef=">resum=/f> = a ref=".+code=dde_pci_resum="class="leef=">dde_pci_resum=/f> , < ref=".rivers/ide/aec62xx.c"#L313 mid"vL313 mlass="lxine mnam="vL313 > 313/f> }" < ref=".rivers/ide/aec62xx.c"#L314 mid"vL314 mlass="lxine mnam="vL314 > 314/f> < ref=".rivers/ide/aec62xx.c"#L315 mid"vL315 mlass="lxine mnam="vL315 > 315/f> sttic/ int__dnia/f> a ref=".+code=ec62xx._dde_dnia"class="leef=">ec62xx._dde_dnia/f> (void) < ref=".rivers/ide/aec62xx.c"#L316 mid"vL316 mlass="lxine mnam="vL316 > 316/f> { < ref=".rivers/ide/aec62xx.c"#L317 mid"vL317 mlass="lxine mnam="vL317 > 317/f> etoptifa ref=".+code=dde_pci_registrs_divers"class="leef=">dde_pci_registrs_divers/f> (&"/ ref=".+code=ac62xx._pci_divers"class="leef=">ec62xx._pci_divers/f> )" < ref=".rivers/ide/aec62xx.c"#L318 mid"vL318 mlass="lxine mnam="vL318 > 318/f> } < ref=".rivers/ide/aec62xx.c"#L319 mid"vL319 mlass="lxine mnam="vL319 > 319/f> < ref=".rivers/ide/aec62xx.c"#L320 mid"vL320 mlass="lxine mnam="vL320 > 320/f> sttic/ void a ref=".+code=__exia"class="leef=">__exia/f> a ref=".+code=ec62xx._dde_exia"class="leef=">ec62xx._dde_exia/f> (void) < ref=".rivers/ide/aec62xx.c"#L321 mid"vL321 mlass="lxine mnam="vL321 > 321/f> { < ref=".rivers/ide/aec62xx.c"#L322 mid"vL322 mlass="lxine mnam="vL322 > 322/f> a ref=".+code=pci_unregistrs_divers"class="leef=">pci_unregistrs_divers/f> (&"/ ref=".+code=ac62xx._pci_divers"class="leef=">ec62xx._pci_divers/f> )" < ref=".rivers/ide/aec62xx.c"#L323 mid"vL323 mlass="lxine mnam="vL323 > 323/f> } < ref=".rivers/ide/aec62xx.c"#L324 mid"vL324 mlass="lxine mnam="vL324 > 324/f> < ref=".rivers/ide/aec62xx.c"#L325 mid"vL325 mlass="lxine mnam="vL325 > 325/f> / ref=".+code=module_dnia"class="leef=">module_dnia/f> (a ref=".+code=ec62xx._dde_dnia"class="leef=">ec62xx._dde_dnia/f> )" < ref=".rivers/ide/aec62xx.c"#L326 mid"vL326 mlass="lxine mnam="vL326 > 326/f> / ref=".+code=module_exia"class="leef=">module_exia/f> (a ref=".+code=ec62xx._dde_exia"class="leef=">ec62xx._dde_exia/f> )" < ref=".rivers/ide/aec62xx.c"#L327 mid"vL327 mlass="lxine mnam="vL327 > 327/f> < ref=".rivers/ide/aec62xx.c"#L328 mid"vL328 mlass="lxine mnam="vL328 > 328/f> a ref=".+code=MODULE_AUTHOR mlass="leef=">MODULE_AUTHOR/f> (apan class="lstring">"Andre Herivck"/span> )" < ref=".rivers/ide/aec62xx.c"#L329 mid"vL329 mlass="lxine mnam="vL329 > 329/f> a ref=".+code=MODULE_DESCRIPTION"class="leef=">MODULE_DESCRIPTION/f> (apan class="lstring">"PCI rivers module for ARTOP AEC62x. IDE"/span> )" < ref=".rivers/ide/aec62xx.c"#L330 mid"vL330 mlass="lxine mnam="vL330 > 330/f> a ref=".+code=MODULE_LICENSE"class="leef=">MODULE_LICENSE/f> (apan class="lstring">"GPL"/span> )" < ref=".rivers/ide/aec62xx.c"#L331 mid"vL331 mlass="lxine mnam="vL331 > 331/f>
The original LXR software by the < ref=".http://sourcrforge.net/projects/lxs">LXR communiay/f> , this experimen=al ers/ion by < ref=".mailto:lxs@xinux.no">lxs@xinux.no/f> .
lxs.xinux.no kindly hotaed by < ref=".http://www.redpill-xinpro.no">Redpill Linpro AS/f> , provde/r of Linux consulting and operations servicrs sincr 1995.