linux/drivers/gpio/gpio-tegra.c
<<
>>
Prefs
   1/*
   2 * arch/arm/mach-tegra/gpio.c
   3 *
   4 * Copyright (c) 2010 Google, Inc
   5 *
   6 * Author:
   7 *      Erik Gilling <konkers@google.com>
   8 *
   9 * This software is licensed under the terms of the GNU General Public
  10 * License version 2, as published by the Free Software Foundation, and
  11 * may be copied, distributed, and modified under those terms.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 */
  19
  20#include <linux/err.h>
  21#include <linux/init.h>
  22#include <linux/irq.h>
  23#include <linux/interrupt.h>
  24#include <linux/io.h>
  25#include <linux/gpio.h>
  26#include <linux/of_device.h>
  27#include <linux/platform_device.h>
  28#include <linux/module.h>
  29#include <linux/irqdomain.h>
  30#include <linux/irqchip/chained_irq.h>
  31#include <linux/pinctrl/consumer.h>
  32#include <linux/pm.h>
  33
  34#define GPIO_BANK(x)            ((x) >> 5)
  35#define GPIO_PORT(x)            (((x) >> 3) & 0x3)
  36#define GPIO_BIT(x)             ((x) & 0x7)
  37
  38#define GPIO_REG(x)             (GPIO_BANK(x) * tegra_gpio_bank_stride + \
  39                                        GPIO_PORT(x) * 4)
  40
  41#define GPIO_CNF(x)             (GPIO_REG(x) + 0x00)
  42#define GPIO_OE(x)              (GPIO_REG(x) + 0x10)
  43#define GPIO_OUT(x)             (GPIO_REG(x) + 0X20)
  44#define GPIO_IN(x)              (GPIO_REG(x) + 0x30)
  45#define GPIO_INT_STA(x)         (GPIO_REG(x) + 0x40)
  46#define GPIO_INT_ENB(x)         (GPIO_REG(x) + 0x50)
  47#define GPIO_INT_LVL(x)         (GPIO_REG(x) + 0x60)
  48#define GPIO_INT_CLR(x)         (GPIO_REG(x) + 0x70)
  49
  50#define GPIO_MSK_CNF(x)         (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
  51#define GPIO_MSK_OE(x)          (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
  52#define GPIO_MSK_OUT(x)         (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
  53#define GPIO_MSK_INT_STA(x)     (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
  54#define GPIO_MSK_INT_ENB(x)     (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
  55#define GPIO_MSK_INT_LVL(x)     (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
  56
  57#define GPIO_INT_LVL_MASK               0x010101
  58#define GPIO_INT_LVL_EDGE_RISING        0x000101
  59#define GPIO_INT_LVL_EDGE_FALLING       0x000100
  60#define GPIO_INT_LVL_EDGE_BOTH          0x010100
  61#define GPIO_INT_LVL_LEVEL_HIGH         0x000001
  62#define GPIO_INT_LVL_LEVEL_LOW          0x000000
  63
  64struct tegra_gpio_bank {
  65        int bank;
  66        int irq;
  67        spinlock_t lvl_lock[4];
  68#ifdef CONFIG_PM_SLEEP
  69        u32 cnf[4];
  70        u32 out[4];
  71        u32 oe[4];
  72        u32 int_enb[4];
  73        u32 int_lvl[4];
  74        u32 wake_enb[4];
  75#endif
  76};
  77
  78static struct irq_domain *irq_domain;
  79static void __iomem *regs;
  80static u32 tegra_gpio_bank_count;
  81static u32 tegra_gpio_bank_stride;
  82static u32 tegra_gpio_upper_offset;
  83static struct tegra_gpio_bank *tegra_gpio_banks;
  84
  85static inline void tegra_gpio_writel(u32 val, u32 reg)
  86{
  87        __raw_writel(val, regs + reg);
  88}
  89
  90static inline u32 tegra_gpio_readl(u32 reg)
  91{
  92        return __raw_readl(regs + reg);
  93}
  94
  95static int tegra_gpio_compose(int bank, int port, int bit)
  96{
  97        return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
  98}
  99
 100static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
 101{
 102        u32 val;
 103
 104        val = 0x100 << GPIO_BIT(gpio);
 105        if (value)
 106                val |= 1 << GPIO_BIT(gpio);
 107        tegra_gpio_writel(val, reg);
 108}
 109
 110static void tegra_gpio_enable(int gpio)
 111{
 112        tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
 113}
 114
 115static void tegra_gpio_disable(int gpio)
 116{
 117        tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
 118}
 119
 120static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
 121{
 122        return pinctrl_request_gpio(offset);
 123}
 124
 125static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
 126{
 127        pinctrl_free_gpio(offset);
 128        tegra_gpio_disable(offset);
 129}
 130
 131static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 132{
 133        tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
 134}
 135
 136static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
 137{
 138        /* If gpio is in output mode then read from the out value */
 139        if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1)
 140                return (tegra_gpio_readl(GPIO_OUT(offset)) >>
 141                                GPIO_BIT(offset)) & 0x1;
 142
 143        return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
 144}
 145
 146static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 147{
 148        tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
 149        tegra_gpio_enable(offset);
 150        return 0;
 151}
 152
 153static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 154                                        int value)
 155{
 156        tegra_gpio_set(chip, offset, value);
 157        tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
 158        tegra_gpio_enable(offset);
 159        return 0;
 160}
 161
 162static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 163{
 164        return irq_find_mapping(irq_domain, offset);
 165}
 166
 167static struct gpio_chip tegra_gpio_chip = {
 168        .label                  = "tegra-gpio",
 169        .request                = tegra_gpio_request,
 170        .free                   = tegra_gpio_free,
 171        .direction_input        = tegra_gpio_direction_input,
 172        .get                    = tegra_gpio_get,
 173        .direction_output       = tegra_gpio_direction_output,
 174        .set                    = tegra_gpio_set,
 175        .to_irq                 = tegra_gpio_to_irq,
 176        .base                   = 0,
 177};
 178
 179static void tegra_gpio_irq_ack(struct irq_data *d)
 180{
 181        int gpio = d->hwirq;
 182
 183        tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
 184}
 185
 186static void tegra_gpio_irq_mask(struct irq_data *d)
 187{
 188        int gpio = d->hwirq;
 189
 190        tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
 191}
 192
 193static void tegra_gpio_irq_unmask(struct irq_data *d)
 194{
 195        int gpio = d->hwirq;
 196
 197        tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
 198}
 199
 200static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 201{
 202        int gpio = d->hwirq;
 203        struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 204        int port = GPIO_PORT(gpio);
 205        int lvl_type;
 206        int val;
 207        unsigned long flags;
 208
 209        switch (type & IRQ_TYPE_SENSE_MASK) {
 210        case IRQ_TYPE_EDGE_RISING:
 211                lvl_type = GPIO_INT_LVL_EDGE_RISING;
 212                break;
 213
 214        case IRQ_TYPE_EDGE_FALLING:
 215                lvl_type = GPIO_INT_LVL_EDGE_FALLING;
 216                break;
 217
 218        case IRQ_TYPE_EDGE_BOTH:
 219                lvl_type = GPIO_INT_LVL_EDGE_BOTH;
 220                break;
 221
 222        case IRQ_TYPE_LEVEL_HIGH:
 223                lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
 224                break;
 225
 226        case IRQ_TYPE_LEVEL_LOW:
 227                lvl_type = GPIO_INT_LVL_LEVEL_LOW;
 228                break;
 229
 230        default:
 231                return -EINVAL;
 232        }
 233
 234        spin_lock_irqsave(&bank->lvl_lock[port], flags);
 235
 236        val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
 237        val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
 238        val |= lvl_type << GPIO_BIT(gpio);
 239        tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
 240
 241        spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
 242
 243        tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
 244        tegra_gpio_enable(gpio);
 245
 246        if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 247                __irq_set_handler_locked(d->irq, handle_level_irq);
 248        else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 249                __irq_set_handler_locked(d->irq, handle_edge_irq);
 250
 251        return 0;
 252}
 253
 254static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 255{
 256        struct tegra_gpio_bank *bank;
 257        int port;
 258        int pin;
 259        int unmasked = 0;
 260        struct irq_chip *chip = irq_desc_get_chip(desc);
 261
 262        chained_irq_enter(chip, desc);
 263
 264        bank = irq_get_handler_data(irq);
 265
 266        for (port = 0; port < 4; port++) {
 267                int gpio = tegra_gpio_compose(bank->bank, port, 0);
 268                unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
 269                        tegra_gpio_readl(GPIO_INT_ENB(gpio));
 270                u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
 271
 272                for_each_set_bit(pin, &sta, 8) {
 273                        tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
 274
 275                        /* if gpio is edge triggered, clear condition
 276                         * before executing the hander so that we don't
 277                         * miss edges
 278                         */
 279                        if (lvl & (0x100 << pin)) {
 280                                unmasked = 1;
 281                                chained_irq_exit(chip, desc);
 282                        }
 283
 284                        generic_handle_irq(gpio_to_irq(gpio + pin));
 285                }
 286        }
 287
 288        if (!unmasked)
 289                chained_irq_exit(chip, desc);
 290
 291}
 292
 293#ifdef CONFIG_PM_SLEEP
 294static int tegra_gpio_resume(struct device *dev)
 295{
 296        unsigned long flags;
 297        int b;
 298        int p;
 299
 300        local_irq_save(flags);
 301
 302        for (b = 0; b < tegra_gpio_bank_count; b++) {
 303                struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
 304
 305                for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 306                        unsigned int gpio = (b<<5) | (p<<3);
 307                        tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
 308                        tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
 309                        tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
 310                        tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
 311                        tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
 312                }
 313        }
 314
 315        local_irq_restore(flags);
 316        return 0;
 317}
 318
 319static int tegra_gpio_suspend(struct device *dev)
 320{
 321        unsigned long flags;
 322        int b;
 323        int p;
 324
 325        local_irq_save(flags);
 326        for (b = 0; b < tegra_gpio_bank_count; b++) {
 327                struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
 328
 329                for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 330                        unsigned int gpio = (b<<5) | (p<<3);
 331                        bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
 332                        bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
 333                        bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
 334                        bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
 335                        bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
 336
 337                        /* Enable gpio irq for wake up source */
 338                        tegra_gpio_writel(bank->wake_enb[p],
 339                                          GPIO_INT_ENB(gpio));
 340                }
 341        }
 342        local_irq_restore(flags);
 343        return 0;
 344}
 345
 346static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
 347{
 348        struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 349        int gpio = d->hwirq;
 350        u32 port, bit, mask;
 351
 352        port = GPIO_PORT(gpio);
 353        bit = GPIO_BIT(gpio);
 354        mask = BIT(bit);
 355
 356        if (enable)
 357                bank->wake_enb[port] |= mask;
 358        else
 359                bank->wake_enb[port] &= ~mask;
 360
 361        return irq_set_irq_wake(bank->irq, enable);
 362}
 363#endif
 364
 365static struct irq_chip tegra_gpio_irq_chip = {
 366        .name           = "GPIO",
 367        .irq_ack        = tegra_gpio_irq_ack,
 368        .irq_mask       = tegra_gpio_irq_mask,
 369        .irq_unmask     = tegra_gpio_irq_unmask,
 370        .irq_set_type   = tegra_gpio_irq_set_type,
 371#ifdef CONFIG_PM_SLEEP
 372        .irq_set_wake   = tegra_gpio_irq_set_wake,
 373#endif
 374};
 375
 376static const struct dev_pm_ops tegra_gpio_pm_ops = {
 377        SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
 378};
 379
 380struct tegra_gpio_soc_config {
 381        u32 bank_stride;
 382        u32 upper_offset;
 383};
 384
 385static struct tegra_gpio_soc_config tegra20_gpio_config = {
 386        .bank_stride = 0x80,
 387        .upper_offset = 0x800,
 388};
 389
 390static struct tegra_gpio_soc_config tegra30_gpio_config = {
 391        .bank_stride = 0x100,
 392        .upper_offset = 0x80,
 393};
 394
 395static struct of_device_id tegra_gpio_of_match[] = {
 396        { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
 397        { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
 398        { },
 399};
 400
 401/* This lock class tells lockdep that GPIO irqs are in a different
 402 * category than their parents, so it won't report false recursion.
 403 */
 404static struct lock_class_key gpio_lock_class;
 405
 406static int tegra_gpio_probe(struct platform_device *pdev)
 407{
 408        const struct of_device_id *match;
 409        struct tegra_gpio_soc_config *config;
 410        struct resource *res;
 411        struct tegra_gpio_bank *bank;
 412        int gpio;
 413        int i;
 414        int j;
 415
 416        match = of_match_device(tegra_gpio_of_match, &pdev->dev);
 417        if (!match) {
 418                dev_err(&pdev->dev, "Error: No device match found\n");
 419                return -ENODEV;
 420        }
 421        config = (struct tegra_gpio_soc_config *)match->data;
 422
 423        tegra_gpio_bank_stride = config->bank_stride;
 424        tegra_gpio_upper_offset = config->upper_offset;
 425
 426        for (;;) {
 427                res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
 428                if (!res)
 429                        break;
 430                tegra_gpio_bank_count++;
 431        }
 432        if (!tegra_gpio_bank_count) {
 433                dev_err(&pdev->dev, "Missing IRQ resource\n");
 434                return -ENODEV;
 435        }
 436
 437        tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
 438
 439        tegra_gpio_banks = devm_kzalloc(&pdev->dev,
 440                        tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
 441                        GFP_KERNEL);
 442        if (!tegra_gpio_banks) {
 443                dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
 444                return -ENODEV;
 445        }
 446
 447        irq_domain = irq_domain_add_linear(pdev->dev.of_node,
 448                                           tegra_gpio_chip.ngpio,
 449                                           &irq_domain_simple_ops, NULL);
 450        if (!irq_domain)
 451                return -ENODEV;
 452
 453        for (i = 0; i < tegra_gpio_bank_count; i++) {
 454                res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
 455                if (!res) {
 456                        dev_err(&pdev->dev, "Missing IRQ resource\n");
 457                        return -ENODEV;
 458                }
 459
 460                bank = &tegra_gpio_banks[i];
 461                bank->bank = i;
 462                bank->irq = res->start;
 463        }
 464
 465        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 466        regs = devm_ioremap_resource(&pdev->dev, res);
 467        if (IS_ERR(regs))
 468                return PTR_ERR(regs);
 469
 470        for (i = 0; i < tegra_gpio_bank_count; i++) {
 471                for (j = 0; j < 4; j++) {
 472                        int gpio = tegra_gpio_compose(i, j, 0);
 473                        tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
 474                }
 475        }
 476
 477        tegra_gpio_chip.of_node = pdev->dev.of_node;
 478
 479        gpiochip_add(&tegra_gpio_chip);
 480
 481        for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
 482                int irq = irq_create_mapping(irq_domain, gpio);
 483                /* No validity check; all Tegra GPIOs are valid IRQs */
 484
 485                bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
 486
 487                irq_set_lockdep_class(irq, &gpio_lock_class);
 488                irq_set_chip_data(irq, bank);
 489                irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
 490                                         handle_simple_irq);
 491                set_irq_flags(irq, IRQF_VALID);
 492        }
 493
 494        for (i = 0; i < tegra_gpio_bank_count; i++) {
 495                bank = &tegra_gpio_banks[i];
 496
 497                irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
 498                irq_set_handler_data(bank->irq, bank);
 499
 500                for (j = 0; j < 4; j++)
 501                        spin_lock_init(&bank->lvl_lock[j]);
 502        }
 503
 504        return 0;
 505}
 506
 507static struct platform_driver tegra_gpio_driver = {
 508        .driver         = {
 509                .name   = "tegra-gpio",
 510                .owner  = THIS_MODULE,
 511                .pm     = &tegra_gpio_pm_ops,
 512                .of_match_table = tegra_gpio_of_match,
 513        },
 514        .probe          = tegra_gpio_probe,
 515};
 516
 517static int __init tegra_gpio_init(void)
 518{
 519        return platform_driver_register(&tegra_gpio_driver);
 520}
 521postcore_initcall(tegra_gpio_init);
 522
 523#ifdef  CONFIG_DEBUG_FS
 524
 525#include <linux/debugfs.h>
 526#include <linux/seq_file.h>
 527
 528static int dbg_gpio_show(struct seq_file *s, void *unused)
 529{
 530        int i;
 531        int j;
 532
 533        for (i = 0; i < tegra_gpio_bank_count; i++) {
 534                for (j = 0; j < 4; j++) {
 535                        int gpio = tegra_gpio_compose(i, j, 0);
 536                        seq_printf(s,
 537                                "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
 538                                i, j,
 539                                tegra_gpio_readl(GPIO_CNF(gpio)),
 540                                tegra_gpio_readl(GPIO_OE(gpio)),
 541                                tegra_gpio_readl(GPIO_OUT(gpio)),
 542                                tegra_gpio_readl(GPIO_IN(gpio)),
 543                                tegra_gpio_readl(GPIO_INT_STA(gpio)),
 544                                tegra_gpio_readl(GPIO_INT_ENB(gpio)),
 545                                tegra_gpio_readl(GPIO_INT_LVL(gpio)));
 546                }
 547        }
 548        return 0;
 549}
 550
 551static int dbg_gpio_open(struct inode *inode, struct file *file)
 552{
 553        return single_open(file, dbg_gpio_show, &inode->i_private);
 554}
 555
 556static const struct file_operations debug_fops = {
 557        .open           = dbg_gpio_open,
 558        .read           = seq_read,
 559        .llseek         = seq_lseek,
 560        .release        = single_release,
 561};
 562
 563static int __init tegra_gpio_debuginit(void)
 564{
 565        (void) debugfs_create_file("tegra_gpio", S_IRUGO,
 566                                        NULL, NULL, &debug_fops);
 567        return 0;
 568}
 569late_initcall(tegra_gpio_debuginit);
 570#endif
 571
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.