linux/drivers/gpio/gpio-em.c
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   1/*
   2 * Emma Mobile GPIO Support - GIO
   3 *
   4 *  Copyright (C) 2012 Magnus Damm
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18 */
  19
  20#include <linux/init.h>
  21#include <linux/platform_device.h>
  22#include <linux/spinlock.h>
  23#include <linux/interrupt.h>
  24#include <linux/ioport.h>
  25#include <linux/io.h>
  26#include <linux/irq.h>
  27#include <linux/irqdomain.h>
  28#include <linux/bitops.h>
  29#include <linux/err.h>
  30#include <linux/gpio.h>
  31#include <linux/slab.h>
  32#include <linux/module.h>
  33#include <linux/pinctrl/consumer.h>
  34#include <linux/platform_data/gpio-em.h>
  35
  36struct em_gio_priv {
  37        void __iomem *base0;
  38        void __iomem *base1;
  39        spinlock_t sense_lock;
  40        struct platform_device *pdev;
  41        struct gpio_chip gpio_chip;
  42        struct irq_chip irq_chip;
  43        struct irq_domain *irq_domain;
  44};
  45
  46#define GIO_E1 0x00
  47#define GIO_E0 0x04
  48#define GIO_EM 0x04
  49#define GIO_OL 0x08
  50#define GIO_OH 0x0c
  51#define GIO_I 0x10
  52#define GIO_IIA 0x14
  53#define GIO_IEN 0x18
  54#define GIO_IDS 0x1c
  55#define GIO_IIM 0x1c
  56#define GIO_RAW 0x20
  57#define GIO_MST 0x24
  58#define GIO_IIR 0x28
  59
  60#define GIO_IDT0 0x40
  61#define GIO_IDT1 0x44
  62#define GIO_IDT2 0x48
  63#define GIO_IDT3 0x4c
  64#define GIO_RAWBL 0x50
  65#define GIO_RAWBH 0x54
  66#define GIO_IRBL 0x58
  67#define GIO_IRBH 0x5c
  68
  69#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
  70
  71static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
  72{
  73        if (offs < GIO_IDT0)
  74                return ioread32(p->base0 + offs);
  75        else
  76                return ioread32(p->base1 + (offs - GIO_IDT0));
  77}
  78
  79static inline void em_gio_write(struct em_gio_priv *p, int offs,
  80                                unsigned long value)
  81{
  82        if (offs < GIO_IDT0)
  83                iowrite32(value, p->base0 + offs);
  84        else
  85                iowrite32(value, p->base1 + (offs - GIO_IDT0));
  86}
  87
  88static void em_gio_irq_disable(struct irq_data *d)
  89{
  90        struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  91
  92        em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
  93}
  94
  95static void em_gio_irq_enable(struct irq_data *d)
  96{
  97        struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  98
  99        em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
 100}
 101
 102#define GIO_ASYNC(x) (x + 8)
 103
 104static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
 105        [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
 106        [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
 107        [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
 108        [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
 109        [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
 110};
 111
 112static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
 113{
 114        unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
 115        struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
 116        unsigned int reg, offset, shift;
 117        unsigned long flags;
 118        unsigned long tmp;
 119
 120        if (!value)
 121                return -EINVAL;
 122
 123        offset = irqd_to_hwirq(d);
 124
 125        pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
 126
 127        /* 8 x 4 bit fields in 4 IDT registers */
 128        reg = GIO_IDT(offset >> 3);
 129        shift = (offset & 0x07) << 4;
 130
 131        spin_lock_irqsave(&p->sense_lock, flags);
 132
 133        /* disable the interrupt in IIA */
 134        tmp = em_gio_read(p, GIO_IIA);
 135        tmp &= ~BIT(offset);
 136        em_gio_write(p, GIO_IIA, tmp);
 137
 138        /* change the sense setting in IDT */
 139        tmp = em_gio_read(p, reg);
 140        tmp &= ~(0xf << shift);
 141        tmp |= value << shift;
 142        em_gio_write(p, reg, tmp);
 143
 144        /* clear pending interrupts */
 145        em_gio_write(p, GIO_IIR, BIT(offset));
 146
 147        /* enable the interrupt in IIA */
 148        tmp = em_gio_read(p, GIO_IIA);
 149        tmp |= BIT(offset);
 150        em_gio_write(p, GIO_IIA, tmp);
 151
 152        spin_unlock_irqrestore(&p->sense_lock, flags);
 153
 154        return 0;
 155}
 156
 157static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
 158{
 159        struct em_gio_priv *p = dev_id;
 160        unsigned long pending;
 161        unsigned int offset, irqs_handled = 0;
 162
 163        while ((pending = em_gio_read(p, GIO_MST))) {
 164                offset = __ffs(pending);
 165                em_gio_write(p, GIO_IIR, BIT(offset));
 166                generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
 167                irqs_handled++;
 168        }
 169
 170        return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
 171}
 172
 173static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
 174{
 175        return container_of(chip, struct em_gio_priv, gpio_chip);
 176}
 177
 178static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
 179{
 180        em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
 181        return 0;
 182}
 183
 184static int em_gio_get(struct gpio_chip *chip, unsigned offset)
 185{
 186        return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
 187}
 188
 189static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
 190                         unsigned shift, int value)
 191{
 192        /* upper 16 bits contains mask and lower 16 actual value */
 193        em_gio_write(gpio_to_priv(chip), reg,
 194                     (1 << (shift + 16)) | (value << shift));
 195}
 196
 197static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
 198{
 199        /* output is split into two registers */
 200        if (offset < 16)
 201                __em_gio_set(chip, GIO_OL, offset, value);
 202        else
 203                __em_gio_set(chip, GIO_OH, offset - 16, value);
 204}
 205
 206static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
 207                                   int value)
 208{
 209        /* write GPIO value to output before selecting output mode of pin */
 210        em_gio_set(chip, offset, value);
 211        em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
 212        return 0;
 213}
 214
 215static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
 216{
 217        return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
 218}
 219
 220static int em_gio_request(struct gpio_chip *chip, unsigned offset)
 221{
 222        return pinctrl_request_gpio(chip->base + offset);
 223}
 224
 225static void em_gio_free(struct gpio_chip *chip, unsigned offset)
 226{
 227        pinctrl_free_gpio(chip->base + offset);
 228
 229        /* Set the GPIO as an input to ensure that the next GPIO request won't
 230        * drive the GPIO pin as an output.
 231        */
 232        em_gio_direction_input(chip, offset);
 233}
 234
 235static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int virq,
 236                                 irq_hw_number_t hw)
 237{
 238        struct em_gio_priv *p = h->host_data;
 239
 240        pr_debug("gio: map hw irq = %d, virq = %d\n", (int)hw, virq);
 241
 242        irq_set_chip_data(virq, h->host_data);
 243        irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
 244        set_irq_flags(virq, IRQF_VALID); /* kill me now */
 245        return 0;
 246}
 247
 248static struct irq_domain_ops em_gio_irq_domain_ops = {
 249        .map    = em_gio_irq_domain_map,
 250        .xlate  = irq_domain_xlate_twocell,
 251};
 252
 253static int em_gio_probe(struct platform_device *pdev)
 254{
 255        struct gpio_em_config pdata_dt;
 256        struct gpio_em_config *pdata = dev_get_platdata(&pdev->dev);
 257        struct em_gio_priv *p;
 258        struct resource *io[2], *irq[2];
 259        struct gpio_chip *gpio_chip;
 260        struct irq_chip *irq_chip;
 261        const char *name = dev_name(&pdev->dev);
 262        int ret;
 263
 264        p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
 265        if (!p) {
 266                dev_err(&pdev->dev, "failed to allocate driver data\n");
 267                ret = -ENOMEM;
 268                goto err0;
 269        }
 270
 271        p->pdev = pdev;
 272        platform_set_drvdata(pdev, p);
 273        spin_lock_init(&p->sense_lock);
 274
 275        io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 276        io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 277        irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 278        irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 279
 280        if (!io[0] || !io[1] || !irq[0] || !irq[1]) {
 281                dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
 282                ret = -EINVAL;
 283                goto err0;
 284        }
 285
 286        p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start,
 287                                        resource_size(io[0]));
 288        if (!p->base0) {
 289                dev_err(&pdev->dev, "failed to remap low I/O memory\n");
 290                ret = -ENXIO;
 291                goto err0;
 292        }
 293
 294        p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start,
 295                                   resource_size(io[1]));
 296        if (!p->base1) {
 297                dev_err(&pdev->dev, "failed to remap high I/O memory\n");
 298                ret = -ENXIO;
 299                goto err0;
 300        }
 301
 302        if (!pdata) {
 303                memset(&pdata_dt, 0, sizeof(pdata_dt));
 304                pdata = &pdata_dt;
 305
 306                if (of_property_read_u32(pdev->dev.of_node, "ngpios",
 307                                         &pdata->number_of_pins)) {
 308                        dev_err(&pdev->dev, "Missing ngpios OF property\n");
 309                        ret = -EINVAL;
 310                        goto err0;
 311                }
 312
 313                ret = of_alias_get_id(pdev->dev.of_node, "gpio");
 314                if (ret < 0) {
 315                        dev_err(&pdev->dev, "Couldn't get OF id\n");
 316                        goto err0;
 317                }
 318                pdata->gpio_base = ret * 32; /* 32 GPIOs per instance */
 319        }
 320
 321        gpio_chip = &p->gpio_chip;
 322        gpio_chip->direction_input = em_gio_direction_input;
 323        gpio_chip->get = em_gio_get;
 324        gpio_chip->direction_output = em_gio_direction_output;
 325        gpio_chip->set = em_gio_set;
 326        gpio_chip->to_irq = em_gio_to_irq;
 327        gpio_chip->request = em_gio_request;
 328        gpio_chip->free = em_gio_free;
 329        gpio_chip->label = name;
 330        gpio_chip->owner = THIS_MODULE;
 331        gpio_chip->base = pdata->gpio_base;
 332        gpio_chip->ngpio = pdata->number_of_pins;
 333
 334        irq_chip = &p->irq_chip;
 335        irq_chip->name = name;
 336        irq_chip->irq_mask = em_gio_irq_disable;
 337        irq_chip->irq_unmask = em_gio_irq_enable;
 338        irq_chip->irq_enable = em_gio_irq_enable;
 339        irq_chip->irq_disable = em_gio_irq_disable;
 340        irq_chip->irq_set_type = em_gio_irq_set_type;
 341        irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
 342
 343        p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
 344                                              pdata->number_of_pins,
 345                                              pdata->irq_base,
 346                                              &em_gio_irq_domain_ops, p);
 347        if (!p->irq_domain) {
 348                ret = -ENXIO;
 349                dev_err(&pdev->dev, "cannot initialize irq domain\n");
 350                goto err0;
 351        }
 352
 353        if (devm_request_irq(&pdev->dev, irq[0]->start,
 354                             em_gio_irq_handler, 0, name, p)) {
 355                dev_err(&pdev->dev, "failed to request low IRQ\n");
 356                ret = -ENOENT;
 357                goto err1;
 358        }
 359
 360        if (devm_request_irq(&pdev->dev, irq[1]->start,
 361                             em_gio_irq_handler, 0, name, p)) {
 362                dev_err(&pdev->dev, "failed to request high IRQ\n");
 363                ret = -ENOENT;
 364                goto err1;
 365        }
 366
 367        ret = gpiochip_add(gpio_chip);
 368        if (ret) {
 369                dev_err(&pdev->dev, "failed to add GPIO controller\n");
 370                goto err1;
 371        }
 372
 373        if (pdata->pctl_name) {
 374                ret = gpiochip_add_pin_range(gpio_chip, pdata->pctl_name, 0,
 375                                             gpio_chip->base, gpio_chip->ngpio);
 376                if (ret < 0)
 377                        dev_warn(&pdev->dev, "failed to add pin range\n");
 378        }
 379        return 0;
 380
 381err1:
 382        irq_domain_remove(p->irq_domain);
 383err0:
 384        return ret;
 385}
 386
 387static int em_gio_remove(struct platform_device *pdev)
 388{
 389        struct em_gio_priv *p = platform_get_drvdata(pdev);
 390        int ret;
 391
 392        ret = gpiochip_remove(&p->gpio_chip);
 393        if (ret)
 394                return ret;
 395
 396        irq_domain_remove(p->irq_domain);
 397        return 0;
 398}
 399
 400static const struct of_device_id em_gio_dt_ids[] = {
 401        { .compatible = "renesas,em-gio", },
 402        {},
 403};
 404MODULE_DEVICE_TABLE(of, em_gio_dt_ids);
 405
 406static struct platform_driver em_gio_device_driver = {
 407        .probe          = em_gio_probe,
 408        .remove         = em_gio_remove,
 409        .driver         = {
 410                .name   = "em_gio",
 411                .of_match_table = em_gio_dt_ids,
 412                .owner          = THIS_MODULE,
 413        }
 414};
 415
 416static int __init em_gio_init(void)
 417{
 418        return platform_driver_register(&em_gio_device_driver);
 419}
 420postcore_initcall(em_gio_init);
 421
 422static void __exit em_gio_exit(void)
 423{
 424        platform_driver_unregister(&em_gio_device_driver);
 425}
 426module_exit(em_gio_exit);
 427
 428MODULE_AUTHOR("Magnus Damm");
 429MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
 430MODULE_LICENSE("GPL v2");
 431
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