linux/drivers/crypto/omap-sham.c
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   1/*
   2 * Cryptographic API.
   3 *
   4 * Support for OMAP SHA1/MD5 HW acceleration.
   5 *
   6 * Copyright (c) 2010 Nokia Corporation
   7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8 * Copyright (c) 2011 Texas Instruments Incorporated
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License version 2 as published
  12 * by the Free Software Foundation.
  13 *
  14 * Some ideas are from old omap-sha1-md5.c driver.
  15 */
  16
  17#define pr_fmt(fmt) "%s: " fmt, __func__
  18
  19#include <linux/err.h>
  20#include <linux/device.h>
  21#include <linux/module.h>
  22#include <linux/init.h>
  23#include <linux/errno.h>
  24#include <linux/interrupt.h>
  25#include <linux/kernel.h>
  26#include <linux/irq.h>
  27#include <linux/io.h>
  28#include <linux/platform_device.h>
  29#include <linux/scatterlist.h>
  30#include <linux/dma-mapping.h>
  31#include <linux/dmaengine.h>
  32#include <linux/omap-dma.h>
  33#include <linux/pm_runtime.h>
  34#include <linux/of.h>
  35#include <linux/of_device.h>
  36#include <linux/of_address.h>
  37#include <linux/of_irq.h>
  38#include <linux/delay.h>
  39#include <linux/crypto.h>
  40#include <linux/cryptohash.h>
  41#include <crypto/scatterwalk.h>
  42#include <crypto/algapi.h>
  43#include <crypto/sha.h>
  44#include <crypto/hash.h>
  45#include <crypto/internal/hash.h>
  46
  47#define MD5_DIGEST_SIZE                 16
  48
  49#define SHA_REG_IDIGEST(dd, x)          ((dd)->pdata->idigest_ofs + ((x)*0x04))
  50#define SHA_REG_DIN(dd, x)              ((dd)->pdata->din_ofs + ((x) * 0x04))
  51#define SHA_REG_DIGCNT(dd)              ((dd)->pdata->digcnt_ofs)
  52
  53#define SHA_REG_ODIGEST(dd, x)          ((dd)->pdata->odigest_ofs + (x * 0x04))
  54
  55#define SHA_REG_CTRL                    0x18
  56#define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  57#define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  58#define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  59#define SHA_REG_CTRL_ALGO               (1 << 2)
  60#define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  61#define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  62
  63#define SHA_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  64
  65#define SHA_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  66#define SHA_REG_MASK_DMA_EN             (1 << 3)
  67#define SHA_REG_MASK_IT_EN              (1 << 2)
  68#define SHA_REG_MASK_SOFTRESET          (1 << 1)
  69#define SHA_REG_AUTOIDLE                (1 << 0)
  70
  71#define SHA_REG_SYSSTATUS(dd)           ((dd)->pdata->sysstatus_ofs)
  72#define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  73
  74#define SHA_REG_MODE(dd)                ((dd)->pdata->mode_ofs)
  75#define SHA_REG_MODE_HMAC_OUTER_HASH    (1 << 7)
  76#define SHA_REG_MODE_HMAC_KEY_PROC      (1 << 5)
  77#define SHA_REG_MODE_CLOSE_HASH         (1 << 4)
  78#define SHA_REG_MODE_ALGO_CONSTANT      (1 << 3)
  79
  80#define SHA_REG_MODE_ALGO_MASK          (7 << 0)
  81#define SHA_REG_MODE_ALGO_MD5_128       (0 << 1)
  82#define SHA_REG_MODE_ALGO_SHA1_160      (1 << 1)
  83#define SHA_REG_MODE_ALGO_SHA2_224      (2 << 1)
  84#define SHA_REG_MODE_ALGO_SHA2_256      (3 << 1)
  85#define SHA_REG_MODE_ALGO_SHA2_384      (1 << 0)
  86#define SHA_REG_MODE_ALGO_SHA2_512      (3 << 0)
  87
  88#define SHA_REG_LENGTH(dd)              ((dd)->pdata->length_ofs)
  89
  90#define SHA_REG_IRQSTATUS               0x118
  91#define SHA_REG_IRQSTATUS_CTX_RDY       (1 << 3)
  92#define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
  93#define SHA_REG_IRQSTATUS_INPUT_RDY     (1 << 1)
  94#define SHA_REG_IRQSTATUS_OUTPUT_RDY    (1 << 0)
  95
  96#define SHA_REG_IRQENA                  0x11C
  97#define SHA_REG_IRQENA_CTX_RDY          (1 << 3)
  98#define SHA_REG_IRQENA_PARTHASH_RDY     (1 << 2)
  99#define SHA_REG_IRQENA_INPUT_RDY        (1 << 1)
 100#define SHA_REG_IRQENA_OUTPUT_RDY       (1 << 0)
 101
 102#define DEFAULT_TIMEOUT_INTERVAL        HZ
 103
 104/* mostly device flags */
 105#define FLAGS_BUSY              0
 106#define FLAGS_FINAL             1
 107#define FLAGS_DMA_ACTIVE        2
 108#define FLAGS_OUTPUT_READY      3
 109#define FLAGS_INIT              4
 110#define FLAGS_CPU               5
 111#define FLAGS_DMA_READY         6
 112#define FLAGS_AUTO_XOR          7
 113#define FLAGS_BE32_SHA1         8
 114/* context flags */
 115#define FLAGS_FINUP             16
 116#define FLAGS_SG                17
 117
 118#define FLAGS_MODE_SHIFT        18
 119#define FLAGS_MODE_MASK         (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
 120#define FLAGS_MODE_MD5          (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
 121#define FLAGS_MODE_SHA1         (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
 122#define FLAGS_MODE_SHA224       (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
 123#define FLAGS_MODE_SHA256       (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
 124#define FLAGS_MODE_SHA384       (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
 125#define FLAGS_MODE_SHA512       (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
 126
 127#define FLAGS_HMAC              21
 128#define FLAGS_ERROR             22
 129
 130#define OP_UPDATE               1
 131#define OP_FINAL                2
 132
 133#define OMAP_ALIGN_MASK         (sizeof(u32)-1)
 134#define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
 135
 136#define BUFLEN                  PAGE_SIZE
 137
 138struct omap_sham_dev;
 139
 140struct omap_sham_reqctx {
 141        struct omap_sham_dev    *dd;
 142        unsigned long           flags;
 143        unsigned long           op;
 144
 145        u8                      digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
 146        size_t                  digcnt;
 147        size_t                  bufcnt;
 148        size_t                  buflen;
 149        dma_addr_t              dma_addr;
 150
 151        /* walk state */
 152        struct scatterlist      *sg;
 153        struct scatterlist      sgl;
 154        unsigned int            offset; /* offset in current sg */
 155        unsigned int            total;  /* total request */
 156
 157        u8                      buffer[0] OMAP_ALIGNED;
 158};
 159
 160struct omap_sham_hmac_ctx {
 161        struct crypto_shash     *shash;
 162        u8                      ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 163        u8                      opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 164};
 165
 166struct omap_sham_ctx {
 167        struct omap_sham_dev    *dd;
 168
 169        unsigned long           flags;
 170
 171        /* fallback stuff */
 172        struct crypto_shash     *fallback;
 173
 174        struct omap_sham_hmac_ctx base[0];
 175};
 176
 177#define OMAP_SHAM_QUEUE_LENGTH  1
 178
 179struct omap_sham_algs_info {
 180        struct ahash_alg        *algs_list;
 181        unsigned int            size;
 182        unsigned int            registered;
 183};
 184
 185struct omap_sham_pdata {
 186        struct omap_sham_algs_info      *algs_info;
 187        unsigned int    algs_info_size;
 188        unsigned long   flags;
 189        int             digest_size;
 190
 191        void            (*copy_hash)(struct ahash_request *req, int out);
 192        void            (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
 193                                      int final, int dma);
 194        void            (*trigger)(struct omap_sham_dev *dd, size_t length);
 195        int             (*poll_irq)(struct omap_sham_dev *dd);
 196        irqreturn_t     (*intr_hdlr)(int irq, void *dev_id);
 197
 198        u32             odigest_ofs;
 199        u32             idigest_ofs;
 200        u32             din_ofs;
 201        u32             digcnt_ofs;
 202        u32             rev_ofs;
 203        u32             mask_ofs;
 204        u32             sysstatus_ofs;
 205        u32             mode_ofs;
 206        u32             length_ofs;
 207
 208        u32             major_mask;
 209        u32             major_shift;
 210        u32             minor_mask;
 211        u32             minor_shift;
 212};
 213
 214struct omap_sham_dev {
 215        struct list_head        list;
 216        unsigned long           phys_base;
 217        struct device           *dev;
 218        void __iomem            *io_base;
 219        int                     irq;
 220        spinlock_t              lock;
 221        int                     err;
 222        unsigned int            dma;
 223        struct dma_chan         *dma_lch;
 224        struct tasklet_struct   done_task;
 225        u8                      polling_mode;
 226
 227        unsigned long           flags;
 228        struct crypto_queue     queue;
 229        struct ahash_request    *req;
 230
 231        const struct omap_sham_pdata    *pdata;
 232};
 233
 234struct omap_sham_drv {
 235        struct list_head        dev_list;
 236        spinlock_t              lock;
 237        unsigned long           flags;
 238};
 239
 240static struct omap_sham_drv sham = {
 241        .dev_list = LIST_HEAD_INIT(sham.dev_list),
 242        .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 243};
 244
 245static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 246{
 247        return __raw_readl(dd->io_base + offset);
 248}
 249
 250static inline void omap_sham_write(struct omap_sham_dev *dd,
 251                                        u32 offset, u32 value)
 252{
 253        __raw_writel(value, dd->io_base + offset);
 254}
 255
 256static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 257                                        u32 value, u32 mask)
 258{
 259        u32 val;
 260
 261        val = omap_sham_read(dd, address);
 262        val &= ~mask;
 263        val |= value;
 264        omap_sham_write(dd, address, val);
 265}
 266
 267static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 268{
 269        unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 270
 271        while (!(omap_sham_read(dd, offset) & bit)) {
 272                if (time_is_before_jiffies(timeout))
 273                        return -ETIMEDOUT;
 274        }
 275
 276        return 0;
 277}
 278
 279static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
 280{
 281        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 282        struct omap_sham_dev *dd = ctx->dd;
 283        u32 *hash = (u32 *)ctx->digest;
 284        int i;
 285
 286        for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 287                if (out)
 288                        hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
 289                else
 290                        omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
 291        }
 292}
 293
 294static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
 295{
 296        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 297        struct omap_sham_dev *dd = ctx->dd;
 298        int i;
 299
 300        if (ctx->flags & BIT(FLAGS_HMAC)) {
 301                struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 302                struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 303                struct omap_sham_hmac_ctx *bctx = tctx->base;
 304                u32 *opad = (u32 *)bctx->opad;
 305
 306                for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 307                        if (out)
 308                                opad[i] = omap_sham_read(dd,
 309                                                SHA_REG_ODIGEST(dd, i));
 310                        else
 311                                omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
 312                                                opad[i]);
 313                }
 314        }
 315
 316        omap_sham_copy_hash_omap2(req, out);
 317}
 318
 319static void omap_sham_copy_ready_hash(struct ahash_request *req)
 320{
 321        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 322        u32 *in = (u32 *)ctx->digest;
 323        u32 *hash = (u32 *)req->result;
 324        int i, d, big_endian = 0;
 325
 326        if (!hash)
 327                return;
 328
 329        switch (ctx->flags & FLAGS_MODE_MASK) {
 330        case FLAGS_MODE_MD5:
 331                d = MD5_DIGEST_SIZE / sizeof(u32);
 332                break;
 333        case FLAGS_MODE_SHA1:
 334                /* OMAP2 SHA1 is big endian */
 335                if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
 336                        big_endian = 1;
 337                d = SHA1_DIGEST_SIZE / sizeof(u32);
 338                break;
 339        case FLAGS_MODE_SHA224:
 340                d = SHA224_DIGEST_SIZE / sizeof(u32);
 341                break;
 342        case FLAGS_MODE_SHA256:
 343                d = SHA256_DIGEST_SIZE / sizeof(u32);
 344                break;
 345        case FLAGS_MODE_SHA384:
 346                d = SHA384_DIGEST_SIZE / sizeof(u32);
 347                break;
 348        case FLAGS_MODE_SHA512:
 349                d = SHA512_DIGEST_SIZE / sizeof(u32);
 350                break;
 351        default:
 352                d = 0;
 353        }
 354
 355        if (big_endian)
 356                for (i = 0; i < d; i++)
 357                        hash[i] = be32_to_cpu(in[i]);
 358        else
 359                for (i = 0; i < d; i++)
 360                        hash[i] = le32_to_cpu(in[i]);
 361}
 362
 363static int omap_sham_hw_init(struct omap_sham_dev *dd)
 364{
 365        pm_runtime_get_sync(dd->dev);
 366
 367        if (!test_bit(FLAGS_INIT, &dd->flags)) {
 368                set_bit(FLAGS_INIT, &dd->flags);
 369                dd->err = 0;
 370        }
 371
 372        return 0;
 373}
 374
 375static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
 376                                 int final, int dma)
 377{
 378        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 379        u32 val = length << 5, mask;
 380
 381        if (likely(ctx->digcnt))
 382                omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 383
 384        omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 385                SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 386                SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 387        /*
 388         * Setting ALGO_CONST only for the first iteration
 389         * and CLOSE_HASH only for the last one.
 390         */
 391        if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
 392                val |= SHA_REG_CTRL_ALGO;
 393        if (!ctx->digcnt)
 394                val |= SHA_REG_CTRL_ALGO_CONST;
 395        if (final)
 396                val |= SHA_REG_CTRL_CLOSE_HASH;
 397
 398        mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 399                        SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 400
 401        omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 402}
 403
 404static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
 405{
 406}
 407
 408static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
 409{
 410        return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
 411}
 412
 413static int get_block_size(struct omap_sham_reqctx *ctx)
 414{
 415        int d;
 416
 417        switch (ctx->flags & FLAGS_MODE_MASK) {
 418        case FLAGS_MODE_MD5:
 419        case FLAGS_MODE_SHA1:
 420                d = SHA1_BLOCK_SIZE;
 421                break;
 422        case FLAGS_MODE_SHA224:
 423        case FLAGS_MODE_SHA256:
 424                d = SHA256_BLOCK_SIZE;
 425                break;
 426        case FLAGS_MODE_SHA384:
 427        case FLAGS_MODE_SHA512:
 428                d = SHA512_BLOCK_SIZE;
 429                break;
 430        default:
 431                d = 0;
 432        }
 433
 434        return d;
 435}
 436
 437static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
 438                                    u32 *value, int count)
 439{
 440        for (; count--; value++, offset += 4)
 441                omap_sham_write(dd, offset, *value);
 442}
 443
 444static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
 445                                 int final, int dma)
 446{
 447        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 448        u32 val, mask;
 449
 450        /*
 451         * Setting ALGO_CONST only for the first iteration and
 452         * CLOSE_HASH only for the last one. Note that flags mode bits
 453         * correspond to algorithm encoding in mode register.
 454         */
 455        val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
 456        if (!ctx->digcnt) {
 457                struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 458                struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 459                struct omap_sham_hmac_ctx *bctx = tctx->base;
 460                int bs, nr_dr;
 461
 462                val |= SHA_REG_MODE_ALGO_CONSTANT;
 463
 464                if (ctx->flags & BIT(FLAGS_HMAC)) {
 465                        bs = get_block_size(ctx);
 466                        nr_dr = bs / (2 * sizeof(u32));
 467                        val |= SHA_REG_MODE_HMAC_KEY_PROC;
 468                        omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
 469                                          (u32 *)bctx->ipad, nr_dr);
 470                        omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
 471                                          (u32 *)bctx->ipad + nr_dr, nr_dr);
 472                        ctx->digcnt += bs;
 473                }
 474        }
 475
 476        if (final) {
 477                val |= SHA_REG_MODE_CLOSE_HASH;
 478
 479                if (ctx->flags & BIT(FLAGS_HMAC))
 480                        val |= SHA_REG_MODE_HMAC_OUTER_HASH;
 481        }
 482
 483        mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
 484               SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
 485               SHA_REG_MODE_HMAC_KEY_PROC;
 486
 487        dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
 488        omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
 489        omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
 490        omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 491                             SHA_REG_MASK_IT_EN |
 492                                     (dma ? SHA_REG_MASK_DMA_EN : 0),
 493                             SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 494}
 495
 496static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
 497{
 498        omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
 499}
 500
 501static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
 502{
 503        return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
 504                              SHA_REG_IRQSTATUS_INPUT_RDY);
 505}
 506
 507static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
 508                              size_t length, int final)
 509{
 510        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 511        int count, len32, bs32, offset = 0;
 512        const u32 *buffer = (const u32 *)buf;
 513
 514        dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 515                                                ctx->digcnt, length, final);
 516
 517        dd->pdata->write_ctrl(dd, length, final, 0);
 518        dd->pdata->trigger(dd, length);
 519
 520        /* should be non-zero before next lines to disable clocks later */
 521        ctx->digcnt += length;
 522
 523        if (final)
 524                set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 525
 526        set_bit(FLAGS_CPU, &dd->flags);
 527
 528        len32 = DIV_ROUND_UP(length, sizeof(u32));
 529        bs32 = get_block_size(ctx) / sizeof(u32);
 530
 531        while (len32) {
 532                if (dd->pdata->poll_irq(dd))
 533                        return -ETIMEDOUT;
 534
 535                for (count = 0; count < min(len32, bs32); count++, offset++)
 536                        omap_sham_write(dd, SHA_REG_DIN(dd, count),
 537                                        buffer[offset]);
 538                len32 -= min(len32, bs32);
 539        }
 540
 541        return -EINPROGRESS;
 542}
 543
 544static void omap_sham_dma_callback(void *param)
 545{
 546        struct omap_sham_dev *dd = param;
 547
 548        set_bit(FLAGS_DMA_READY, &dd->flags);
 549        tasklet_schedule(&dd->done_task);
 550}
 551
 552static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
 553                              size_t length, int final, int is_sg)
 554{
 555        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 556        struct dma_async_tx_descriptor *tx;
 557        struct dma_slave_config cfg;
 558        int len32, ret, dma_min = get_block_size(ctx);
 559
 560        dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 561                                                ctx->digcnt, length, final);
 562
 563        memset(&cfg, 0, sizeof(cfg));
 564
 565        cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
 566        cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 567        cfg.dst_maxburst = dma_min / DMA_SLAVE_BUSWIDTH_4_BYTES;
 568
 569        ret = dmaengine_slave_config(dd->dma_lch, &cfg);
 570        if (ret) {
 571                pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
 572                return ret;
 573        }
 574
 575        len32 = DIV_ROUND_UP(length, dma_min) * dma_min;
 576
 577        if (is_sg) {
 578                /*
 579                 * The SG entry passed in may not have the 'length' member
 580                 * set correctly so use a local SG entry (sgl) with the
 581                 * proper value for 'length' instead.  If this is not done,
 582                 * the dmaengine may try to DMA the incorrect amount of data.
 583                 */
 584                sg_init_table(&ctx->sgl, 1);
 585                ctx->sgl.page_link = ctx->sg->page_link;
 586                ctx->sgl.offset = ctx->sg->offset;
 587                sg_dma_len(&ctx->sgl) = len32;
 588                sg_dma_address(&ctx->sgl) = sg_dma_address(ctx->sg);
 589
 590                tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl, 1,
 591                        DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 592        } else {
 593                tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, len32,
 594                        DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 595        }
 596
 597        if (!tx) {
 598                dev_err(dd->dev, "prep_slave_sg/single() failed\n");
 599                return -EINVAL;
 600        }
 601
 602        tx->callback = omap_sham_dma_callback;
 603        tx->callback_param = dd;
 604
 605        dd->pdata->write_ctrl(dd, length, final, 1);
 606
 607        ctx->digcnt += length;
 608
 609        if (final)
 610                set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 611
 612        set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 613
 614        dmaengine_submit(tx);
 615        dma_async_issue_pending(dd->dma_lch);
 616
 617        dd->pdata->trigger(dd, length);
 618
 619        return -EINPROGRESS;
 620}
 621
 622static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
 623                                const u8 *data, size_t length)
 624{
 625        size_t count = min(length, ctx->buflen - ctx->bufcnt);
 626
 627        count = min(count, ctx->total);
 628        if (count <= 0)
 629                return 0;
 630        memcpy(ctx->buffer + ctx->bufcnt, data, count);
 631        ctx->bufcnt += count;
 632
 633        return count;
 634}
 635
 636static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
 637{
 638        size_t count;
 639
 640        while (ctx->sg) {
 641                count = omap_sham_append_buffer(ctx,
 642                                sg_virt(ctx->sg) + ctx->offset,
 643                                ctx->sg->length - ctx->offset);
 644                if (!count)
 645                        break;
 646                ctx->offset += count;
 647                ctx->total -= count;
 648                if (ctx->offset == ctx->sg->length) {
 649                        ctx->sg = sg_next(ctx->sg);
 650                        if (ctx->sg)
 651                                ctx->offset = 0;
 652                        else
 653                                ctx->total = 0;
 654                }
 655        }
 656
 657        return 0;
 658}
 659
 660static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
 661                                        struct omap_sham_reqctx *ctx,
 662                                        size_t length, int final)
 663{
 664        int ret;
 665
 666        ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
 667                                       DMA_TO_DEVICE);
 668        if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
 669                dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
 670                return -EINVAL;
 671        }
 672
 673        ctx->flags &= ~BIT(FLAGS_SG);
 674
 675        ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0);
 676        if (ret != -EINPROGRESS)
 677                dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
 678                                 DMA_TO_DEVICE);
 679
 680        return ret;
 681}
 682
 683static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
 684{
 685        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 686        unsigned int final;
 687        size_t count;
 688
 689        omap_sham_append_sg(ctx);
 690
 691        final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 692
 693        dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
 694                                         ctx->bufcnt, ctx->digcnt, final);
 695
 696        if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
 697                count = ctx->bufcnt;
 698                ctx->bufcnt = 0;
 699                return omap_sham_xmit_dma_map(dd, ctx, count, final);
 700        }
 701
 702        return 0;
 703}
 704
 705/* Start address alignment */
 706#define SG_AA(sg)       (IS_ALIGNED(sg->offset, sizeof(u32)))
 707/* SHA1 block size alignment */
 708#define SG_SA(sg, bs)   (IS_ALIGNED(sg->length, bs))
 709
 710static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
 711{
 712        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 713        unsigned int length, final, tail;
 714        struct scatterlist *sg;
 715        int ret, bs;
 716
 717        if (!ctx->total)
 718                return 0;
 719
 720        if (ctx->bufcnt || ctx->offset)
 721                return omap_sham_update_dma_slow(dd);
 722
 723        /*
 724         * Don't use the sg interface when the transfer size is less
 725         * than the number of elements in a DMA frame.  Otherwise,
 726         * the dmaengine infrastructure will calculate that it needs
 727         * to transfer 0 frames which ultimately fails.
 728         */
 729        if (ctx->total < get_block_size(ctx))
 730                return omap_sham_update_dma_slow(dd);
 731
 732        dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
 733                        ctx->digcnt, ctx->bufcnt, ctx->total);
 734
 735        sg = ctx->sg;
 736        bs = get_block_size(ctx);
 737
 738        if (!SG_AA(sg))
 739                return omap_sham_update_dma_slow(dd);
 740
 741        if (!sg_is_last(sg) && !SG_SA(sg, bs))
 742                /* size is not BLOCK_SIZE aligned */
 743                return omap_sham_update_dma_slow(dd);
 744
 745        length = min(ctx->total, sg->length);
 746
 747        if (sg_is_last(sg)) {
 748                if (!(ctx->flags & BIT(FLAGS_FINUP))) {
 749                        /* not last sg must be BLOCK_SIZE aligned */
 750                        tail = length & (bs - 1);
 751                        /* without finup() we need one block to close hash */
 752                        if (!tail)
 753                                tail = bs;
 754                        length -= tail;
 755                }
 756        }
 757
 758        if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
 759                dev_err(dd->dev, "dma_map_sg  error\n");
 760                return -EINVAL;
 761        }
 762
 763        ctx->flags |= BIT(FLAGS_SG);
 764
 765        ctx->total -= length;
 766        ctx->offset = length; /* offset where to start slow */
 767
 768        final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 769
 770        ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1);
 771        if (ret != -EINPROGRESS)
 772                dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
 773
 774        return ret;
 775}
 776
 777static int omap_sham_update_cpu(struct omap_sham_dev *dd)
 778{
 779        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 780        int bufcnt, final;
 781
 782        if (!ctx->total)
 783                return 0;
 784
 785        omap_sham_append_sg(ctx);
 786
 787        final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 788
 789        dev_dbg(dd->dev, "cpu: bufcnt: %u, digcnt: %d, final: %d\n",
 790                ctx->bufcnt, ctx->digcnt, final);
 791
 792        bufcnt = ctx->bufcnt;
 793        ctx->bufcnt = 0;
 794
 795        return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, final);
 796}
 797
 798static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 799{
 800        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 801
 802        dmaengine_terminate_all(dd->dma_lch);
 803
 804        if (ctx->flags & BIT(FLAGS_SG)) {
 805                dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
 806                if (ctx->sg->length == ctx->offset) {
 807                        ctx->sg = sg_next(ctx->sg);
 808                        if (ctx->sg)
 809                                ctx->offset = 0;
 810                }
 811        } else {
 812                dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
 813                                 DMA_TO_DEVICE);
 814        }
 815
 816        return 0;
 817}
 818
 819static int omap_sham_init(struct ahash_request *req)
 820{
 821        struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 822        struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 823        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 824        struct omap_sham_dev *dd = NULL, *tmp;
 825        int bs = 0;
 826
 827        spin_lock_bh(&sham.lock);
 828        if (!tctx->dd) {
 829                list_for_each_entry(tmp, &sham.dev_list, list) {
 830                        dd = tmp;
 831                        break;
 832                }
 833                tctx->dd = dd;
 834        } else {
 835                dd = tctx->dd;
 836        }
 837        spin_unlock_bh(&sham.lock);
 838
 839        ctx->dd = dd;
 840
 841        ctx->flags = 0;
 842
 843        dev_dbg(dd->dev, "init: digest size: %d\n",
 844                crypto_ahash_digestsize(tfm));
 845
 846        switch (crypto_ahash_digestsize(tfm)) {
 847        case MD5_DIGEST_SIZE:
 848                ctx->flags |= FLAGS_MODE_MD5;
 849                bs = SHA1_BLOCK_SIZE;
 850                break;
 851        case SHA1_DIGEST_SIZE:
 852                ctx->flags |= FLAGS_MODE_SHA1;
 853                bs = SHA1_BLOCK_SIZE;
 854                break;
 855        case SHA224_DIGEST_SIZE:
 856                ctx->flags |= FLAGS_MODE_SHA224;
 857                bs = SHA224_BLOCK_SIZE;
 858                break;
 859        case SHA256_DIGEST_SIZE:
 860                ctx->flags |= FLAGS_MODE_SHA256;
 861                bs = SHA256_BLOCK_SIZE;
 862                break;
 863        case SHA384_DIGEST_SIZE:
 864                ctx->flags |= FLAGS_MODE_SHA384;
 865                bs = SHA384_BLOCK_SIZE;
 866                break;
 867        case SHA512_DIGEST_SIZE:
 868                ctx->flags |= FLAGS_MODE_SHA512;
 869                bs = SHA512_BLOCK_SIZE;
 870                break;
 871        }
 872
 873        ctx->bufcnt = 0;
 874        ctx->digcnt = 0;
 875        ctx->buflen = BUFLEN;
 876
 877        if (tctx->flags & BIT(FLAGS_HMAC)) {
 878                if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
 879                        struct omap_sham_hmac_ctx *bctx = tctx->base;
 880
 881                        memcpy(ctx->buffer, bctx->ipad, bs);
 882                        ctx->bufcnt = bs;
 883                }
 884
 885                ctx->flags |= BIT(FLAGS_HMAC);
 886        }
 887
 888        return 0;
 889
 890}
 891
 892static int omap_sham_update_req(struct omap_sham_dev *dd)
 893{
 894        struct ahash_request *req = dd->req;
 895        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 896        int err;
 897
 898        dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
 899                 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
 900
 901        if (ctx->flags & BIT(FLAGS_CPU))
 902                err = omap_sham_update_cpu(dd);
 903        else
 904                err = omap_sham_update_dma_start(dd);
 905
 906        /* wait for dma completion before can take more data */
 907        dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
 908
 909        return err;
 910}
 911
 912static int omap_sham_final_req(struct omap_sham_dev *dd)
 913{
 914        struct ahash_request *req = dd->req;
 915        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 916        int err = 0, use_dma = 1;
 917
 918        if ((ctx->bufcnt <= get_block_size(ctx)) || dd->polling_mode)
 919                /*
 920                 * faster to handle last block with cpu or
 921                 * use cpu when dma is not present.
 922                 */
 923                use_dma = 0;
 924
 925        if (use_dma)
 926                err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
 927        else
 928                err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
 929
 930        ctx->bufcnt = 0;
 931
 932        dev_dbg(dd->dev, "final_req: err: %d\n", err);
 933
 934        return err;
 935}
 936
 937static int omap_sham_finish_hmac(struct ahash_request *req)
 938{
 939        struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
 940        struct omap_sham_hmac_ctx *bctx = tctx->base;
 941        int bs = crypto_shash_blocksize(bctx->shash);
 942        int ds = crypto_shash_digestsize(bctx->shash);
 943        struct {
 944                struct shash_desc shash;
 945                char ctx[crypto_shash_descsize(bctx->shash)];
 946        } desc;
 947
 948        desc.shash.tfm = bctx->shash;
 949        desc.shash.flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
 950
 951        return crypto_shash_init(&desc.shash) ?:
 952               crypto_shash_update(&desc.shash, bctx->opad, bs) ?:
 953               crypto_shash_finup(&desc.shash, req->result, ds, req->result);
 954}
 955
 956static int omap_sham_finish(struct ahash_request *req)
 957{
 958        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 959        struct omap_sham_dev *dd = ctx->dd;
 960        int err = 0;
 961
 962        if (ctx->digcnt) {
 963                omap_sham_copy_ready_hash(req);
 964                if ((ctx->flags & BIT(FLAGS_HMAC)) &&
 965                                !test_bit(FLAGS_AUTO_XOR, &dd->flags))
 966                        err = omap_sham_finish_hmac(req);
 967        }
 968
 969        dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
 970
 971        return err;
 972}
 973
 974static void omap_sham_finish_req(struct ahash_request *req, int err)
 975{
 976        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 977        struct omap_sham_dev *dd = ctx->dd;
 978
 979        if (!err) {
 980                dd->pdata->copy_hash(req, 1);
 981                if (test_bit(FLAGS_FINAL, &dd->flags))
 982                        err = omap_sham_finish(req);
 983        } else {
 984                ctx->flags |= BIT(FLAGS_ERROR);
 985        }
 986
 987        /* atomic operation is not needed here */
 988        dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
 989                        BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
 990
 991        pm_runtime_put(dd->dev);
 992
 993        if (req->base.complete)
 994                req->base.complete(&req->base, err);
 995
 996        /* handle new request */
 997        tasklet_schedule(&dd->done_task);
 998}
 999
1000static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1001                                  struct ahash_request *req)
1002{
1003        struct crypto_async_request *async_req, *backlog;
1004        struct omap_sham_reqctx *ctx;
1005        unsigned long flags;
1006        int err = 0, ret = 0;
1007
1008        spin_lock_irqsave(&dd->lock, flags);
1009        if (req)
1010                ret = ahash_enqueue_request(&dd->queue, req);
1011        if (test_bit(FLAGS_BUSY, &dd->flags)) {
1012                spin_unlock_irqrestore(&dd->lock, flags);
1013                return ret;
1014        }
1015        backlog = crypto_get_backlog(&dd->queue);
1016        async_req = crypto_dequeue_request(&dd->queue);
1017        if (async_req)
1018                set_bit(FLAGS_BUSY, &dd->flags);
1019        spin_unlock_irqrestore(&dd->lock, flags);
1020
1021        if (!async_req)
1022                return ret;
1023
1024        if (backlog)
1025                backlog->complete(backlog, -EINPROGRESS);
1026
1027        req = ahash_request_cast(async_req);
1028        dd->req = req;
1029        ctx = ahash_request_ctx(req);
1030
1031        dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1032                                                ctx->op, req->nbytes);
1033
1034        err = omap_sham_hw_init(dd);
1035        if (err)
1036                goto err1;
1037
1038        if (ctx->digcnt)
1039                /* request has changed - restore hash */
1040                dd->pdata->copy_hash(req, 0);
1041
1042        if (ctx->op == OP_UPDATE) {
1043                err = omap_sham_update_req(dd);
1044                if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1045                        /* no final() after finup() */
1046                        err = omap_sham_final_req(dd);
1047        } else if (ctx->op == OP_FINAL) {
1048                err = omap_sham_final_req(dd);
1049        }
1050err1:
1051        if (err != -EINPROGRESS)
1052                /* done_task will not finish it, so do it here */
1053                omap_sham_finish_req(req, err);
1054
1055        dev_dbg(dd->dev, "exit, err: %d\n", err);
1056
1057        return ret;
1058}
1059
1060static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1061{
1062        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1063        struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1064        struct omap_sham_dev *dd = tctx->dd;
1065
1066        ctx->op = op;
1067
1068        return omap_sham_handle_queue(dd, req);
1069}
1070
1071static int omap_sham_update(struct ahash_request *req)
1072{
1073        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1074        struct omap_sham_dev *dd = ctx->dd;
1075        int bs = get_block_size(ctx);
1076
1077        if (!req->nbytes)
1078                return 0;
1079
1080        ctx->total = req->nbytes;
1081        ctx->sg = req->src;
1082        ctx->offset = 0;
1083
1084        if (ctx->flags & BIT(FLAGS_FINUP)) {
1085                if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) {
1086                        /*
1087                        * OMAP HW accel works only with buffers >= 9
1088                        * will switch to bypass in final()
1089                        * final has the same request and data
1090                        */
1091                        omap_sham_append_sg(ctx);
1092                        return 0;
1093                } else if ((ctx->bufcnt + ctx->total <= bs) ||
1094                           dd->polling_mode) {
1095                        /*
1096                         * faster to use CPU for short transfers or
1097                         * use cpu when dma is not present.
1098                         */
1099                        ctx->flags |= BIT(FLAGS_CPU);
1100                }
1101        } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
1102                omap_sham_append_sg(ctx);
1103                return 0;
1104        }
1105
1106        return omap_sham_enqueue(req, OP_UPDATE);
1107}
1108
1109static int omap_sham_shash_digest(struct crypto_shash *shash, u32 flags,
1110                                  const u8 *data, unsigned int len, u8 *out)
1111{
1112        struct {
1113                struct shash_desc shash;
1114                char ctx[crypto_shash_descsize(shash)];
1115        } desc;
1116
1117        desc.shash.tfm = shash;
1118        desc.shash.flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1119
1120        return crypto_shash_digest(&desc.shash, data, len, out);
1121}
1122
1123static int omap_sham_final_shash(struct ahash_request *req)
1124{
1125        struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1126        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1127
1128        return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1129                                      ctx->buffer, ctx->bufcnt, req->result);
1130}
1131
1132static int omap_sham_final(struct ahash_request *req)
1133{
1134        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1135
1136        ctx->flags |= BIT(FLAGS_FINUP);
1137
1138        if (ctx->flags & BIT(FLAGS_ERROR))
1139                return 0; /* uncompleted hash is not needed */
1140
1141        /* OMAP HW accel works only with buffers >= 9 */
1142        /* HMAC is always >= 9 because ipad == block size */
1143        if ((ctx->digcnt + ctx->bufcnt) < 9)
1144                return omap_sham_final_shash(req);
1145        else if (ctx->bufcnt)
1146                return omap_sham_enqueue(req, OP_FINAL);
1147
1148        /* copy ready hash (+ finalize hmac) */
1149        return omap_sham_finish(req);
1150}
1151
1152static int omap_sham_finup(struct ahash_request *req)
1153{
1154        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1155        int err1, err2;
1156
1157        ctx->flags |= BIT(FLAGS_FINUP);
1158
1159        err1 = omap_sham_update(req);
1160        if (err1 == -EINPROGRESS || err1 == -EBUSY)
1161                return err1;
1162        /*
1163         * final() has to be always called to cleanup resources
1164         * even if udpate() failed, except EINPROGRESS
1165         */
1166        err2 = omap_sham_final(req);
1167
1168        return err1 ?: err2;
1169}
1170
1171static int omap_sham_digest(struct ahash_request *req)
1172{
1173        return omap_sham_init(req) ?: omap_sham_finup(req);
1174}
1175
1176static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1177                      unsigned int keylen)
1178{
1179        struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1180        struct omap_sham_hmac_ctx *bctx = tctx->base;
1181        int bs = crypto_shash_blocksize(bctx->shash);
1182        int ds = crypto_shash_digestsize(bctx->shash);
1183        struct omap_sham_dev *dd = NULL, *tmp;
1184        int err, i;
1185
1186        spin_lock_bh(&sham.lock);
1187        if (!tctx->dd) {
1188                list_for_each_entry(tmp, &sham.dev_list, list) {
1189                        dd = tmp;
1190                        break;
1191                }
1192                tctx->dd = dd;
1193        } else {
1194                dd = tctx->dd;
1195        }
1196        spin_unlock_bh(&sham.lock);
1197
1198        err = crypto_shash_setkey(tctx->fallback, key, keylen);
1199        if (err)
1200                return err;
1201
1202        if (keylen > bs) {
1203                err = omap_sham_shash_digest(bctx->shash,
1204                                crypto_shash_get_flags(bctx->shash),
1205                                key, keylen, bctx->ipad);
1206                if (err)
1207                        return err;
1208                keylen = ds;
1209        } else {
1210                memcpy(bctx->ipad, key, keylen);
1211        }
1212
1213        memset(bctx->ipad + keylen, 0, bs - keylen);
1214
1215        if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1216                memcpy(bctx->opad, bctx->ipad, bs);
1217
1218                for (i = 0; i < bs; i++) {
1219                        bctx->ipad[i] ^= 0x36;
1220                        bctx->opad[i] ^= 0x5c;
1221                }
1222        }
1223
1224        return err;
1225}
1226
1227static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1228{
1229        struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1230        const char *alg_name = crypto_tfm_alg_name(tfm);
1231
1232        /* Allocate a fallback and abort if it failed. */
1233        tctx->fallback = crypto_alloc_shash(alg_name, 0,
1234                                            CRYPTO_ALG_NEED_FALLBACK);
1235        if (IS_ERR(tctx->fallback)) {
1236                pr_err("omap-sham: fallback driver '%s' "
1237                                "could not be loaded.\n", alg_name);
1238                return PTR_ERR(tctx->fallback);
1239        }
1240
1241        crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1242                                 sizeof(struct omap_sham_reqctx) + BUFLEN);
1243
1244        if (alg_base) {
1245                struct omap_sham_hmac_ctx *bctx = tctx->base;
1246                tctx->flags |= BIT(FLAGS_HMAC);
1247                bctx->shash = crypto_alloc_shash(alg_base, 0,
1248                                                CRYPTO_ALG_NEED_FALLBACK);
1249                if (IS_ERR(bctx->shash)) {
1250                        pr_err("omap-sham: base driver '%s' "
1251                                        "could not be loaded.\n", alg_base);
1252                        crypto_free_shash(tctx->fallback);
1253                        return PTR_ERR(bctx->shash);
1254                }
1255
1256        }
1257
1258        return 0;
1259}
1260
1261static int omap_sham_cra_init(struct crypto_tfm *tfm)
1262{
1263        return omap_sham_cra_init_alg(tfm, NULL);
1264}
1265
1266static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1267{
1268        return omap_sham_cra_init_alg(tfm, "sha1");
1269}
1270
1271static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1272{
1273        return omap_sham_cra_init_alg(tfm, "sha224");
1274}
1275
1276static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1277{
1278        return omap_sham_cra_init_alg(tfm, "sha256");
1279}
1280
1281static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1282{
1283        return omap_sham_cra_init_alg(tfm, "md5");
1284}
1285
1286static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1287{
1288        return omap_sham_cra_init_alg(tfm, "sha384");
1289}
1290
1291static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1292{
1293        return omap_sham_cra_init_alg(tfm, "sha512");
1294}
1295
1296static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1297{
1298        struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1299
1300        crypto_free_shash(tctx->fallback);
1301        tctx->fallback = NULL;
1302
1303        if (tctx->flags & BIT(FLAGS_HMAC)) {
1304                struct omap_sham_hmac_ctx *bctx = tctx->base;
1305                crypto_free_shash(bctx->shash);
1306        }
1307}
1308
1309static struct ahash_alg algs_sha1_md5[] = {
1310{
1311        .init           = omap_sham_init,
1312        .update         = omap_sham_update,
1313        .final          = omap_sham_final,
1314        .finup          = omap_sham_finup,
1315        .digest         = omap_sham_digest,
1316        .halg.digestsize        = SHA1_DIGEST_SIZE,
1317        .halg.base      = {
1318                .cra_name               = "sha1",
1319                .cra_driver_name        = "omap-sha1",
1320                .cra_priority           = 100,
1321                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1322                                                CRYPTO_ALG_KERN_DRIVER_ONLY |
1323                                                CRYPTO_ALG_ASYNC |
1324                                                CRYPTO_ALG_NEED_FALLBACK,
1325                .cra_blocksize          = SHA1_BLOCK_SIZE,
1326                .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1327                .cra_alignmask          = 0,
1328                .cra_module             = THIS_MODULE,
1329                .cra_init               = omap_sham_cra_init,
1330                .cra_exit               = omap_sham_cra_exit,
1331        }
1332},
1333{
1334        .init           = omap_sham_init,
1335        .update         = omap_sham_update,
1336        .final          = omap_sham_final,
1337        .finup          = omap_sham_finup,
1338        .digest         = omap_sham_digest,
1339        .halg.digestsize        = MD5_DIGEST_SIZE,
1340        .halg.base      = {
1341                .cra_name               = "md5",
1342                .cra_driver_name        = "omap-md5",
1343                .cra_priority           = 100,
1344                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1345                                                CRYPTO_ALG_KERN_DRIVER_ONLY |
1346                                                CRYPTO_ALG_ASYNC |
1347                                                CRYPTO_ALG_NEED_FALLBACK,
1348                .cra_blocksize          = SHA1_BLOCK_SIZE,
1349                .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1350                .cra_alignmask          = OMAP_ALIGN_MASK,
1351                .cra_module             = THIS_MODULE,
1352                .cra_init               = omap_sham_cra_init,
1353                .cra_exit               = omap_sham_cra_exit,
1354        }
1355},
1356{
1357        .init           = omap_sham_init,
1358        .update         = omap_sham_update,
1359        .final          = omap_sham_final,
1360        .finup          = omap_sham_finup,
1361        .digest         = omap_sham_digest,
1362        .setkey         = omap_sham_setkey,
1363        .halg.digestsize        = SHA1_DIGEST_SIZE,
1364        .halg.base      = {
1365                .cra_name               = "hmac(sha1)",
1366                .cra_driver_name        = "omap-hmac-sha1",
1367                .cra_priority           = 100,
1368                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1369                                                CRYPTO_ALG_KERN_DRIVER_ONLY |
1370                                                CRYPTO_ALG_ASYNC |
1371                                                CRYPTO_ALG_NEED_FALLBACK,
1372                .cra_blocksize          = SHA1_BLOCK_SIZE,
1373                .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1374                                        sizeof(struct omap_sham_hmac_ctx),
1375                .cra_alignmask          = OMAP_ALIGN_MASK,
1376                .cra_module             = THIS_MODULE,
1377                .cra_init               = omap_sham_cra_sha1_init,
1378                .cra_exit               = omap_sham_cra_exit,
1379        }
1380},
1381{
1382        .init           = omap_sham_init,
1383        .update         = omap_sham_update,
1384        .final          = omap_sham_final,
1385        .finup          = omap_sham_finup,
1386        .digest         = omap_sham_digest,
1387        .setkey         = omap_sham_setkey,
1388        .halg.digestsize        = MD5_DIGEST_SIZE,
1389        .halg.base      = {
1390                .cra_name               = "hmac(md5)",
1391                .cra_driver_name        = "omap-hmac-md5",
1392                .cra_priority           = 100,
1393                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1394                                                CRYPTO_ALG_KERN_DRIVER_ONLY |
1395                                                CRYPTO_ALG_ASYNC |
1396                                                CRYPTO_ALG_NEED_FALLBACK,
1397                .cra_blocksize          = SHA1_BLOCK_SIZE,
1398                .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1399                                        sizeof(struct omap_sham_hmac_ctx),
1400                .cra_alignmask          = OMAP_ALIGN_MASK,
1401                .cra_module             = THIS_MODULE,
1402                .cra_init               = omap_sham_cra_md5_init,
1403                .cra_exit               = omap_sham_cra_exit,
1404        }
1405}
1406};
1407
1408/* OMAP4 has some algs in addition to what OMAP2 has */
1409static struct ahash_alg algs_sha224_sha256[] = {
1410{
1411        .init           = omap_sham_init,
1412        .update         = omap_sham_update,
1413        .final          = omap_sham_final,
1414        .finup          = omap_sham_finup,
1415        .digest         = omap_sham_digest,
1416        .halg.digestsize        = SHA224_DIGEST_SIZE,
1417        .halg.base      = {
1418                .cra_name               = "sha224",
1419                .cra_driver_name        = "omap-sha224",
1420                .cra_priority           = 100,
1421                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1422                                                CRYPTO_ALG_ASYNC |
1423                                                CRYPTO_ALG_NEED_FALLBACK,
1424                .cra_blocksize          = SHA224_BLOCK_SIZE,
1425                .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1426                .cra_alignmask          = 0,
1427                .cra_module             = THIS_MODULE,
1428                .cra_init               = omap_sham_cra_init,
1429                .cra_exit               = omap_sham_cra_exit,
1430        }
1431},
1432{
1433        .init           = omap_sham_init,
1434        .update         = omap_sham_update,
1435        .final          = omap_sham_final,
1436        .finup          = omap_sham_finup,
1437        .digest         = omap_sham_digest,
1438        .halg.digestsize        = SHA256_DIGEST_SIZE,
1439        .halg.base      = {
1440                .cra_name               = "sha256",
1441                .cra_driver_name        = "omap-sha256",
1442                .cra_priority           = 100,
1443                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1444                                                CRYPTO_ALG_ASYNC |
1445                                                CRYPTO_ALG_NEED_FALLBACK,
1446                .cra_blocksize          = SHA256_BLOCK_SIZE,
1447                .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1448                .cra_alignmask          = 0,
1449                .cra_module             = THIS_MODULE,
1450                .cra_init               = omap_sham_cra_init,
1451                .cra_exit               = omap_sham_cra_exit,
1452        }
1453},
1454{
1455        .init           = omap_sham_init,
1456        .update         = omap_sham_update,
1457        .final          = omap_sham_final,
1458        .finup          = omap_sham_finup,
1459        .digest         = omap_sham_digest,
1460        .setkey         = omap_sham_setkey,
1461        .halg.digestsize        = SHA224_DIGEST_SIZE,
1462        .halg.base      = {
1463                .cra_name               = "hmac(sha224)",
1464                .cra_driver_name        = "omap-hmac-sha224",
1465                .cra_priority           = 100,
1466                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1467                                                CRYPTO_ALG_ASYNC |
1468                                                CRYPTO_ALG_NEED_FALLBACK,
1469                .cra_blocksize          = SHA224_BLOCK_SIZE,
1470                .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1471                                        sizeof(struct omap_sham_hmac_ctx),
1472                .cra_alignmask          = OMAP_ALIGN_MASK,
1473                .cra_module             = THIS_MODULE,
1474                .cra_init               = omap_sham_cra_sha224_init,
1475                .cra_exit               = omap_sham_cra_exit,
1476        }
1477},
1478{
1479        .init           = omap_sham_init,
1480        .update         = omap_sham_update,
1481        .final          = omap_sham_final,
1482        .finup          = omap_sham_finup,
1483        .digest         = omap_sham_digest,
1484        .setkey         = omap_sham_setkey,
1485        .halg.digestsize        = SHA256_DIGEST_SIZE,
1486        .halg.base      = {
1487                .cra_name               = "hmac(sha256)",
1488                .cra_driver_name        = "omap-hmac-sha256",
1489                .cra_priority           = 100,
1490                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1491                                                CRYPTO_ALG_ASYNC |
1492                                                CRYPTO_ALG_NEED_FALLBACK,
1493                .cra_blocksize          = SHA256_BLOCK_SIZE,
1494                .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1495                                        sizeof(struct omap_sham_hmac_ctx),
1496                .cra_alignmask          = OMAP_ALIGN_MASK,
1497                .cra_module             = THIS_MODULE,
1498                .cra_init               = omap_sham_cra_sha256_init,
1499                .cra_exit               = omap_sham_cra_exit,
1500        }
1501},
1502};
1503
1504static struct ahash_alg algs_sha384_sha512[] = {
1505{
1506        .init           = omap_sham_init,
1507        .update         = omap_sham_update,
1508        .final          = omap_sham_final,
1509        .finup          = omap_sham_finup,
1510        .digest         = omap_sham_digest,
1511        .halg.digestsize        = SHA384_DIGEST_SIZE,
1512        .halg.base      = {
1513                .cra_name               = "sha384",
1514                .cra_driver_name        = "omap-sha384",
1515                .cra_priority           = 100,
1516                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1517                                                CRYPTO_ALG_ASYNC |
1518                                                CRYPTO_ALG_NEED_FALLBACK,
1519                .cra_blocksize          = SHA384_BLOCK_SIZE,
1520                .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1521                .cra_alignmask          = 0,
1522                .cra_module             = THIS_MODULE,
1523                .cra_init               = omap_sham_cra_init,
1524                .cra_exit               = omap_sham_cra_exit,
1525        }
1526},
1527{
1528        .init           = omap_sham_init,
1529        .update         = omap_sham_update,
1530        .final          = omap_sham_final,
1531        .finup          = omap_sham_finup,
1532        .digest         = omap_sham_digest,
1533        .halg.digestsize        = SHA512_DIGEST_SIZE,
1534        .halg.base      = {
1535                .cra_name               = "sha512",
1536                .cra_driver_name        = "omap-sha512",
1537                .cra_priority           = 100,
1538                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1539                                                CRYPTO_ALG_ASYNC |
1540                                                CRYPTO_ALG_NEED_FALLBACK,
1541                .cra_blocksize          = SHA512_BLOCK_SIZE,
1542                .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1543                .cra_alignmask          = 0,
1544                .cra_module             = THIS_MODULE,
1545                .cra_init               = omap_sham_cra_init,
1546                .cra_exit               = omap_sham_cra_exit,
1547        }
1548},
1549{
1550        .init           = omap_sham_init,
1551        .update         = omap_sham_update,
1552        .final          = omap_sham_final,
1553        .finup          = omap_sham_finup,
1554        .digest         = omap_sham_digest,
1555        .setkey         = omap_sham_setkey,
1556        .halg.digestsize        = SHA384_DIGEST_SIZE,
1557        .halg.base      = {
1558                .cra_name               = "hmac(sha384)",
1559                .cra_driver_name        = "omap-hmac-sha384",
1560                .cra_priority           = 100,
1561                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1562                                                CRYPTO_ALG_ASYNC |
1563                                                CRYPTO_ALG_NEED_FALLBACK,
1564                .cra_blocksize          = SHA384_BLOCK_SIZE,
1565                .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1566                                        sizeof(struct omap_sham_hmac_ctx),
1567                .cra_alignmask          = OMAP_ALIGN_MASK,
1568                .cra_module             = THIS_MODULE,
1569                .cra_init               = omap_sham_cra_sha384_init,
1570                .cra_exit               = omap_sham_cra_exit,
1571        }
1572},
1573{
1574        .init           = omap_sham_init,
1575        .update         = omap_sham_update,
1576        .final          = omap_sham_final,
1577        .finup          = omap_sham_finup,
1578        .digest         = omap_sham_digest,
1579        .setkey         = omap_sham_setkey,
1580        .halg.digestsize        = SHA512_DIGEST_SIZE,
1581        .halg.base      = {
1582                .cra_name               = "hmac(sha512)",
1583                .cra_driver_name        = "omap-hmac-sha512",
1584                .cra_priority           = 100,
1585                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1586                                                CRYPTO_ALG_ASYNC |
1587                                                CRYPTO_ALG_NEED_FALLBACK,
1588                .cra_blocksize          = SHA512_BLOCK_SIZE,
1589                .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1590                                        sizeof(struct omap_sham_hmac_ctx),
1591                .cra_alignmask          = OMAP_ALIGN_MASK,
1592                .cra_module             = THIS_MODULE,
1593                .cra_init               = omap_sham_cra_sha512_init,
1594                .cra_exit               = omap_sham_cra_exit,
1595        }
1596},
1597};
1598
1599static void omap_sham_done_task(unsigned long data)
1600{
1601        struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1602        int err = 0;
1603
1604        if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1605                omap_sham_handle_queue(dd, NULL);
1606                return;
1607        }
1608
1609        if (test_bit(FLAGS_CPU, &dd->flags)) {
1610                if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1611                        /* hash or semi-hash ready */
1612                        err = omap_sham_update_cpu(dd);
1613                        if (err != -EINPROGRESS)
1614                                goto finish;
1615                }
1616        } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1617                if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1618                        omap_sham_update_dma_stop(dd);
1619                        if (dd->err) {
1620                                err = dd->err;
1621                                goto finish;
1622                        }
1623                }
1624                if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1625                        /* hash or semi-hash ready */
1626                        clear_bit(FLAGS_DMA_READY, &dd->flags);
1627                        err = omap_sham_update_dma_start(dd);
1628                        if (err != -EINPROGRESS)
1629                                goto finish;
1630                }
1631        }
1632
1633        return;
1634
1635finish:
1636        dev_dbg(dd->dev, "update done: err: %d\n", err);
1637        /* finish curent request */
1638        omap_sham_finish_req(dd->req, err);
1639}
1640
1641static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1642{
1643        if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1644                dev_warn(dd->dev, "Interrupt when no active requests.\n");
1645        } else {
1646                set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1647                tasklet_schedule(&dd->done_task);
1648        }
1649
1650        return IRQ_HANDLED;
1651}
1652
1653static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1654{
1655        struct omap_sham_dev *dd = dev_id;
1656
1657        if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1658                /* final -> allow device to go to power-saving mode */
1659                omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1660
1661        omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1662                                 SHA_REG_CTRL_OUTPUT_READY);
1663        omap_sham_read(dd, SHA_REG_CTRL);
1664
1665        return omap_sham_irq_common(dd);
1666}
1667
1668static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1669{
1670        struct omap_sham_dev *dd = dev_id;
1671
1672        omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1673
1674        return omap_sham_irq_common(dd);
1675}
1676
1677static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1678        {
1679                .algs_list      = algs_sha1_md5,
1680                .size           = ARRAY_SIZE(algs_sha1_md5),
1681        },
1682};
1683
1684static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1685        .algs_info      = omap_sham_algs_info_omap2,
1686        .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1687        .flags          = BIT(FLAGS_BE32_SHA1),
1688        .digest_size    = SHA1_DIGEST_SIZE,
1689        .copy_hash      = omap_sham_copy_hash_omap2,
1690        .write_ctrl     = omap_sham_write_ctrl_omap2,
1691        .trigger        = omap_sham_trigger_omap2,
1692        .poll_irq       = omap_sham_poll_irq_omap2,
1693        .intr_hdlr      = omap_sham_irq_omap2,
1694        .idigest_ofs    = 0x00,
1695        .din_ofs        = 0x1c,
1696        .digcnt_ofs     = 0x14,
1697        .rev_ofs        = 0x5c,
1698        .mask_ofs       = 0x60,
1699        .sysstatus_ofs  = 0x64,
1700        .major_mask     = 0xf0,
1701        .major_shift    = 4,
1702        .minor_mask     = 0x0f,
1703        .minor_shift    = 0,
1704};
1705
1706#ifdef CONFIG_OF
1707static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1708        {
1709                .algs_list      = algs_sha1_md5,
1710                .size           = ARRAY_SIZE(algs_sha1_md5),
1711        },
1712        {
1713                .algs_list      = algs_sha224_sha256,
1714                .size           = ARRAY_SIZE(algs_sha224_sha256),
1715        },
1716};
1717
1718static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1719        .algs_info      = omap_sham_algs_info_omap4,
1720        .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1721        .flags          = BIT(FLAGS_AUTO_XOR),
1722        .digest_size    = SHA256_DIGEST_SIZE,
1723        .copy_hash      = omap_sham_copy_hash_omap4,
1724        .write_ctrl     = omap_sham_write_ctrl_omap4,
1725        .trigger        = omap_sham_trigger_omap4,
1726        .poll_irq       = omap_sham_poll_irq_omap4,
1727        .intr_hdlr      = omap_sham_irq_omap4,
1728        .idigest_ofs    = 0x020,
1729        .odigest_ofs    = 0x0,
1730        .din_ofs        = 0x080,
1731        .digcnt_ofs     = 0x040,
1732        .rev_ofs        = 0x100,
1733        .mask_ofs       = 0x110,
1734        .sysstatus_ofs  = 0x114,
1735        .mode_ofs       = 0x44,
1736        .length_ofs     = 0x48,
1737        .major_mask     = 0x0700,
1738        .major_shift    = 8,
1739        .minor_mask     = 0x003f,
1740        .minor_shift    = 0,
1741};
1742
1743static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1744        {
1745                .algs_list      = algs_sha1_md5,
1746                .size           = ARRAY_SIZE(algs_sha1_md5),
1747        },
1748        {
1749                .algs_list      = algs_sha224_sha256,
1750                .size           = ARRAY_SIZE(algs_sha224_sha256),
1751        },
1752        {
1753                .algs_list      = algs_sha384_sha512,
1754                .size           = ARRAY_SIZE(algs_sha384_sha512),
1755        },
1756};
1757
1758static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1759        .algs_info      = omap_sham_algs_info_omap5,
1760        .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1761        .flags          = BIT(FLAGS_AUTO_XOR),
1762        .digest_size    = SHA512_DIGEST_SIZE,
1763        .copy_hash      = omap_sham_copy_hash_omap4,
1764        .write_ctrl     = omap_sham_write_ctrl_omap4,
1765        .trigger        = omap_sham_trigger_omap4,
1766        .poll_irq       = omap_sham_poll_irq_omap4,
1767        .intr_hdlr      = omap_sham_irq_omap4,
1768        .idigest_ofs    = 0x240,
1769        .odigest_ofs    = 0x200,
1770        .din_ofs        = 0x080,
1771        .digcnt_ofs     = 0x280,
1772        .rev_ofs        = 0x100,
1773        .mask_ofs       = 0x110,
1774        .sysstatus_ofs  = 0x114,
1775        .mode_ofs       = 0x284,
1776        .length_ofs     = 0x288,
1777        .major_mask     = 0x0700,
1778        .major_shift    = 8,
1779        .minor_mask     = 0x003f,
1780        .minor_shift    = 0,
1781};
1782
1783static const struct of_device_id omap_sham_of_match[] = {
1784        {
1785                .compatible     = "ti,omap2-sham",
1786                .data           = &omap_sham_pdata_omap2,
1787        },
1788        {
1789                .compatible     = "ti,omap4-sham",
1790                .data           = &omap_sham_pdata_omap4,
1791        },
1792        {
1793                .compatible     = "ti,omap5-sham",
1794                .data           = &omap_sham_pdata_omap5,
1795        },
1796        {},
1797};
1798MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1799
1800static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1801                struct device *dev, struct resource *res)
1802{
1803        struct device_node *node = dev->of_node;
1804        const struct of_device_id *match;
1805        int err = 0;
1806
1807        match = of_match_device(of_match_ptr(omap_sham_of_match), dev);
1808        if (!match) {
1809                dev_err(dev, "no compatible OF match\n");
1810                err = -EINVAL;
1811                goto err;
1812        }
1813
1814        err = of_address_to_resource(node, 0, res);
1815        if (err < 0) {
1816                dev_err(dev, "can't translate OF node address\n");
1817                err = -EINVAL;
1818                goto err;
1819        }
1820
1821        dd->irq = of_irq_to_resource(node, 0, NULL);
1822        if (!dd->irq) {
1823                dev_err(dev, "can't translate OF irq value\n");
1824                err = -EINVAL;
1825                goto err;
1826        }
1827
1828        dd->dma = -1; /* Dummy value that's unused */
1829        dd->pdata = match->data;
1830
1831err:
1832        return err;
1833}
1834#else
1835static const struct of_device_id omap_sham_of_match[] = {
1836        {},
1837};
1838
1839static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1840                struct device *dev, struct resource *res)
1841{
1842        return -EINVAL;
1843}
1844#endif
1845
1846static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1847                struct platform_device *pdev, struct resource *res)
1848{
1849        struct device *dev = &pdev->dev;
1850        struct resource *r;
1851        int err = 0;
1852
1853        /* Get the base address */
1854        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1855        if (!r) {
1856                dev_err(dev, "no MEM resource info\n");
1857                err = -ENODEV;
1858                goto err;
1859        }
1860        memcpy(res, r, sizeof(*res));
1861
1862        /* Get the IRQ */
1863        dd->irq = platform_get_irq(pdev, 0);
1864        if (dd->irq < 0) {
1865                dev_err(dev, "no IRQ resource info\n");
1866                err = dd->irq;
1867                goto err;
1868        }
1869
1870        /* Get the DMA */
1871        r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1872        if (!r) {
1873                dev_err(dev, "no DMA resource info\n");
1874                err = -ENODEV;
1875                goto err;
1876        }
1877        dd->dma = r->start;
1878
1879        /* Only OMAP2/3 can be non-DT */
1880        dd->pdata = &omap_sham_pdata_omap2;
1881
1882err:
1883        return err;
1884}
1885
1886static int omap_sham_probe(struct platform_device *pdev)
1887{
1888        struct omap_sham_dev *dd;
1889        struct device *dev = &pdev->dev;
1890        struct resource res;
1891        dma_cap_mask_t mask;
1892        int err, i, j;
1893        u32 rev;
1894
1895        dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
1896        if (dd == NULL) {
1897                dev_err(dev, "unable to alloc data struct.\n");
1898                err = -ENOMEM;
1899                goto data_err;
1900        }
1901        dd->dev = dev;
1902        platform_set_drvdata(pdev, dd);
1903
1904        INIT_LIST_HEAD(&dd->list);
1905        spin_lock_init(&dd->lock);
1906        tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
1907        crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
1908
1909        err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
1910                               omap_sham_get_res_pdev(dd, pdev, &res);
1911        if (err)
1912                goto data_err;
1913
1914        dd->io_base = devm_ioremap_resource(dev, &res);
1915        if (IS_ERR(dd->io_base)) {
1916                err = PTR_ERR(dd->io_base);
1917                goto data_err;
1918        }
1919        dd->phys_base = res.start;
1920
1921        err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
1922                               IRQF_TRIGGER_NONE, dev_name(dev), dd);
1923        if (err) {
1924                dev_err(dev, "unable to request irq %d, err = %d\n",
1925                        dd->irq, err);
1926                goto data_err;
1927        }
1928
1929        dma_cap_zero(mask);
1930        dma_cap_set(DMA_SLAVE, mask);
1931
1932        dd->dma_lch = dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
1933                                                       &dd->dma, dev, "rx");
1934        if (!dd->dma_lch) {
1935                dd->polling_mode = 1;
1936                dev_dbg(dev, "using polling mode instead of dma\n");
1937        }
1938
1939        dd->flags |= dd->pdata->flags;
1940
1941        pm_runtime_enable(dev);
1942        pm_runtime_get_sync(dev);
1943        rev = omap_sham_read(dd, SHA_REG_REV(dd));
1944        pm_runtime_put_sync(&pdev->dev);
1945
1946        dev_info(dev, "hw accel on OMAP rev %u.%u\n",
1947                (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
1948                (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1949
1950        spin_lock(&sham.lock);
1951        list_add_tail(&dd->list, &sham.dev_list);
1952        spin_unlock(&sham.lock);
1953
1954        for (i = 0; i < dd->pdata->algs_info_size; i++) {
1955                for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1956                        err = crypto_register_ahash(
1957                                        &dd->pdata->algs_info[i].algs_list[j]);
1958                        if (err)
1959                                goto err_algs;
1960
1961                        dd->pdata->algs_info[i].registered++;
1962                }
1963        }
1964
1965        return 0;
1966
1967err_algs:
1968        for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1969                for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1970                        crypto_unregister_ahash(
1971                                        &dd->pdata->algs_info[i].algs_list[j]);
1972        pm_runtime_disable(dev);
1973        dma_release_channel(dd->dma_lch);
1974data_err:
1975        dev_err(dev, "initialization failed.\n");
1976
1977        return err;
1978}
1979
1980static int omap_sham_remove(struct platform_device *pdev)
1981{
1982        static struct omap_sham_dev *dd;
1983        int i, j;
1984
1985        dd = platform_get_drvdata(pdev);
1986        if (!dd)
1987                return -ENODEV;
1988        spin_lock(&sham.lock);
1989        list_del(&dd->list);
1990        spin_unlock(&sham.lock);
1991        for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1992                for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1993                        crypto_unregister_ahash(
1994                                        &dd->pdata->algs_info[i].algs_list[j]);
1995        tasklet_kill(&dd->done_task);
1996        pm_runtime_disable(&pdev->dev);
1997        dma_release_channel(dd->dma_lch);
1998
1999        return 0;
2000}
2001
2002#ifdef CONFIG_PM_SLEEP
2003static int omap_sham_suspend(struct device *dev)
2004{
2005        pm_runtime_put_sync(dev);
2006        return 0;
2007}
2008
2009static int omap_sham_resume(struct device *dev)
2010{
2011        pm_runtime_get_sync(dev);
2012        return 0;
2013}
2014#endif
2015
2016static const struct dev_pm_ops omap_sham_pm_ops = {
2017        SET_SYSTEM_SLEEP_PM_OPS(omap_sham_suspend, omap_sham_resume)
2018};
2019
2020static struct platform_driver omap_sham_driver = {
2021        .probe  = omap_sham_probe,
2022        .remove = omap_sham_remove,
2023        .driver = {
2024                .name   = "omap-sham",
2025                .owner  = THIS_MODULE,
2026                .pm     = &omap_sham_pm_ops,
2027                .of_match_table = omap_sham_of_match,
2028        },
2029};
2030
2031module_platform_driver(omap_sham_driver);
2032
2033MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2034MODULE_LICENSE("GPL v2");
2035MODULE_AUTHOR("Dmitry Kasatkin");
2036
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