linux/drivers/cpufreq/sa1110-cpufreq.c
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   1/*
   2 *  linux/arch/arm/mach-sa1100/cpu-sa1110.c
   3 *
   4 *  Copyright (C) 2001 Russell King
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 *
  10 * Note: there are two erratas that apply to the SA1110 here:
  11 *  7 - SDRAM auto-power-up failure (rev A0)
  12 * 13 - Corruption of internal register reads/writes following
  13 *      SDRAM reads (rev A0, B0, B1)
  14 *
  15 * We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
  16 *
  17 * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
  18 */
  19#include <linux/cpufreq.h>
  20#include <linux/delay.h>
  21#include <linux/init.h>
  22#include <linux/io.h>
  23#include <linux/kernel.h>
  24#include <linux/moduleparam.h>
  25#include <linux/types.h>
  26
  27#include <asm/cputype.h>
  28#include <asm/mach-types.h>
  29
  30#include <mach/generic.h>
  31#include <mach/hardware.h>
  32
  33#undef DEBUG
  34
  35struct sdram_params {
  36        const char name[20];
  37        u_char  rows;           /* bits                          */
  38        u_char  cas_latency;    /* cycles                        */
  39        u_char  tck;            /* clock cycle time (ns)         */
  40        u_char  trcd;           /* activate to r/w (ns)          */
  41        u_char  trp;            /* precharge to activate (ns)    */
  42        u_char  twr;            /* write recovery time (ns)      */
  43        u_short refresh;        /* refresh time for array (us)   */
  44};
  45
  46struct sdram_info {
  47        u_int   mdcnfg;
  48        u_int   mdrefr;
  49        u_int   mdcas[3];
  50};
  51
  52static struct sdram_params sdram_tbl[] __initdata = {
  53        {       /* Toshiba TC59SM716 CL2 */
  54                .name           = "TC59SM716-CL2",
  55                .rows           = 12,
  56                .tck            = 10,
  57                .trcd           = 20,
  58                .trp            = 20,
  59                .twr            = 10,
  60                .refresh        = 64000,
  61                .cas_latency    = 2,
  62        }, {    /* Toshiba TC59SM716 CL3 */
  63                .name           = "TC59SM716-CL3",
  64                .rows           = 12,
  65                .tck            = 8,
  66                .trcd           = 20,
  67                .trp            = 20,
  68                .twr            = 8,
  69                .refresh        = 64000,
  70                .cas_latency    = 3,
  71        }, {    /* Samsung K4S641632D TC75 */
  72                .name           = "K4S641632D",
  73                .rows           = 14,
  74                .tck            = 9,
  75                .trcd           = 27,
  76                .trp            = 20,
  77                .twr            = 9,
  78                .refresh        = 64000,
  79                .cas_latency    = 3,
  80        }, {    /* Samsung K4S281632B-1H */
  81                .name           = "K4S281632B-1H",
  82                .rows           = 12,
  83                .tck            = 10,
  84                .trp            = 20,
  85                .twr            = 10,
  86                .refresh        = 64000,
  87                .cas_latency    = 3,
  88        }, {    /* Samsung KM416S4030CT */
  89                .name           = "KM416S4030CT",
  90                .rows           = 13,
  91                .tck            = 8,
  92                .trcd           = 24,   /* 3 CLKs */
  93                .trp            = 24,   /* 3 CLKs */
  94                .twr            = 16,   /* Trdl: 2 CLKs */
  95                .refresh        = 64000,
  96                .cas_latency    = 3,
  97        }, {    /* Winbond W982516AH75L CL3 */
  98                .name           = "W982516AH75L",
  99                .rows           = 16,
 100                .tck            = 8,
 101                .trcd           = 20,
 102                .trp            = 20,
 103                .twr            = 8,
 104                .refresh        = 64000,
 105                .cas_latency    = 3,
 106        }, {    /* Micron MT48LC8M16A2TG-75 */
 107                .name           = "MT48LC8M16A2TG-75",
 108                .rows           = 12,
 109                .tck            = 8,
 110                .trcd           = 20,
 111                .trp            = 20,
 112                .twr            = 8,
 113                .refresh        = 64000,
 114                .cas_latency    = 3,
 115        },
 116};
 117
 118static struct sdram_params sdram_params;
 119
 120/*
 121 * Given a period in ns and frequency in khz, calculate the number of
 122 * cycles of frequency in period.  Note that we round up to the next
 123 * cycle, even if we are only slightly over.
 124 */
 125static inline u_int ns_to_cycles(u_int ns, u_int khz)
 126{
 127        return (ns * khz + 999999) / 1000000;
 128}
 129
 130/*
 131 * Create the MDCAS register bit pattern.
 132 */
 133static inline void set_mdcas(u_int *mdcas, int delayed, u_int rcd)
 134{
 135        u_int shift;
 136
 137        rcd = 2 * rcd - 1;
 138        shift = delayed + 1 + rcd;
 139
 140        mdcas[0]  = (1 << rcd) - 1;
 141        mdcas[0] |= 0x55555555 << shift;
 142        mdcas[1]  = mdcas[2] = 0x55555555 << (shift & 1);
 143}
 144
 145static void
 146sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
 147                       struct sdram_params *sdram)
 148{
 149        u_int mem_khz, sd_khz, trp, twr;
 150
 151        mem_khz = cpu_khz / 2;
 152        sd_khz = mem_khz;
 153
 154        /*
 155         * If SDCLK would invalidate the SDRAM timings,
 156         * run SDCLK at half speed.
 157         *
 158         * CPU steppings prior to B2 must either run the memory at
 159         * half speed or use delayed read latching (errata 13).
 160         */
 161        if ((ns_to_cycles(sdram->tck, sd_khz) > 1) ||
 162            (CPU_REVISION < CPU_SA1110_B2 && sd_khz < 62000))
 163                sd_khz /= 2;
 164
 165        sd->mdcnfg = MDCNFG & 0x007f007f;
 166
 167        twr = ns_to_cycles(sdram->twr, mem_khz);
 168
 169        /* trp should always be >1 */
 170        trp = ns_to_cycles(sdram->trp, mem_khz) - 1;
 171        if (trp < 1)
 172                trp = 1;
 173
 174        sd->mdcnfg |= trp << 8;
 175        sd->mdcnfg |= trp << 24;
 176        sd->mdcnfg |= sdram->cas_latency << 12;
 177        sd->mdcnfg |= sdram->cas_latency << 28;
 178        sd->mdcnfg |= twr << 14;
 179        sd->mdcnfg |= twr << 30;
 180
 181        sd->mdrefr = MDREFR & 0xffbffff0;
 182        sd->mdrefr |= 7;
 183
 184        if (sd_khz != mem_khz)
 185                sd->mdrefr |= MDREFR_K1DB2;
 186
 187        /* initial number of '1's in MDCAS + 1 */
 188        set_mdcas(sd->mdcas, sd_khz >= 62000,
 189                ns_to_cycles(sdram->trcd, mem_khz));
 190
 191#ifdef DEBUG
 192        printk(KERN_DEBUG "MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
 193                sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1],
 194                sd->mdcas[2]);
 195#endif
 196}
 197
 198/*
 199 * Set the SDRAM refresh rate.
 200 */
 201static inline void sdram_set_refresh(u_int dri)
 202{
 203        MDREFR = (MDREFR & 0xffff000f) | (dri << 4);
 204        (void) MDREFR;
 205}
 206
 207/*
 208 * Update the refresh period.  We do this such that we always refresh
 209 * the SDRAMs within their permissible period.  The refresh period is
 210 * always a multiple of the memory clock (fixed at cpu_clock / 2).
 211 *
 212 * FIXME: we don't currently take account of burst accesses here,
 213 * but neither do Intels DM nor Angel.
 214 */
 215static void
 216sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
 217{
 218        u_int ns_row = (sdram->refresh * 1000) >> sdram->rows;
 219        u_int dri = ns_to_cycles(ns_row, cpu_khz / 2) / 32;
 220
 221#ifdef DEBUG
 222        mdelay(250);
 223        printk(KERN_DEBUG "new dri value = %d\n", dri);
 224#endif
 225
 226        sdram_set_refresh(dri);
 227}
 228
 229/*
 230 * Ok, set the CPU frequency.
 231 */
 232static int sa1110_target(struct cpufreq_policy *policy,
 233                         unsigned int target_freq,
 234                         unsigned int relation)
 235{
 236        struct sdram_params *sdram = &sdram_params;
 237        struct cpufreq_freqs freqs;
 238        struct sdram_info sd;
 239        unsigned long flags;
 240        unsigned int ppcr, unused;
 241
 242        switch (relation) {
 243        case CPUFREQ_RELATION_L:
 244                ppcr = sa11x0_freq_to_ppcr(target_freq);
 245                if (sa11x0_ppcr_to_freq(ppcr) > policy->max)
 246                        ppcr--;
 247                break;
 248        case CPUFREQ_RELATION_H:
 249                ppcr = sa11x0_freq_to_ppcr(target_freq);
 250                if (ppcr && (sa11x0_ppcr_to_freq(ppcr) > target_freq) &&
 251                    (sa11x0_ppcr_to_freq(ppcr-1) >= policy->min))
 252                        ppcr--;
 253                break;
 254        default:
 255                return -EINVAL;
 256        }
 257
 258        freqs.old = sa11x0_getspeed(0);
 259        freqs.new = sa11x0_ppcr_to_freq(ppcr);
 260
 261        sdram_calculate_timing(&sd, freqs.new, sdram);
 262
 263#if 0
 264        /*
 265         * These values are wrong according to the SA1110 documentation
 266         * and errata, but they seem to work.  Need to get a storage
 267         * scope on to the SDRAM signals to work out why.
 268         */
 269        if (policy->max < 147500) {
 270                sd.mdrefr |= MDREFR_K1DB2;
 271                sd.mdcas[0] = 0xaaaaaa7f;
 272        } else {
 273                sd.mdrefr &= ~MDREFR_K1DB2;
 274                sd.mdcas[0] = 0xaaaaaa9f;
 275        }
 276        sd.mdcas[1] = 0xaaaaaaaa;
 277        sd.mdcas[2] = 0xaaaaaaaa;
 278#endif
 279
 280        cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
 281
 282        /*
 283         * The clock could be going away for some time.  Set the SDRAMs
 284         * to refresh rapidly (every 64 memory clock cycles).  To get
 285         * through the whole array, we need to wait 262144 mclk cycles.
 286         * We wait 20ms to be safe.
 287         */
 288        sdram_set_refresh(2);
 289        if (!irqs_disabled())
 290                msleep(20);
 291        else
 292                mdelay(20);
 293
 294        /*
 295         * Reprogram the DRAM timings with interrupts disabled, and
 296         * ensure that we are doing this within a complete cache line.
 297         * This means that we won't access SDRAM for the duration of
 298         * the programming.
 299         */
 300        local_irq_save(flags);
 301        asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 302        udelay(10);
 303        __asm__ __volatile__("\n\
 304                b       2f                                      \n\
 305                .align  5                                       \n\
 3061:              str     %3, [%1, #0]            @ MDCNFG        \n\
 307                str     %4, [%1, #28]           @ MDREFR        \n\
 308                str     %5, [%1, #4]            @ MDCAS0        \n\
 309                str     %6, [%1, #8]            @ MDCAS1        \n\
 310                str     %7, [%1, #12]           @ MDCAS2        \n\
 311                str     %8, [%2, #0]            @ PPCR          \n\
 312                ldr     %0, [%1, #0]                            \n\
 313                b       3f                                      \n\
 3142:              b       1b                                      \n\
 3153:              nop                                             \n\
 316                nop"
 317                : "=&r" (unused)
 318                : "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),
 319                  "r" (sd.mdrefr), "r" (sd.mdcas[0]),
 320                  "r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr));
 321        local_irq_restore(flags);
 322
 323        /*
 324         * Now, return the SDRAM refresh back to normal.
 325         */
 326        sdram_update_refresh(freqs.new, sdram);
 327
 328        cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
 329
 330        return 0;
 331}
 332
 333static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
 334{
 335        if (policy->cpu != 0)
 336                return -EINVAL;
 337        policy->cur = policy->min = policy->max = sa11x0_getspeed(0);
 338        policy->cpuinfo.min_freq = 59000;
 339        policy->cpuinfo.max_freq = 287000;
 340        policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
 341        return 0;
 342}
 343
 344/* sa1110_driver needs __refdata because it must remain after init registers
 345 * it with cpufreq_register_driver() */
 346static struct cpufreq_driver sa1110_driver __refdata = {
 347        .flags          = CPUFREQ_STICKY,
 348        .verify         = sa11x0_verify_speed,
 349        .target         = sa1110_target,
 350        .get            = sa11x0_getspeed,
 351        .init           = sa1110_cpu_init,
 352        .name           = "sa1110",
 353};
 354
 355static struct sdram_params *sa1110_find_sdram(const char *name)
 356{
 357        struct sdram_params *sdram;
 358
 359        for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl);
 360             sdram++)
 361                if (strcmp(name, sdram->name) == 0)
 362                        return sdram;
 363
 364        return NULL;
 365}
 366
 367static char sdram_name[16];
 368
 369static int __init sa1110_clk_init(void)
 370{
 371        struct sdram_params *sdram;
 372        const char *name = sdram_name;
 373
 374        if (!cpu_is_sa1110())
 375                return -ENODEV;
 376
 377        if (!name[0]) {
 378                if (machine_is_assabet())
 379                        name = "TC59SM716-CL3";
 380                if (machine_is_pt_system3())
 381                        name = "K4S641632D";
 382                if (machine_is_h3100())
 383                        name = "KM416S4030CT";
 384                if (machine_is_jornada720())
 385                        name = "K4S281632B-1H";
 386                if (machine_is_nanoengine())
 387                        name = "MT48LC8M16A2TG-75";
 388        }
 389
 390        sdram = sa1110_find_sdram(name);
 391        if (sdram) {
 392                printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
 393                        " twr: %d refresh: %d cas_latency: %d\n",
 394                        sdram->tck, sdram->trcd, sdram->trp,
 395                        sdram->twr, sdram->refresh, sdram->cas_latency);
 396
 397                memcpy(&sdram_params, sdram, sizeof(sdram_params));
 398
 399                return cpufreq_register_driver(&sa1110_driver);
 400        }
 401
 402        return 0;
 403}
 404
 405module_param_string(sdram, sdram_name, sizeof(sdram_name), 0);
 406arch_initcall(sa1110_clk_init);
 407
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