linux/drivers/clocksource/tcb_clksrc.c
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   1#include <linux/init.h>
   2#include <linux/clocksource.h>
   3#include <linux/clockchips.h>
   4#include <linux/interrupt.h>
   5#include <linux/irq.h>
   6
   7#include <linux/clk.h>
   8#include <linux/err.h>
   9#include <linux/ioport.h>
  10#include <linux/io.h>
  11#include <linux/platform_device.h>
  12#include <linux/atmel_tc.h>
  13
  14
  15/*
  16 * We're configured to use a specific TC block, one that's not hooked
  17 * up to external hardware, to provide a time solution:
  18 *
  19 *   - Two channels combine to create a free-running 32 bit counter
  20 *     with a base rate of 5+ MHz, packaged as a clocksource (with
  21 *     resolution better than 200 nsec).
  22 *   - Some chips support 32 bit counter. A single channel is used for
  23 *     this 32 bit free-running counter. the second channel is not used.
  24 *
  25 *   - The third channel may be used to provide a 16-bit clockevent
  26 *     source, used in either periodic or oneshot mode.  This runs
  27 *     at 32 KiHZ, and can handle delays of up to two seconds.
  28 *
  29 * A boot clocksource and clockevent source are also currently needed,
  30 * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
  31 * this code can be used when init_timers() is called, well before most
  32 * devices are set up.  (Some low end AT91 parts, which can run uClinux,
  33 * have only the timers in one TC block... they currently don't support
  34 * the tclib code, because of that initialization issue.)
  35 *
  36 * REVISIT behavior during system suspend states... we should disable
  37 * all clocks and save the power.  Easily done for clockevent devices,
  38 * but clocksources won't necessarily get the needed notifications.
  39 * For deeper system sleep states, this will be mandatory...
  40 */
  41
  42static void __iomem *tcaddr;
  43
  44static cycle_t tc_get_cycles(struct clocksource *cs)
  45{
  46        unsigned long   flags;
  47        u32             lower, upper;
  48
  49        raw_local_irq_save(flags);
  50        do {
  51                upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
  52                lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
  53        } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
  54
  55        raw_local_irq_restore(flags);
  56        return (upper << 16) | lower;
  57}
  58
  59static cycle_t tc_get_cycles32(struct clocksource *cs)
  60{
  61        return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
  62}
  63
  64static struct clocksource clksrc = {
  65        .name           = "tcb_clksrc",
  66        .rating         = 200,
  67        .read           = tc_get_cycles,
  68        .mask           = CLOCKSOURCE_MASK(32),
  69        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  70};
  71
  72#ifdef CONFIG_GENERIC_CLOCKEVENTS
  73
  74struct tc_clkevt_device {
  75        struct clock_event_device       clkevt;
  76        struct clk                      *clk;
  77        void __iomem                    *regs;
  78};
  79
  80static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
  81{
  82        return container_of(clkevt, struct tc_clkevt_device, clkevt);
  83}
  84
  85/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
  86 * because using one of the divided clocks would usually mean the
  87 * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
  88 *
  89 * A divided clock could be good for high resolution timers, since
  90 * 30.5 usec resolution can seem "low".
  91 */
  92static u32 timer_clock;
  93
  94static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
  95{
  96        struct tc_clkevt_device *tcd = to_tc_clkevt(d);
  97        void __iomem            *regs = tcd->regs;
  98
  99        if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
 100                        || tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
 101                __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
 102                __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
 103                clk_disable(tcd->clk);
 104        }
 105
 106        switch (m) {
 107
 108        /* By not making the gentime core emulate periodic mode on top
 109         * of oneshot, we get lower overhead and improved accuracy.
 110         */
 111        case CLOCK_EVT_MODE_PERIODIC:
 112                clk_enable(tcd->clk);
 113
 114                /* slow clock, count up to RC, then irq and restart */
 115                __raw_writel(timer_clock
 116                                | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
 117                                regs + ATMEL_TC_REG(2, CMR));
 118                __raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
 119
 120                /* Enable clock and interrupts on RC compare */
 121                __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 122
 123                /* go go gadget! */
 124                __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
 125                                regs + ATMEL_TC_REG(2, CCR));
 126                break;
 127
 128        case CLOCK_EVT_MODE_ONESHOT:
 129                clk_enable(tcd->clk);
 130
 131                /* slow clock, count up to RC, then irq and stop */
 132                __raw_writel(timer_clock | ATMEL_TC_CPCSTOP
 133                                | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
 134                                regs + ATMEL_TC_REG(2, CMR));
 135                __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 136
 137                /* set_next_event() configures and starts the timer */
 138                break;
 139
 140        default:
 141                break;
 142        }
 143}
 144
 145static int tc_next_event(unsigned long delta, struct clock_event_device *d)
 146{
 147        __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
 148
 149        /* go go gadget! */
 150        __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
 151                        tcaddr + ATMEL_TC_REG(2, CCR));
 152        return 0;
 153}
 154
 155static struct tc_clkevt_device clkevt = {
 156        .clkevt = {
 157                .name           = "tc_clkevt",
 158                .features       = CLOCK_EVT_FEAT_PERIODIC
 159                                        | CLOCK_EVT_FEAT_ONESHOT,
 160                /* Should be lower than at91rm9200's system timer */
 161                .rating         = 125,
 162                .set_next_event = tc_next_event,
 163                .set_mode       = tc_mode,
 164        },
 165};
 166
 167static irqreturn_t ch2_irq(int irq, void *handle)
 168{
 169        struct tc_clkevt_device *dev = handle;
 170        unsigned int            sr;
 171
 172        sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
 173        if (sr & ATMEL_TC_CPCS) {
 174                dev->clkevt.event_handler(&dev->clkevt);
 175                return IRQ_HANDLED;
 176        }
 177
 178        return IRQ_NONE;
 179}
 180
 181static struct irqaction tc_irqaction = {
 182        .name           = "tc_clkevt",
 183        .flags          = IRQF_TIMER | IRQF_DISABLED,
 184        .handler        = ch2_irq,
 185};
 186
 187static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
 188{
 189        struct clk *t2_clk = tc->clk[2];
 190        int irq = tc->irq[2];
 191
 192        clkevt.regs = tc->regs;
 193        clkevt.clk = t2_clk;
 194        tc_irqaction.dev_id = &clkevt;
 195
 196        timer_clock = clk32k_divisor_idx;
 197
 198        clkevt.clkevt.cpumask = cpumask_of(0);
 199
 200        clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);
 201
 202        setup_irq(irq, &tc_irqaction);
 203}
 204
 205#else /* !CONFIG_GENERIC_CLOCKEVENTS */
 206
 207static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
 208{
 209        /* NOTHING */
 210}
 211
 212#endif
 213
 214static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
 215{
 216        /* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
 217        __raw_writel(mck_divisor_idx                    /* likely divide-by-8 */
 218                        | ATMEL_TC_WAVE
 219                        | ATMEL_TC_WAVESEL_UP           /* free-run */
 220                        | ATMEL_TC_ACPA_SET             /* TIOA0 rises at 0 */
 221                        | ATMEL_TC_ACPC_CLEAR,          /* (duty cycle 50%) */
 222                        tcaddr + ATMEL_TC_REG(0, CMR));
 223        __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
 224        __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
 225        __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));      /* no irqs */
 226        __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 227
 228        /* channel 1:  waveform mode, input TIOA0 */
 229        __raw_writel(ATMEL_TC_XC1                       /* input: TIOA0 */
 230                        | ATMEL_TC_WAVE
 231                        | ATMEL_TC_WAVESEL_UP,          /* free-run */
 232                        tcaddr + ATMEL_TC_REG(1, CMR));
 233        __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));      /* no irqs */
 234        __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
 235
 236        /* chain channel 0 to channel 1*/
 237        __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
 238        /* then reset all the timers */
 239        __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 240}
 241
 242static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
 243{
 244        /* channel 0:  waveform mode, input mclk/8 */
 245        __raw_writel(mck_divisor_idx                    /* likely divide-by-8 */
 246                        | ATMEL_TC_WAVE
 247                        | ATMEL_TC_WAVESEL_UP,          /* free-run */
 248                        tcaddr + ATMEL_TC_REG(0, CMR));
 249        __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));      /* no irqs */
 250        __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 251
 252        /* then reset all the timers */
 253        __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 254}
 255
 256static int __init tcb_clksrc_init(void)
 257{
 258        static char bootinfo[] __initdata
 259                = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
 260
 261        struct platform_device *pdev;
 262        struct atmel_tc *tc;
 263        struct clk *t0_clk;
 264        u32 rate, divided_rate = 0;
 265        int best_divisor_idx = -1;
 266        int clk32k_divisor_idx = -1;
 267        int i;
 268
 269        tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK, clksrc.name);
 270        if (!tc) {
 271                pr_debug("can't alloc TC for clocksource\n");
 272                return -ENODEV;
 273        }
 274        tcaddr = tc->regs;
 275        pdev = tc->pdev;
 276
 277        t0_clk = tc->clk[0];
 278        clk_enable(t0_clk);
 279
 280        /* How fast will we be counting?  Pick something over 5 MHz.  */
 281        rate = (u32) clk_get_rate(t0_clk);
 282        for (i = 0; i < 5; i++) {
 283                unsigned divisor = atmel_tc_divisors[i];
 284                unsigned tmp;
 285
 286                /* remember 32 KiHz clock for later */
 287                if (!divisor) {
 288                        clk32k_divisor_idx = i;
 289                        continue;
 290                }
 291
 292                tmp = rate / divisor;
 293                pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
 294                if (best_divisor_idx > 0) {
 295                        if (tmp < 5 * 1000 * 1000)
 296                                continue;
 297                }
 298                divided_rate = tmp;
 299                best_divisor_idx = i;
 300        }
 301
 302
 303        printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
 304                        divided_rate / 1000000,
 305                        ((divided_rate + 500000) % 1000000) / 1000);
 306
 307        if (tc->tcb_config && tc->tcb_config->counter_width == 32) {
 308                /* use apropriate function to read 32 bit counter */
 309                clksrc.read = tc_get_cycles32;
 310                /* setup ony channel 0 */
 311                tcb_setup_single_chan(tc, best_divisor_idx);
 312        } else {
 313                /* tclib will give us three clocks no matter what the
 314                 * underlying platform supports.
 315                 */
 316                clk_enable(tc->clk[1]);
 317                /* setup both channel 0 & 1 */
 318                tcb_setup_dual_chan(tc, best_divisor_idx);
 319        }
 320
 321        /* and away we go! */
 322        clocksource_register_hz(&clksrc, divided_rate);
 323
 324        /* channel 2:  periodic and oneshot timer support */
 325        setup_clkevents(tc, clk32k_divisor_idx);
 326
 327        return 0;
 328}
 329arch_initcall(tcb_clksrc_init);
 330
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