linux/drivers/clocksource/nomadik-mtu.c
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   1/*
   2 * Copyright (C) 2008 STMicroelectronics
   3 * Copyright (C) 2010 Alessandro Rubini
   4 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2, as
   8 * published by the Free Software Foundation.
   9 */
  10#include <linux/init.h>
  11#include <linux/interrupt.h>
  12#include <linux/irq.h>
  13#include <linux/io.h>
  14#include <linux/clockchips.h>
  15#include <linux/clocksource.h>
  16#include <linux/of_address.h>
  17#include <linux/of_irq.h>
  18#include <linux/of_platform.h>
  19#include <linux/clk.h>
  20#include <linux/jiffies.h>
  21#include <linux/delay.h>
  22#include <linux/err.h>
  23#include <linux/platform_data/clocksource-nomadik-mtu.h>
  24#include <linux/sched_clock.h>
  25#include <asm/mach/time.h>
  26
  27/*
  28 * The MTU device hosts four different counters, with 4 set of
  29 * registers. These are register names.
  30 */
  31
  32#define MTU_IMSC        0x00    /* Interrupt mask set/clear */
  33#define MTU_RIS         0x04    /* Raw interrupt status */
  34#define MTU_MIS         0x08    /* Masked interrupt status */
  35#define MTU_ICR         0x0C    /* Interrupt clear register */
  36
  37/* per-timer registers take 0..3 as argument */
  38#define MTU_LR(x)       (0x10 + 0x10 * (x) + 0x00)      /* Load value */
  39#define MTU_VAL(x)      (0x10 + 0x10 * (x) + 0x04)      /* Current value */
  40#define MTU_CR(x)       (0x10 + 0x10 * (x) + 0x08)      /* Control reg */
  41#define MTU_BGLR(x)     (0x10 + 0x10 * (x) + 0x0c)      /* At next overflow */
  42
  43/* bits for the control register */
  44#define MTU_CRn_ENA             0x80
  45#define MTU_CRn_PERIODIC        0x40    /* if 0 = free-running */
  46#define MTU_CRn_PRESCALE_MASK   0x0c
  47#define MTU_CRn_PRESCALE_1              0x00
  48#define MTU_CRn_PRESCALE_16             0x04
  49#define MTU_CRn_PRESCALE_256            0x08
  50#define MTU_CRn_32BITS          0x02
  51#define MTU_CRn_ONESHOT         0x01    /* if 0 = wraps reloading from BGLR*/
  52
  53/* Other registers are usual amba/primecell registers, currently not used */
  54#define MTU_ITCR        0xff0
  55#define MTU_ITOP        0xff4
  56
  57#define MTU_PERIPH_ID0  0xfe0
  58#define MTU_PERIPH_ID1  0xfe4
  59#define MTU_PERIPH_ID2  0xfe8
  60#define MTU_PERIPH_ID3  0xfeC
  61
  62#define MTU_PCELL0      0xff0
  63#define MTU_PCELL1      0xff4
  64#define MTU_PCELL2      0xff8
  65#define MTU_PCELL3      0xffC
  66
  67static void __iomem *mtu_base;
  68static bool clkevt_periodic;
  69static u32 clk_prescale;
  70static u32 nmdk_cycle;          /* write-once */
  71static struct delay_timer mtu_delay_timer;
  72
  73#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
  74/*
  75 * Override the global weak sched_clock symbol with this
  76 * local implementation which uses the clocksource to get some
  77 * better resolution when scheduling the kernel.
  78 */
  79static u32 notrace nomadik_read_sched_clock(void)
  80{
  81        if (unlikely(!mtu_base))
  82                return 0;
  83
  84        return -readl(mtu_base + MTU_VAL(0));
  85}
  86#endif
  87
  88static unsigned long nmdk_timer_read_current_timer(void)
  89{
  90        return ~readl_relaxed(mtu_base + MTU_VAL(0));
  91}
  92
  93/* Clockevent device: use one-shot mode */
  94static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
  95{
  96        writel(1 << 1, mtu_base + MTU_IMSC);
  97        writel(evt, mtu_base + MTU_LR(1));
  98        /* Load highest value, enable device, enable interrupts */
  99        writel(MTU_CRn_ONESHOT | clk_prescale |
 100               MTU_CRn_32BITS | MTU_CRn_ENA,
 101               mtu_base + MTU_CR(1));
 102
 103        return 0;
 104}
 105
 106void nmdk_clkevt_reset(void)
 107{
 108        if (clkevt_periodic) {
 109                /* Timer: configure load and background-load, and fire it up */
 110                writel(nmdk_cycle, mtu_base + MTU_LR(1));
 111                writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
 112
 113                writel(MTU_CRn_PERIODIC | clk_prescale |
 114                       MTU_CRn_32BITS | MTU_CRn_ENA,
 115                       mtu_base + MTU_CR(1));
 116                writel(1 << 1, mtu_base + MTU_IMSC);
 117        } else {
 118                /* Generate an interrupt to start the clockevent again */
 119                (void) nmdk_clkevt_next(nmdk_cycle, NULL);
 120        }
 121}
 122
 123static void nmdk_clkevt_mode(enum clock_event_mode mode,
 124                             struct clock_event_device *dev)
 125{
 126        switch (mode) {
 127        case CLOCK_EVT_MODE_PERIODIC:
 128                clkevt_periodic = true;
 129                nmdk_clkevt_reset();
 130                break;
 131        case CLOCK_EVT_MODE_ONESHOT:
 132                clkevt_periodic = false;
 133                break;
 134        case CLOCK_EVT_MODE_SHUTDOWN:
 135        case CLOCK_EVT_MODE_UNUSED:
 136                writel(0, mtu_base + MTU_IMSC);
 137                /* disable timer */
 138                writel(0, mtu_base + MTU_CR(1));
 139                /* load some high default value */
 140                writel(0xffffffff, mtu_base + MTU_LR(1));
 141                break;
 142        case CLOCK_EVT_MODE_RESUME:
 143                break;
 144        }
 145}
 146
 147void nmdk_clksrc_reset(void)
 148{
 149        /* Disable */
 150        writel(0, mtu_base + MTU_CR(0));
 151
 152        /* ClockSource: configure load and background-load, and fire it up */
 153        writel(nmdk_cycle, mtu_base + MTU_LR(0));
 154        writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
 155
 156        writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
 157               mtu_base + MTU_CR(0));
 158}
 159
 160static void nmdk_clkevt_resume(struct clock_event_device *cedev)
 161{
 162        nmdk_clkevt_reset();
 163        nmdk_clksrc_reset();
 164}
 165
 166static struct clock_event_device nmdk_clkevt = {
 167        .name           = "mtu_1",
 168        .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC |
 169                          CLOCK_EVT_FEAT_DYNIRQ,
 170        .rating         = 200,
 171        .set_mode       = nmdk_clkevt_mode,
 172        .set_next_event = nmdk_clkevt_next,
 173        .resume         = nmdk_clkevt_resume,
 174};
 175
 176/*
 177 * IRQ Handler for timer 1 of the MTU block.
 178 */
 179static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
 180{
 181        struct clock_event_device *evdev = dev_id;
 182
 183        writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
 184        evdev->event_handler(evdev);
 185        return IRQ_HANDLED;
 186}
 187
 188static struct irqaction nmdk_timer_irq = {
 189        .name           = "Nomadik Timer Tick",
 190        .flags          = IRQF_DISABLED | IRQF_TIMER,
 191        .handler        = nmdk_timer_interrupt,
 192        .dev_id         = &nmdk_clkevt,
 193};
 194
 195static void __init __nmdk_timer_init(void __iomem *base, int irq,
 196                                     struct clk *pclk, struct clk *clk)
 197{
 198        unsigned long rate;
 199
 200        mtu_base = base;
 201
 202        BUG_ON(clk_prepare_enable(pclk));
 203        BUG_ON(clk_prepare_enable(clk));
 204
 205        /*
 206         * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
 207         * for ux500.
 208         * Use a divide-by-16 counter if the tick rate is more than 32MHz.
 209         * At 32 MHz, the timer (with 32 bit counter) can be programmed
 210         * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
 211         * with 16 gives too low timer resolution.
 212         */
 213        rate = clk_get_rate(clk);
 214        if (rate > 32000000) {
 215                rate /= 16;
 216                clk_prescale = MTU_CRn_PRESCALE_16;
 217        } else {
 218                clk_prescale = MTU_CRn_PRESCALE_1;
 219        }
 220
 221        /* Cycles for periodic mode */
 222        nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);
 223
 224
 225        /* Timer 0 is the free running clocksource */
 226        nmdk_clksrc_reset();
 227
 228        if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
 229                        rate, 200, 32, clocksource_mmio_readl_down))
 230                pr_err("timer: failed to initialize clock source %s\n",
 231                       "mtu_0");
 232
 233#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
 234        setup_sched_clock(nomadik_read_sched_clock, 32, rate);
 235#endif
 236
 237        /* Timer 1 is used for events, register irq and clockevents */
 238        setup_irq(irq, &nmdk_timer_irq);
 239        nmdk_clkevt.cpumask = cpumask_of(0);
 240        nmdk_clkevt.irq = irq;
 241        clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
 242
 243        mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
 244        mtu_delay_timer.freq = rate;
 245        register_current_timer_delay(&mtu_delay_timer);
 246}
 247
 248void __init nmdk_timer_init(void __iomem *base, int irq)
 249{
 250        struct clk *clk0, *pclk0;
 251
 252        pclk0 = clk_get_sys("mtu0", "apb_pclk");
 253        BUG_ON(IS_ERR(pclk0));
 254        clk0 = clk_get_sys("mtu0", NULL);
 255        BUG_ON(IS_ERR(clk0));
 256
 257        __nmdk_timer_init(base, irq, pclk0, clk0);
 258}
 259
 260static void __init nmdk_timer_of_init(struct device_node *node)
 261{
 262        struct clk *pclk;
 263        struct clk *clk;
 264        void __iomem *base;
 265        int irq;
 266
 267        base = of_iomap(node, 0);
 268        if (!base)
 269                panic("Can't remap registers");
 270
 271        pclk = of_clk_get_by_name(node, "apb_pclk");
 272        if (IS_ERR(pclk))
 273                panic("could not get apb_pclk");
 274
 275        clk = of_clk_get_by_name(node, "timclk");
 276        if (IS_ERR(clk))
 277                panic("could not get timclk");
 278
 279        irq = irq_of_parse_and_map(node, 0);
 280        if (irq <= 0)
 281                panic("Can't parse IRQ");
 282
 283        __nmdk_timer_init(base, irq, pclk, clk);
 284}
 285CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
 286                       nmdk_timer_of_init);
 287
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