linux/drivers/clocksource/cadence_ttc_timer.c
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   1/*
   2 * This file contains driver for the Cadence Triple Timer Counter Rev 06
   3 *
   4 *  Copyright (C) 2011-2013 Xilinx
   5 *
   6 * based on arch/mips/kernel/time.c timer driver
   7 *
   8 * This software is licensed under the terms of the GNU General Public
   9 * License version 2, as published by the Free Software Foundation, and
  10 * may be copied, distributed, and modified under those terms.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 */
  17
  18#include <linux/clk.h>
  19#include <linux/interrupt.h>
  20#include <linux/clockchips.h>
  21#include <linux/of_address.h>
  22#include <linux/of_irq.h>
  23#include <linux/slab.h>
  24#include <linux/sched_clock.h>
  25
  26/*
  27 * This driver configures the 2 16-bit count-up timers as follows:
  28 *
  29 * T1: Timer 1, clocksource for generic timekeeping
  30 * T2: Timer 2, clockevent source for hrtimers
  31 * T3: Timer 3, <unused>
  32 *
  33 * The input frequency to the timer module for emulation is 2.5MHz which is
  34 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
  35 * the timers are clocked at 78.125KHz (12.8 us resolution).
  36
  37 * The input frequency to the timer module in silicon is configurable and
  38 * obtained from device tree. The pre-scaler of 32 is used.
  39 */
  40
  41/*
  42 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
  43 * and use same offsets for Timer 2
  44 */
  45#define TTC_CLK_CNTRL_OFFSET            0x00 /* Clock Control Reg, RW */
  46#define TTC_CNT_CNTRL_OFFSET            0x0C /* Counter Control Reg, RW */
  47#define TTC_COUNT_VAL_OFFSET            0x18 /* Counter Value Reg, RO */
  48#define TTC_INTR_VAL_OFFSET             0x24 /* Interval Count Reg, RW */
  49#define TTC_ISR_OFFSET          0x54 /* Interrupt Status Reg, RO */
  50#define TTC_IER_OFFSET          0x60 /* Interrupt Enable Reg, RW */
  51
  52#define TTC_CNT_CNTRL_DISABLE_MASK      0x1
  53
  54#define TTC_CLK_CNTRL_CSRC_MASK         (1 << 5)        /* clock source */
  55
  56/*
  57 * Setup the timers to use pre-scaling, using a fixed value for now that will
  58 * work across most input frequency, but it may need to be more dynamic
  59 */
  60#define PRESCALE_EXPONENT       11      /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
  61#define PRESCALE                2048    /* The exponent must match this */
  62#define CLK_CNTRL_PRESCALE      ((PRESCALE_EXPONENT - 1) << 1)
  63#define CLK_CNTRL_PRESCALE_EN   1
  64#define CNT_CNTRL_RESET         (1 << 4)
  65
  66/**
  67 * struct ttc_timer - This definition defines local timer structure
  68 *
  69 * @base_addr:  Base address of timer
  70 * @clk:        Associated clock source
  71 * @clk_rate_change_nb  Notifier block for clock rate changes
  72 */
  73struct ttc_timer {
  74        void __iomem *base_addr;
  75        struct clk *clk;
  76        struct notifier_block clk_rate_change_nb;
  77};
  78
  79#define to_ttc_timer(x) \
  80                container_of(x, struct ttc_timer, clk_rate_change_nb)
  81
  82struct ttc_timer_clocksource {
  83        struct ttc_timer        ttc;
  84        struct clocksource      cs;
  85};
  86
  87#define to_ttc_timer_clksrc(x) \
  88                container_of(x, struct ttc_timer_clocksource, cs)
  89
  90struct ttc_timer_clockevent {
  91        struct ttc_timer                ttc;
  92        struct clock_event_device       ce;
  93};
  94
  95#define to_ttc_timer_clkevent(x) \
  96                container_of(x, struct ttc_timer_clockevent, ce)
  97
  98static void __iomem *ttc_sched_clock_val_reg;
  99
 100/**
 101 * ttc_set_interval - Set the timer interval value
 102 *
 103 * @timer:      Pointer to the timer instance
 104 * @cycles:     Timer interval ticks
 105 **/
 106static void ttc_set_interval(struct ttc_timer *timer,
 107                                        unsigned long cycles)
 108{
 109        u32 ctrl_reg;
 110
 111        /* Disable the counter, set the counter value  and re-enable counter */
 112        ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 113        ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
 114        __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 115
 116        __raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
 117
 118        /*
 119         * Reset the counter (0x10) so that it starts from 0, one-shot
 120         * mode makes this needed for timing to be right.
 121         */
 122        ctrl_reg |= CNT_CNTRL_RESET;
 123        ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
 124        __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 125}
 126
 127/**
 128 * ttc_clock_event_interrupt - Clock event timer interrupt handler
 129 *
 130 * @irq:        IRQ number of the Timer
 131 * @dev_id:     void pointer to the ttc_timer instance
 132 *
 133 * returns: Always IRQ_HANDLED - success
 134 **/
 135static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
 136{
 137        struct ttc_timer_clockevent *ttce = dev_id;
 138        struct ttc_timer *timer = &ttce->ttc;
 139
 140        /* Acknowledge the interrupt and call event handler */
 141        __raw_readl(timer->base_addr + TTC_ISR_OFFSET);
 142
 143        ttce->ce.event_handler(&ttce->ce);
 144
 145        return IRQ_HANDLED;
 146}
 147
 148/**
 149 * __ttc_clocksource_read - Reads the timer counter register
 150 *
 151 * returns: Current timer counter register value
 152 **/
 153static cycle_t __ttc_clocksource_read(struct clocksource *cs)
 154{
 155        struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
 156
 157        return (cycle_t)__raw_readl(timer->base_addr +
 158                                TTC_COUNT_VAL_OFFSET);
 159}
 160
 161static u32 notrace ttc_sched_clock_read(void)
 162{
 163        return __raw_readl(ttc_sched_clock_val_reg);
 164}
 165
 166/**
 167 * ttc_set_next_event - Sets the time interval for next event
 168 *
 169 * @cycles:     Timer interval ticks
 170 * @evt:        Address of clock event instance
 171 *
 172 * returns: Always 0 - success
 173 **/
 174static int ttc_set_next_event(unsigned long cycles,
 175                                        struct clock_event_device *evt)
 176{
 177        struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
 178        struct ttc_timer *timer = &ttce->ttc;
 179
 180        ttc_set_interval(timer, cycles);
 181        return 0;
 182}
 183
 184/**
 185 * ttc_set_mode - Sets the mode of timer
 186 *
 187 * @mode:       Mode to be set
 188 * @evt:        Address of clock event instance
 189 **/
 190static void ttc_set_mode(enum clock_event_mode mode,
 191                                        struct clock_event_device *evt)
 192{
 193        struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
 194        struct ttc_timer *timer = &ttce->ttc;
 195        u32 ctrl_reg;
 196
 197        switch (mode) {
 198        case CLOCK_EVT_MODE_PERIODIC:
 199                ttc_set_interval(timer,
 200                                DIV_ROUND_CLOSEST(clk_get_rate(ttce->ttc.clk),
 201                                        PRESCALE * HZ));
 202                break;
 203        case CLOCK_EVT_MODE_ONESHOT:
 204        case CLOCK_EVT_MODE_UNUSED:
 205        case CLOCK_EVT_MODE_SHUTDOWN:
 206                ctrl_reg = __raw_readl(timer->base_addr +
 207                                        TTC_CNT_CNTRL_OFFSET);
 208                ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
 209                __raw_writel(ctrl_reg,
 210                                timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 211                break;
 212        case CLOCK_EVT_MODE_RESUME:
 213                ctrl_reg = __raw_readl(timer->base_addr +
 214                                        TTC_CNT_CNTRL_OFFSET);
 215                ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
 216                __raw_writel(ctrl_reg,
 217                                timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 218                break;
 219        }
 220}
 221
 222static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
 223                unsigned long event, void *data)
 224{
 225        struct clk_notifier_data *ndata = data;
 226        struct ttc_timer *ttc = to_ttc_timer(nb);
 227        struct ttc_timer_clocksource *ttccs = container_of(ttc,
 228                        struct ttc_timer_clocksource, ttc);
 229
 230        switch (event) {
 231        case POST_RATE_CHANGE:
 232                /*
 233                 * Do whatever is necessary to maintain a proper time base
 234                 *
 235                 * I cannot find a way to adjust the currently used clocksource
 236                 * to the new frequency. __clocksource_updatefreq_hz() sounds
 237                 * good, but does not work. Not sure what's that missing.
 238                 *
 239                 * This approach works, but triggers two clocksource switches.
 240                 * The first after unregister to clocksource jiffies. And
 241                 * another one after the register to the newly registered timer.
 242                 *
 243                 * Alternatively we could 'waste' another HW timer to ping pong
 244                 * between clock sources. That would also use one register and
 245                 * one unregister call, but only trigger one clocksource switch
 246                 * for the cost of another HW timer used by the OS.
 247                 */
 248                clocksource_unregister(&ttccs->cs);
 249                clocksource_register_hz(&ttccs->cs,
 250                                ndata->new_rate / PRESCALE);
 251                /* fall through */
 252        case PRE_RATE_CHANGE:
 253        case ABORT_RATE_CHANGE:
 254        default:
 255                return NOTIFY_DONE;
 256        }
 257}
 258
 259static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
 260{
 261        struct ttc_timer_clocksource *ttccs;
 262        int err;
 263
 264        ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
 265        if (WARN_ON(!ttccs))
 266                return;
 267
 268        ttccs->ttc.clk = clk;
 269
 270        err = clk_prepare_enable(ttccs->ttc.clk);
 271        if (WARN_ON(err)) {
 272                kfree(ttccs);
 273                return;
 274        }
 275
 276        ttccs->ttc.clk_rate_change_nb.notifier_call =
 277                ttc_rate_change_clocksource_cb;
 278        ttccs->ttc.clk_rate_change_nb.next = NULL;
 279        if (clk_notifier_register(ttccs->ttc.clk,
 280                                &ttccs->ttc.clk_rate_change_nb))
 281                pr_warn("Unable to register clock notifier.\n");
 282
 283        ttccs->ttc.base_addr = base;
 284        ttccs->cs.name = "ttc_clocksource";
 285        ttccs->cs.rating = 200;
 286        ttccs->cs.read = __ttc_clocksource_read;
 287        ttccs->cs.mask = CLOCKSOURCE_MASK(16);
 288        ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
 289
 290        /*
 291         * Setup the clock source counter to be an incrementing counter
 292         * with no interrupt and it rolls over at 0xFFFF. Pre-scale
 293         * it by 32 also. Let it start running now.
 294         */
 295        __raw_writel(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);
 296        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
 297                     ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
 298        __raw_writel(CNT_CNTRL_RESET,
 299                     ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
 300
 301        err = clocksource_register_hz(&ttccs->cs,
 302                        clk_get_rate(ttccs->ttc.clk) / PRESCALE);
 303        if (WARN_ON(err)) {
 304                kfree(ttccs);
 305                return;
 306        }
 307
 308        ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
 309        setup_sched_clock(ttc_sched_clock_read, 16,
 310                        clk_get_rate(ttccs->ttc.clk) / PRESCALE);
 311}
 312
 313static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
 314                unsigned long event, void *data)
 315{
 316        struct clk_notifier_data *ndata = data;
 317        struct ttc_timer *ttc = to_ttc_timer(nb);
 318        struct ttc_timer_clockevent *ttcce = container_of(ttc,
 319                        struct ttc_timer_clockevent, ttc);
 320
 321        switch (event) {
 322        case POST_RATE_CHANGE:
 323        {
 324                unsigned long flags;
 325
 326                /*
 327                 * clockevents_update_freq should be called with IRQ disabled on
 328                 * the CPU the timer provides events for. The timer we use is
 329                 * common to both CPUs, not sure if we need to run on both
 330                 * cores.
 331                 */
 332                local_irq_save(flags);
 333                clockevents_update_freq(&ttcce->ce,
 334                                ndata->new_rate / PRESCALE);
 335                local_irq_restore(flags);
 336
 337                /* fall through */
 338        }
 339        case PRE_RATE_CHANGE:
 340        case ABORT_RATE_CHANGE:
 341        default:
 342                return NOTIFY_DONE;
 343        }
 344}
 345
 346static void __init ttc_setup_clockevent(struct clk *clk,
 347                                                void __iomem *base, u32 irq)
 348{
 349        struct ttc_timer_clockevent *ttcce;
 350        int err;
 351
 352        ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
 353        if (WARN_ON(!ttcce))
 354                return;
 355
 356        ttcce->ttc.clk = clk;
 357
 358        err = clk_prepare_enable(ttcce->ttc.clk);
 359        if (WARN_ON(err)) {
 360                kfree(ttcce);
 361                return;
 362        }
 363
 364        ttcce->ttc.clk_rate_change_nb.notifier_call =
 365                ttc_rate_change_clockevent_cb;
 366        ttcce->ttc.clk_rate_change_nb.next = NULL;
 367        if (clk_notifier_register(ttcce->ttc.clk,
 368                                &ttcce->ttc.clk_rate_change_nb))
 369                pr_warn("Unable to register clock notifier.\n");
 370
 371        ttcce->ttc.base_addr = base;
 372        ttcce->ce.name = "ttc_clockevent";
 373        ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 374        ttcce->ce.set_next_event = ttc_set_next_event;
 375        ttcce->ce.set_mode = ttc_set_mode;
 376        ttcce->ce.rating = 200;
 377        ttcce->ce.irq = irq;
 378        ttcce->ce.cpumask = cpu_possible_mask;
 379
 380        /*
 381         * Setup the clock event timer to be an interval timer which
 382         * is prescaled by 32 using the interval interrupt. Leave it
 383         * disabled for now.
 384         */
 385        __raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
 386        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
 387                     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
 388        __raw_writel(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);
 389
 390        err = request_irq(irq, ttc_clock_event_interrupt,
 391                          IRQF_DISABLED | IRQF_TIMER,
 392                          ttcce->ce.name, ttcce);
 393        if (WARN_ON(err)) {
 394                kfree(ttcce);
 395                return;
 396        }
 397
 398        clockevents_config_and_register(&ttcce->ce,
 399                        clk_get_rate(ttcce->ttc.clk) / PRESCALE, 1, 0xfffe);
 400}
 401
 402/**
 403 * ttc_timer_init - Initialize the timer
 404 *
 405 * Initializes the timer hardware and register the clock source and clock event
 406 * timers with Linux kernal timer framework
 407 */
 408static void __init ttc_timer_init(struct device_node *timer)
 409{
 410        unsigned int irq;
 411        void __iomem *timer_baseaddr;
 412        struct clk *clk_cs, *clk_ce;
 413        static int initialized;
 414        int clksel;
 415
 416        if (initialized)
 417                return;
 418
 419        initialized = 1;
 420
 421        /*
 422         * Get the 1st Triple Timer Counter (TTC) block from the device tree
 423         * and use it. Note that the event timer uses the interrupt and it's the
 424         * 2nd TTC hence the irq_of_parse_and_map(,1)
 425         */
 426        timer_baseaddr = of_iomap(timer, 0);
 427        if (!timer_baseaddr) {
 428                pr_err("ERROR: invalid timer base address\n");
 429                BUG();
 430        }
 431
 432        irq = irq_of_parse_and_map(timer, 1);
 433        if (irq <= 0) {
 434                pr_err("ERROR: invalid interrupt number\n");
 435                BUG();
 436        }
 437
 438        clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
 439        clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
 440        clk_cs = of_clk_get(timer, clksel);
 441        if (IS_ERR(clk_cs)) {
 442                pr_err("ERROR: timer input clock not found\n");
 443                BUG();
 444        }
 445
 446        clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
 447        clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
 448        clk_ce = of_clk_get(timer, clksel);
 449        if (IS_ERR(clk_ce)) {
 450                pr_err("ERROR: timer input clock not found\n");
 451                BUG();
 452        }
 453
 454        ttc_setup_clocksource(clk_cs, timer_baseaddr);
 455        ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
 456
 457        pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
 458}
 459
 460CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);
 461
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