linux/drivers/bus/mvebu-mbus.c
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   1/*
   2 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
   3 * 370/XP, Dove, Orion5x and MV78xx0)
   4 *
   5 * This file is licensed under the terms of the GNU General Public
   6 * License version 2.  This program is licensed "as is" without any
   7 * warranty of any kind, whether express or implied.
   8 *
   9 * The Marvell EBU SoCs have a configurable physical address space:
  10 * the physical address at which certain devices (PCIe, NOR, NAND,
  11 * etc.) sit can be configured. The configuration takes place through
  12 * two sets of registers:
  13 *
  14 * - One to configure the access of the CPU to the devices. Depending
  15 *   on the families, there are between 8 and 20 configurable windows,
  16 *   each can be use to create a physical memory window that maps to a
  17 *   specific device. Devices are identified by a tuple (target,
  18 *   attribute).
  19 *
  20 * - One to configure the access to the CPU to the SDRAM. There are
  21 *   either 2 (for Dove) or 4 (for other families) windows to map the
  22 *   SDRAM into the physical address space.
  23 *
  24 * This driver:
  25 *
  26 * - Reads out the SDRAM address decoding windows at initialization
  27 *   time, and fills the mvebu_mbus_dram_info structure with these
  28 *   informations. The exported function mv_mbus_dram_info() allow
  29 *   device drivers to get those informations related to the SDRAM
  30 *   address decoding windows. This is because devices also have their
  31 *   own windows (configured through registers that are part of each
  32 *   device register space), and therefore the drivers for Marvell
  33 *   devices have to configure those device -> SDRAM windows to ensure
  34 *   that DMA works properly.
  35 *
  36 * - Provides an API for platform code or device drivers to
  37 *   dynamically add or remove address decoding windows for the CPU ->
  38 *   device accesses. This API is mvebu_mbus_add_window_by_id(),
  39 *   mvebu_mbus_add_window_remap_by_id() and
  40 *   mvebu_mbus_del_window().
  41 *
  42 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
  43 *   see the list of CPU -> SDRAM windows and their configuration
  44 *   (file 'sdram') and the list of CPU -> devices windows and their
  45 *   configuration (file 'devices').
  46 */
  47
  48#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  49
  50#include <linux/kernel.h>
  51#include <linux/module.h>
  52#include <linux/init.h>
  53#include <linux/mbus.h>
  54#include <linux/io.h>
  55#include <linux/ioport.h>
  56#include <linux/of.h>
  57#include <linux/of_address.h>
  58#include <linux/debugfs.h>
  59
  60/*
  61 * DDR target is the same on all platforms.
  62 */
  63#define TARGET_DDR              0
  64
  65/*
  66 * CPU Address Decode Windows registers
  67 */
  68#define WIN_CTRL_OFF            0x0000
  69#define   WIN_CTRL_ENABLE       BIT(0)
  70#define   WIN_CTRL_TGT_MASK     0xf0
  71#define   WIN_CTRL_TGT_SHIFT    4
  72#define   WIN_CTRL_ATTR_MASK    0xff00
  73#define   WIN_CTRL_ATTR_SHIFT   8
  74#define   WIN_CTRL_SIZE_MASK    0xffff0000
  75#define   WIN_CTRL_SIZE_SHIFT   16
  76#define WIN_BASE_OFF            0x0004
  77#define   WIN_BASE_LOW          0xffff0000
  78#define   WIN_BASE_HIGH         0xf
  79#define WIN_REMAP_LO_OFF        0x0008
  80#define   WIN_REMAP_LOW         0xffff0000
  81#define WIN_REMAP_HI_OFF        0x000c
  82
  83#define ATTR_HW_COHERENCY       (0x1 << 4)
  84
  85#define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
  86#define  DDR_BASE_CS_HIGH_MASK  0xf
  87#define  DDR_BASE_CS_LOW_MASK   0xff000000
  88#define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
  89#define  DDR_SIZE_ENABLED       BIT(0)
  90#define  DDR_SIZE_CS_MASK       0x1c
  91#define  DDR_SIZE_CS_SHIFT      2
  92#define  DDR_SIZE_MASK          0xff000000
  93
  94#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
  95
  96struct mvebu_mbus_state;
  97
  98struct mvebu_mbus_soc_data {
  99        unsigned int num_wins;
 100        unsigned int num_remappable_wins;
 101        unsigned int (*win_cfg_offset)(const int win);
 102        void (*setup_cpu_target)(struct mvebu_mbus_state *s);
 103        int (*show_cpu_target)(struct mvebu_mbus_state *s,
 104                               struct seq_file *seq, void *v);
 105};
 106
 107struct mvebu_mbus_state {
 108        void __iomem *mbuswins_base;
 109        void __iomem *sdramwins_base;
 110        struct dentry *debugfs_root;
 111        struct dentry *debugfs_sdram;
 112        struct dentry *debugfs_devs;
 113        struct resource pcie_mem_aperture;
 114        struct resource pcie_io_aperture;
 115        const struct mvebu_mbus_soc_data *soc;
 116        int hw_io_coherency;
 117};
 118
 119static struct mvebu_mbus_state mbus_state;
 120
 121static struct mbus_dram_target_info mvebu_mbus_dram_info;
 122const struct mbus_dram_target_info *mv_mbus_dram_info(void)
 123{
 124        return &mvebu_mbus_dram_info;
 125}
 126EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
 127
 128/*
 129 * Functions to manipulate the address decoding windows
 130 */
 131
 132static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
 133                                   int win, int *enabled, u64 *base,
 134                                   u32 *size, u8 *target, u8 *attr,
 135                                   u64 *remap)
 136{
 137        void __iomem *addr = mbus->mbuswins_base +
 138                mbus->soc->win_cfg_offset(win);
 139        u32 basereg = readl(addr + WIN_BASE_OFF);
 140        u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
 141
 142        if (!(ctrlreg & WIN_CTRL_ENABLE)) {
 143                *enabled = 0;
 144                return;
 145        }
 146
 147        *enabled = 1;
 148        *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
 149        *base |= (basereg & WIN_BASE_LOW);
 150        *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
 151
 152        if (target)
 153                *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
 154
 155        if (attr)
 156                *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
 157
 158        if (remap) {
 159                if (win < mbus->soc->num_remappable_wins) {
 160                        u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
 161                        u32 remap_hi  = readl(addr + WIN_REMAP_HI_OFF);
 162                        *remap = ((u64)remap_hi << 32) | remap_low;
 163                } else
 164                        *remap = 0;
 165        }
 166}
 167
 168static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
 169                                      int win)
 170{
 171        void __iomem *addr;
 172
 173        addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
 174
 175        writel(0, addr + WIN_BASE_OFF);
 176        writel(0, addr + WIN_CTRL_OFF);
 177        if (win < mbus->soc->num_remappable_wins) {
 178                writel(0, addr + WIN_REMAP_LO_OFF);
 179                writel(0, addr + WIN_REMAP_HI_OFF);
 180        }
 181}
 182
 183/* Checks whether the given window number is available */
 184static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
 185                                     const int win)
 186{
 187        void __iomem *addr = mbus->mbuswins_base +
 188                mbus->soc->win_cfg_offset(win);
 189        u32 ctrl = readl(addr + WIN_CTRL_OFF);
 190        return !(ctrl & WIN_CTRL_ENABLE);
 191}
 192
 193/*
 194 * Checks whether the given (base, base+size) area doesn't overlap an
 195 * existing region
 196 */
 197static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
 198                                       phys_addr_t base, size_t size,
 199                                       u8 target, u8 attr)
 200{
 201        u64 end = (u64)base + size;
 202        int win;
 203
 204        for (win = 0; win < mbus->soc->num_wins; win++) {
 205                u64 wbase, wend;
 206                u32 wsize;
 207                u8 wtarget, wattr;
 208                int enabled;
 209
 210                mvebu_mbus_read_window(mbus, win,
 211                                       &enabled, &wbase, &wsize,
 212                                       &wtarget, &wattr, NULL);
 213
 214                if (!enabled)
 215                        continue;
 216
 217                wend = wbase + wsize;
 218
 219                /*
 220                 * Check if the current window overlaps with the
 221                 * proposed physical range
 222                 */
 223                if ((u64)base < wend && end > wbase)
 224                        return 0;
 225
 226                /*
 227                 * Check if target/attribute conflicts
 228                 */
 229                if (target == wtarget && attr == wattr)
 230                        return 0;
 231        }
 232
 233        return 1;
 234}
 235
 236static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
 237                                  phys_addr_t base, size_t size)
 238{
 239        int win;
 240
 241        for (win = 0; win < mbus->soc->num_wins; win++) {
 242                u64 wbase;
 243                u32 wsize;
 244                int enabled;
 245
 246                mvebu_mbus_read_window(mbus, win,
 247                                       &enabled, &wbase, &wsize,
 248                                       NULL, NULL, NULL);
 249
 250                if (!enabled)
 251                        continue;
 252
 253                if (base == wbase && size == wsize)
 254                        return win;
 255        }
 256
 257        return -ENODEV;
 258}
 259
 260static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
 261                                   int win, phys_addr_t base, size_t size,
 262                                   phys_addr_t remap, u8 target,
 263                                   u8 attr)
 264{
 265        void __iomem *addr = mbus->mbuswins_base +
 266                mbus->soc->win_cfg_offset(win);
 267        u32 ctrl, remap_addr;
 268
 269        ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
 270                (attr << WIN_CTRL_ATTR_SHIFT)    |
 271                (target << WIN_CTRL_TGT_SHIFT)   |
 272                WIN_CTRL_ENABLE;
 273
 274        writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
 275        writel(ctrl, addr + WIN_CTRL_OFF);
 276        if (win < mbus->soc->num_remappable_wins) {
 277                if (remap == MVEBU_MBUS_NO_REMAP)
 278                        remap_addr = base;
 279                else
 280                        remap_addr = remap;
 281                writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
 282                writel(0, addr + WIN_REMAP_HI_OFF);
 283        }
 284
 285        return 0;
 286}
 287
 288static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
 289                                   phys_addr_t base, size_t size,
 290                                   phys_addr_t remap, u8 target,
 291                                   u8 attr)
 292{
 293        int win;
 294
 295        if (remap == MVEBU_MBUS_NO_REMAP) {
 296                for (win = mbus->soc->num_remappable_wins;
 297                     win < mbus->soc->num_wins; win++)
 298                        if (mvebu_mbus_window_is_free(mbus, win))
 299                                return mvebu_mbus_setup_window(mbus, win, base,
 300                                                               size, remap,
 301                                                               target, attr);
 302        }
 303
 304
 305        for (win = 0; win < mbus->soc->num_wins; win++)
 306                if (mvebu_mbus_window_is_free(mbus, win))
 307                        return mvebu_mbus_setup_window(mbus, win, base, size,
 308                                                       remap, target, attr);
 309
 310        return -ENOMEM;
 311}
 312
 313/*
 314 * Debugfs debugging
 315 */
 316
 317/* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
 318static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
 319                                        struct seq_file *seq, void *v)
 320{
 321        int i;
 322
 323        for (i = 0; i < 4; i++) {
 324                u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
 325                u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
 326                u64 base;
 327                u32 size;
 328
 329                if (!(sizereg & DDR_SIZE_ENABLED)) {
 330                        seq_printf(seq, "[%d] disabled\n", i);
 331                        continue;
 332                }
 333
 334                base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
 335                base |= basereg & DDR_BASE_CS_LOW_MASK;
 336                size = (sizereg | ~DDR_SIZE_MASK);
 337
 338                seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
 339                           i, (unsigned long long)base,
 340                           (unsigned long long)base + size + 1,
 341                           (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
 342        }
 343
 344        return 0;
 345}
 346
 347/* Special function for Dove */
 348static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
 349                                       struct seq_file *seq, void *v)
 350{
 351        int i;
 352
 353        for (i = 0; i < 2; i++) {
 354                u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
 355                u64 base;
 356                u32 size;
 357
 358                if (!(map & 1)) {
 359                        seq_printf(seq, "[%d] disabled\n", i);
 360                        continue;
 361                }
 362
 363                base = map & 0xff800000;
 364                size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
 365
 366                seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
 367                           i, (unsigned long long)base,
 368                           (unsigned long long)base + size, i);
 369        }
 370
 371        return 0;
 372}
 373
 374static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
 375{
 376        struct mvebu_mbus_state *mbus = &mbus_state;
 377        return mbus->soc->show_cpu_target(mbus, seq, v);
 378}
 379
 380static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
 381{
 382        return single_open(file, mvebu_sdram_debug_show, inode->i_private);
 383}
 384
 385static const struct file_operations mvebu_sdram_debug_fops = {
 386        .open = mvebu_sdram_debug_open,
 387        .read = seq_read,
 388        .llseek = seq_lseek,
 389        .release = single_release,
 390};
 391
 392static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
 393{
 394        struct mvebu_mbus_state *mbus = &mbus_state;
 395        int win;
 396
 397        for (win = 0; win < mbus->soc->num_wins; win++) {
 398                u64 wbase, wremap;
 399                u32 wsize;
 400                u8 wtarget, wattr;
 401                int enabled;
 402
 403                mvebu_mbus_read_window(mbus, win,
 404                                       &enabled, &wbase, &wsize,
 405                                       &wtarget, &wattr, &wremap);
 406
 407                if (!enabled) {
 408                        seq_printf(seq, "[%02d] disabled\n", win);
 409                        continue;
 410                }
 411
 412                seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
 413                           win, (unsigned long long)wbase,
 414                           (unsigned long long)(wbase + wsize), wtarget, wattr);
 415
 416                if (win < mbus->soc->num_remappable_wins) {
 417                        seq_printf(seq, " (remap %016llx)\n",
 418                                   (unsigned long long)wremap);
 419                } else
 420                        seq_printf(seq, "\n");
 421        }
 422
 423        return 0;
 424}
 425
 426static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
 427{
 428        return single_open(file, mvebu_devs_debug_show, inode->i_private);
 429}
 430
 431static const struct file_operations mvebu_devs_debug_fops = {
 432        .open = mvebu_devs_debug_open,
 433        .read = seq_read,
 434        .llseek = seq_lseek,
 435        .release = single_release,
 436};
 437
 438/*
 439 * SoC-specific functions and definitions
 440 */
 441
 442static unsigned int orion_mbus_win_offset(int win)
 443{
 444        return win << 4;
 445}
 446
 447static unsigned int armada_370_xp_mbus_win_offset(int win)
 448{
 449        /* The register layout is a bit annoying and the below code
 450         * tries to cope with it.
 451         * - At offset 0x0, there are the registers for the first 8
 452         *   windows, with 4 registers of 32 bits per window (ctrl,
 453         *   base, remap low, remap high)
 454         * - Then at offset 0x80, there is a hole of 0x10 bytes for
 455         *   the internal registers base address and internal units
 456         *   sync barrier register.
 457         * - Then at offset 0x90, there the registers for 12
 458         *   windows, with only 2 registers of 32 bits per window
 459         *   (ctrl, base).
 460         */
 461        if (win < 8)
 462                return win << 4;
 463        else
 464                return 0x90 + ((win - 8) << 3);
 465}
 466
 467static unsigned int mv78xx0_mbus_win_offset(int win)
 468{
 469        if (win < 8)
 470                return win << 4;
 471        else
 472                return 0x900 + ((win - 8) << 4);
 473}
 474
 475static void __init
 476mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
 477{
 478        int i;
 479        int cs;
 480
 481        mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 482
 483        for (i = 0, cs = 0; i < 4; i++) {
 484                u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
 485                u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
 486
 487                /*
 488                 * We only take care of entries for which the chip
 489                 * select is enabled, and that don't have high base
 490                 * address bits set (devices can only access the first
 491                 * 32 bits of the memory).
 492                 */
 493                if ((size & DDR_SIZE_ENABLED) &&
 494                    !(base & DDR_BASE_CS_HIGH_MASK)) {
 495                        struct mbus_dram_window *w;
 496
 497                        w = &mvebu_mbus_dram_info.cs[cs++];
 498                        w->cs_index = i;
 499                        w->mbus_attr = 0xf & ~(1 << i);
 500                        if (mbus->hw_io_coherency)
 501                                w->mbus_attr |= ATTR_HW_COHERENCY;
 502                        w->base = base & DDR_BASE_CS_LOW_MASK;
 503                        w->size = (size | ~DDR_SIZE_MASK) + 1;
 504                }
 505        }
 506        mvebu_mbus_dram_info.num_cs = cs;
 507}
 508
 509static void __init
 510mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
 511{
 512        int i;
 513        int cs;
 514
 515        mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 516
 517        for (i = 0, cs = 0; i < 2; i++) {
 518                u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
 519
 520                /*
 521                 * Chip select enabled?
 522                 */
 523                if (map & 1) {
 524                        struct mbus_dram_window *w;
 525
 526                        w = &mvebu_mbus_dram_info.cs[cs++];
 527                        w->cs_index = i;
 528                        w->mbus_attr = 0; /* CS address decoding done inside */
 529                                          /* the DDR controller, no need to  */
 530                                          /* provide attributes */
 531                        w->base = map & 0xff800000;
 532                        w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
 533                }
 534        }
 535
 536        mvebu_mbus_dram_info.num_cs = cs;
 537}
 538
 539static const struct mvebu_mbus_soc_data armada_370_xp_mbus_data = {
 540        .num_wins            = 20,
 541        .num_remappable_wins = 8,
 542        .win_cfg_offset      = armada_370_xp_mbus_win_offset,
 543        .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
 544        .show_cpu_target     = mvebu_sdram_debug_show_orion,
 545};
 546
 547static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
 548        .num_wins            = 8,
 549        .num_remappable_wins = 4,
 550        .win_cfg_offset      = orion_mbus_win_offset,
 551        .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
 552        .show_cpu_target     = mvebu_sdram_debug_show_orion,
 553};
 554
 555static const struct mvebu_mbus_soc_data dove_mbus_data = {
 556        .num_wins            = 8,
 557        .num_remappable_wins = 4,
 558        .win_cfg_offset      = orion_mbus_win_offset,
 559        .setup_cpu_target    = mvebu_mbus_dove_setup_cpu_target,
 560        .show_cpu_target     = mvebu_sdram_debug_show_dove,
 561};
 562
 563/*
 564 * Some variants of Orion5x have 4 remappable windows, some other have
 565 * only two of them.
 566 */
 567static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
 568        .num_wins            = 8,
 569        .num_remappable_wins = 4,
 570        .win_cfg_offset      = orion_mbus_win_offset,
 571        .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
 572        .show_cpu_target     = mvebu_sdram_debug_show_orion,
 573};
 574
 575static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
 576        .num_wins            = 8,
 577        .num_remappable_wins = 2,
 578        .win_cfg_offset      = orion_mbus_win_offset,
 579        .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
 580        .show_cpu_target     = mvebu_sdram_debug_show_orion,
 581};
 582
 583static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
 584        .num_wins            = 14,
 585        .num_remappable_wins = 8,
 586        .win_cfg_offset      = mv78xx0_mbus_win_offset,
 587        .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
 588        .show_cpu_target     = mvebu_sdram_debug_show_orion,
 589};
 590
 591/*
 592 * The driver doesn't yet have a DT binding because the details of
 593 * this DT binding still need to be sorted out. However, as a
 594 * preparation, we already use of_device_id to match a SoC description
 595 * string against the SoC specific details of this driver.
 596 */
 597static const struct of_device_id of_mvebu_mbus_ids[] = {
 598        { .compatible = "marvell,armada370-mbus",
 599          .data = &armada_370_xp_mbus_data, },
 600        { .compatible = "marvell,armadaxp-mbus",
 601          .data = &armada_370_xp_mbus_data, },
 602        { .compatible = "marvell,kirkwood-mbus",
 603          .data = &kirkwood_mbus_data, },
 604        { .compatible = "marvell,dove-mbus",
 605          .data = &dove_mbus_data, },
 606        { .compatible = "marvell,orion5x-88f5281-mbus",
 607          .data = &orion5x_4win_mbus_data, },
 608        { .compatible = "marvell,orion5x-88f5182-mbus",
 609          .data = &orion5x_2win_mbus_data, },
 610        { .compatible = "marvell,orion5x-88f5181-mbus",
 611          .data = &orion5x_2win_mbus_data, },
 612        { .compatible = "marvell,orion5x-88f6183-mbus",
 613          .data = &orion5x_4win_mbus_data, },
 614        { .compatible = "marvell,mv78xx0-mbus",
 615          .data = &mv78xx0_mbus_data, },
 616        { },
 617};
 618
 619/*
 620 * Public API of the driver
 621 */
 622int mvebu_mbus_add_window_remap_by_id(unsigned int target,
 623                                      unsigned int attribute,
 624                                      phys_addr_t base, size_t size,
 625                                      phys_addr_t remap)
 626{
 627        struct mvebu_mbus_state *s = &mbus_state;
 628
 629        if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
 630                pr_err("cannot add window '%x:%x', conflicts with another window\n",
 631                       target, attribute);
 632                return -EINVAL;
 633        }
 634
 635        return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
 636}
 637
 638int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
 639                                phys_addr_t base, size_t size)
 640{
 641        return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
 642                                                 size, MVEBU_MBUS_NO_REMAP);
 643}
 644
 645int mvebu_mbus_del_window(phys_addr_t base, size_t size)
 646{
 647        int win;
 648
 649        win = mvebu_mbus_find_window(&mbus_state, base, size);
 650        if (win < 0)
 651                return win;
 652
 653        mvebu_mbus_disable_window(&mbus_state, win);
 654        return 0;
 655}
 656
 657void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
 658{
 659        if (!res)
 660                return;
 661        *res = mbus_state.pcie_mem_aperture;
 662}
 663
 664void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
 665{
 666        if (!res)
 667                return;
 668        *res = mbus_state.pcie_io_aperture;
 669}
 670
 671static __init int mvebu_mbus_debugfs_init(void)
 672{
 673        struct mvebu_mbus_state *s = &mbus_state;
 674
 675        /*
 676         * If no base has been initialized, doesn't make sense to
 677         * register the debugfs entries. We may be on a multiplatform
 678         * kernel that isn't running a Marvell EBU SoC.
 679         */
 680        if (!s->mbuswins_base)
 681                return 0;
 682
 683        s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
 684        if (s->debugfs_root) {
 685                s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
 686                                                       s->debugfs_root, NULL,
 687                                                       &mvebu_sdram_debug_fops);
 688                s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
 689                                                      s->debugfs_root, NULL,
 690                                                      &mvebu_devs_debug_fops);
 691        }
 692
 693        return 0;
 694}
 695fs_initcall(mvebu_mbus_debugfs_init);
 696
 697static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
 698                                         phys_addr_t mbuswins_phys_base,
 699                                         size_t mbuswins_size,
 700                                         phys_addr_t sdramwins_phys_base,
 701                                         size_t sdramwins_size)
 702{
 703        struct device_node *np;
 704        int win;
 705
 706        mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
 707        if (!mbus->mbuswins_base)
 708                return -ENOMEM;
 709
 710        mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
 711        if (!mbus->sdramwins_base) {
 712                iounmap(mbus_state.mbuswins_base);
 713                return -ENOMEM;
 714        }
 715
 716        np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
 717        if (np) {
 718                mbus->hw_io_coherency = 1;
 719                of_node_put(np);
 720        }
 721
 722        for (win = 0; win < mbus->soc->num_wins; win++)
 723                mvebu_mbus_disable_window(mbus, win);
 724
 725        mbus->soc->setup_cpu_target(mbus);
 726
 727        return 0;
 728}
 729
 730int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
 731                           size_t mbuswins_size,
 732                           phys_addr_t sdramwins_phys_base,
 733                           size_t sdramwins_size)
 734{
 735        const struct of_device_id *of_id;
 736
 737        for (of_id = of_mvebu_mbus_ids; of_id->compatible; of_id++)
 738                if (!strcmp(of_id->compatible, soc))
 739                        break;
 740
 741        if (!of_id->compatible) {
 742                pr_err("could not find a matching SoC family\n");
 743                return -ENODEV;
 744        }
 745
 746        mbus_state.soc = of_id->data;
 747
 748        return mvebu_mbus_common_init(&mbus_state,
 749                        mbuswins_phys_base,
 750                        mbuswins_size,
 751                        sdramwins_phys_base,
 752                        sdramwins_size);
 753}
 754
 755#ifdef CONFIG_OF
 756/*
 757 * The window IDs in the ranges DT property have the following format:
 758 *  - bits 28 to 31: MBus custom field
 759 *  - bits 24 to 27: window target ID
 760 *  - bits 16 to 23: window attribute ID
 761 *  - bits  0 to 15: unused
 762 */
 763#define CUSTOM(id) (((id) & 0xF0000000) >> 24)
 764#define TARGET(id) (((id) & 0x0F000000) >> 24)
 765#define ATTR(id)   (((id) & 0x00FF0000) >> 16)
 766
 767static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
 768                                    u32 base, u32 size,
 769                                    u8 target, u8 attr)
 770{
 771        if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
 772                pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
 773                       target, attr);
 774                return -EBUSY;
 775        }
 776
 777        if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
 778                                    target, attr)) {
 779                pr_err("cannot add window '%04x:%04x', too many windows\n",
 780                       target, attr);
 781                return -ENOMEM;
 782        }
 783        return 0;
 784}
 785
 786static int __init
 787mbus_parse_ranges(struct device_node *node,
 788                  int *addr_cells, int *c_addr_cells, int *c_size_cells,
 789                  int *cell_count, const __be32 **ranges_start,
 790                  const __be32 **ranges_end)
 791{
 792        const __be32 *prop;
 793        int ranges_len, tuple_len;
 794
 795        /* Allow a node with no 'ranges' property */
 796        *ranges_start = of_get_property(node, "ranges", &ranges_len);
 797        if (*ranges_start == NULL) {
 798                *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
 799                *ranges_start = *ranges_end = NULL;
 800                return 0;
 801        }
 802        *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
 803
 804        *addr_cells = of_n_addr_cells(node);
 805
 806        prop = of_get_property(node, "#address-cells", NULL);
 807        *c_addr_cells = be32_to_cpup(prop);
 808
 809        prop = of_get_property(node, "#size-cells", NULL);
 810        *c_size_cells = be32_to_cpup(prop);
 811
 812        *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
 813        tuple_len = (*cell_count) * sizeof(__be32);
 814
 815        if (ranges_len % tuple_len) {
 816                pr_warn("malformed ranges entry '%s'\n", node->name);
 817                return -EINVAL;
 818        }
 819        return 0;
 820}
 821
 822static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
 823                                struct device_node *np)
 824{
 825        int addr_cells, c_addr_cells, c_size_cells;
 826        int i, ret, cell_count;
 827        const __be32 *r, *ranges_start, *ranges_end;
 828
 829        ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
 830                                &c_size_cells, &cell_count,
 831                                &ranges_start, &ranges_end);
 832        if (ret < 0)
 833                return ret;
 834
 835        for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
 836                u32 windowid, base, size;
 837                u8 target, attr;
 838
 839                /*
 840                 * An entry with a non-zero custom field do not
 841                 * correspond to a static window, so skip it.
 842                 */
 843                windowid = of_read_number(r, 1);
 844                if (CUSTOM(windowid))
 845                        continue;
 846
 847                target = TARGET(windowid);
 848                attr = ATTR(windowid);
 849
 850                base = of_read_number(r + c_addr_cells, addr_cells);
 851                size = of_read_number(r + c_addr_cells + addr_cells,
 852                                      c_size_cells);
 853                ret = mbus_dt_setup_win(mbus, base, size, target, attr);
 854                if (ret < 0)
 855                        return ret;
 856        }
 857        return 0;
 858}
 859
 860static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
 861                                                 struct resource *mem,
 862                                                 struct resource *io)
 863{
 864        u32 reg[2];
 865        int ret;
 866
 867        /*
 868         * These are optional, so we make sure that resource_size(x) will
 869         * return 0.
 870         */
 871        memset(mem, 0, sizeof(struct resource));
 872        mem->end = -1;
 873        memset(io, 0, sizeof(struct resource));
 874        io->end = -1;
 875
 876        ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
 877        if (!ret) {
 878                mem->start = reg[0];
 879                mem->end = mem->start + reg[1];
 880                mem->flags = IORESOURCE_MEM;
 881        }
 882
 883        ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
 884        if (!ret) {
 885                io->start = reg[0];
 886                io->end = io->start + reg[1];
 887                io->flags = IORESOURCE_IO;
 888        }
 889}
 890
 891int __init mvebu_mbus_dt_init(void)
 892{
 893        struct resource mbuswins_res, sdramwins_res;
 894        struct device_node *np, *controller;
 895        const struct of_device_id *of_id;
 896        const __be32 *prop;
 897        int ret;
 898
 899        np = of_find_matching_node(NULL, of_mvebu_mbus_ids);
 900        if (!np) {
 901                pr_err("could not find a matching SoC family\n");
 902                return -ENODEV;
 903        }
 904
 905        of_id = of_match_node(of_mvebu_mbus_ids, np);
 906        mbus_state.soc = of_id->data;
 907
 908        prop = of_get_property(np, "controller", NULL);
 909        if (!prop) {
 910                pr_err("required 'controller' property missing\n");
 911                return -EINVAL;
 912        }
 913
 914        controller = of_find_node_by_phandle(be32_to_cpup(prop));
 915        if (!controller) {
 916                pr_err("could not find an 'mbus-controller' node\n");
 917                return -ENODEV;
 918        }
 919
 920        if (of_address_to_resource(controller, 0, &mbuswins_res)) {
 921                pr_err("cannot get MBUS register address\n");
 922                return -EINVAL;
 923        }
 924
 925        if (of_address_to_resource(controller, 1, &sdramwins_res)) {
 926                pr_err("cannot get SDRAM register address\n");
 927                return -EINVAL;
 928        }
 929
 930        /* Get optional pcie-{mem,io}-aperture properties */
 931        mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
 932                                          &mbus_state.pcie_io_aperture);
 933
 934        ret = mvebu_mbus_common_init(&mbus_state,
 935                                     mbuswins_res.start,
 936                                     resource_size(&mbuswins_res),
 937                                     sdramwins_res.start,
 938                                     resource_size(&sdramwins_res));
 939        if (ret)
 940                return ret;
 941
 942        /* Setup statically declared windows in the DT */
 943        return mbus_dt_setup(&mbus_state, np);
 944}
 945#endif
 946
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