linux/drivers/ata/sata_svw.c
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   1/*
   2 *  sata_svw.c - ServerWorks / Apple K2 SATA
   3 *
   4 *  Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
   5 *                 Jeff Garzik <jgarzik@pobox.com>
   6 *                  Please ALWAYS copy linux-ide@vger.kernel.org
   7 *                  on emails.
   8 *
   9 *  Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
  10 *
  11 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
  12 *
  13 *  This driver probably works with non-Apple versions of the
  14 *  Broadcom chipset...
  15 *
  16 *
  17 *  This program is free software; you can redistribute it and/or modify
  18 *  it under the terms of the GNU General Public License as published by
  19 *  the Free Software Foundation; either version 2, or (at your option)
  20 *  any later version.
  21 *
  22 *  This program is distributed in the hope that it will be useful,
  23 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25 *  GNU General Public License for more details.
  26 *
  27 *  You should have received a copy of the GNU General Public License
  28 *  along with this program; see the file COPYING.  If not, write to
  29 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  30 *
  31 *
  32 *  libata documentation is available via 'make {ps|pdf}docs',
  33 *  as Documentation/DocBook/libata.*
  34 *
  35 *  Hardware documentation available under NDA.
  36 *
  37 */
  38
  39#include <linux/kernel.h>
  40#include <linux/module.h>
  41#include <linux/pci.h>
  42#include <linux/init.h>
  43#include <linux/blkdev.h>
  44#include <linux/delay.h>
  45#include <linux/interrupt.h>
  46#include <linux/device.h>
  47#include <scsi/scsi_host.h>
  48#include <scsi/scsi_cmnd.h>
  49#include <scsi/scsi.h>
  50#include <linux/libata.h>
  51
  52#ifdef CONFIG_PPC_OF
  53#include <asm/prom.h>
  54#include <asm/pci-bridge.h>
  55#endif /* CONFIG_PPC_OF */
  56
  57#define DRV_NAME        "sata_svw"
  58#define DRV_VERSION     "2.3"
  59
  60enum {
  61        /* ap->flags bits */
  62        K2_FLAG_SATA_8_PORTS            = (1 << 24),
  63        K2_FLAG_NO_ATAPI_DMA            = (1 << 25),
  64        K2_FLAG_BAR_POS_3                       = (1 << 26),
  65
  66        /* Taskfile registers offsets */
  67        K2_SATA_TF_CMD_OFFSET           = 0x00,
  68        K2_SATA_TF_DATA_OFFSET          = 0x00,
  69        K2_SATA_TF_ERROR_OFFSET         = 0x04,
  70        K2_SATA_TF_NSECT_OFFSET         = 0x08,
  71        K2_SATA_TF_LBAL_OFFSET          = 0x0c,
  72        K2_SATA_TF_LBAM_OFFSET          = 0x10,
  73        K2_SATA_TF_LBAH_OFFSET          = 0x14,
  74        K2_SATA_TF_DEVICE_OFFSET        = 0x18,
  75        K2_SATA_TF_CMDSTAT_OFFSET       = 0x1c,
  76        K2_SATA_TF_CTL_OFFSET           = 0x20,
  77
  78        /* DMA base */
  79        K2_SATA_DMA_CMD_OFFSET          = 0x30,
  80
  81        /* SCRs base */
  82        K2_SATA_SCR_STATUS_OFFSET       = 0x40,
  83        K2_SATA_SCR_ERROR_OFFSET        = 0x44,
  84        K2_SATA_SCR_CONTROL_OFFSET      = 0x48,
  85
  86        /* Others */
  87        K2_SATA_SICR1_OFFSET            = 0x80,
  88        K2_SATA_SICR2_OFFSET            = 0x84,
  89        K2_SATA_SIM_OFFSET              = 0x88,
  90
  91        /* Port stride */
  92        K2_SATA_PORT_OFFSET             = 0x100,
  93
  94        chip_svw4                       = 0,
  95        chip_svw8                       = 1,
  96        chip_svw42                      = 2,    /* bar 3 */
  97        chip_svw43                      = 3,    /* bar 5 */
  98};
  99
 100static u8 k2_stat_check_status(struct ata_port *ap);
 101
 102
 103static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
 104{
 105        u8 cmnd = qc->scsicmd->cmnd[0];
 106
 107        if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
 108                return -1;      /* ATAPI DMA not supported */
 109        else {
 110                switch (cmnd) {
 111                case READ_10:
 112                case READ_12:
 113                case READ_16:
 114                case WRITE_10:
 115                case WRITE_12:
 116                case WRITE_16:
 117                        return 0;
 118
 119                default:
 120                        return -1;
 121                }
 122
 123        }
 124}
 125
 126static int k2_sata_scr_read(struct ata_link *link,
 127                            unsigned int sc_reg, u32 *val)
 128{
 129        if (sc_reg > SCR_CONTROL)
 130                return -EINVAL;
 131        *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
 132        return 0;
 133}
 134
 135
 136static int k2_sata_scr_write(struct ata_link *link,
 137                             unsigned int sc_reg, u32 val)
 138{
 139        if (sc_reg > SCR_CONTROL)
 140                return -EINVAL;
 141        writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
 142        return 0;
 143}
 144
 145static int k2_sata_softreset(struct ata_link *link,
 146                             unsigned int *class, unsigned long deadline)
 147{
 148        u8 dmactl;
 149        void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
 150
 151        dmactl = readb(mmio + ATA_DMA_CMD);
 152
 153        /* Clear the start bit */
 154        if (dmactl & ATA_DMA_START) {
 155                dmactl &= ~ATA_DMA_START;
 156                writeb(dmactl, mmio + ATA_DMA_CMD);
 157        }
 158
 159        return ata_sff_softreset(link, class, deadline);
 160}
 161
 162static int k2_sata_hardreset(struct ata_link *link,
 163                             unsigned int *class, unsigned long deadline)
 164{
 165        u8 dmactl;
 166        void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
 167
 168        dmactl = readb(mmio + ATA_DMA_CMD);
 169
 170        /* Clear the start bit */
 171        if (dmactl & ATA_DMA_START) {
 172                dmactl &= ~ATA_DMA_START;
 173                writeb(dmactl, mmio + ATA_DMA_CMD);
 174        }
 175
 176        return sata_sff_hardreset(link, class, deadline);
 177}
 178
 179static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
 180{
 181        struct ata_ioports *ioaddr = &ap->ioaddr;
 182        unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
 183
 184        if (tf->ctl != ap->last_ctl) {
 185                writeb(tf->ctl, ioaddr->ctl_addr);
 186                ap->last_ctl = tf->ctl;
 187                ata_wait_idle(ap);
 188        }
 189        if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
 190                writew(tf->feature | (((u16)tf->hob_feature) << 8),
 191                       ioaddr->feature_addr);
 192                writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
 193                       ioaddr->nsect_addr);
 194                writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
 195                       ioaddr->lbal_addr);
 196                writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
 197                       ioaddr->lbam_addr);
 198                writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
 199                       ioaddr->lbah_addr);
 200        } else if (is_addr) {
 201                writew(tf->feature, ioaddr->feature_addr);
 202                writew(tf->nsect, ioaddr->nsect_addr);
 203                writew(tf->lbal, ioaddr->lbal_addr);
 204                writew(tf->lbam, ioaddr->lbam_addr);
 205                writew(tf->lbah, ioaddr->lbah_addr);
 206        }
 207
 208        if (tf->flags & ATA_TFLAG_DEVICE)
 209                writeb(tf->device, ioaddr->device_addr);
 210
 211        ata_wait_idle(ap);
 212}
 213
 214
 215static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 216{
 217        struct ata_ioports *ioaddr = &ap->ioaddr;
 218        u16 nsect, lbal, lbam, lbah, feature;
 219
 220        tf->command = k2_stat_check_status(ap);
 221        tf->device = readw(ioaddr->device_addr);
 222        feature = readw(ioaddr->error_addr);
 223        nsect = readw(ioaddr->nsect_addr);
 224        lbal = readw(ioaddr->lbal_addr);
 225        lbam = readw(ioaddr->lbam_addr);
 226        lbah = readw(ioaddr->lbah_addr);
 227
 228        tf->feature = feature;
 229        tf->nsect = nsect;
 230        tf->lbal = lbal;
 231        tf->lbam = lbam;
 232        tf->lbah = lbah;
 233
 234        if (tf->flags & ATA_TFLAG_LBA48) {
 235                tf->hob_feature = feature >> 8;
 236                tf->hob_nsect = nsect >> 8;
 237                tf->hob_lbal = lbal >> 8;
 238                tf->hob_lbam = lbam >> 8;
 239                tf->hob_lbah = lbah >> 8;
 240        }
 241}
 242
 243/**
 244 *      k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
 245 *      @qc: Info associated with this ATA transaction.
 246 *
 247 *      LOCKING:
 248 *      spin_lock_irqsave(host lock)
 249 */
 250
 251static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
 252{
 253        struct ata_port *ap = qc->ap;
 254        unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
 255        u8 dmactl;
 256        void __iomem *mmio = ap->ioaddr.bmdma_addr;
 257
 258        /* load PRD table addr. */
 259        mb();   /* make sure PRD table writes are visible to controller */
 260        writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);
 261
 262        /* specify data direction, triple-check start bit is clear */
 263        dmactl = readb(mmio + ATA_DMA_CMD);
 264        dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
 265        if (!rw)
 266                dmactl |= ATA_DMA_WR;
 267        writeb(dmactl, mmio + ATA_DMA_CMD);
 268
 269        /* issue r/w command if this is not a ATA DMA command*/
 270        if (qc->tf.protocol != ATA_PROT_DMA)
 271                ap->ops->sff_exec_command(ap, &qc->tf);
 272}
 273
 274/**
 275 *      k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
 276 *      @qc: Info associated with this ATA transaction.
 277 *
 278 *      LOCKING:
 279 *      spin_lock_irqsave(host lock)
 280 */
 281
 282static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
 283{
 284        struct ata_port *ap = qc->ap;
 285        void __iomem *mmio = ap->ioaddr.bmdma_addr;
 286        u8 dmactl;
 287
 288        /* start host DMA transaction */
 289        dmactl = readb(mmio + ATA_DMA_CMD);
 290        writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
 291        /* This works around possible data corruption.
 292
 293           On certain SATA controllers that can be seen when the r/w
 294           command is given to the controller before the host DMA is
 295           started.
 296
 297           On a Read command, the controller would initiate the
 298           command to the drive even before it sees the DMA
 299           start. When there are very fast drives connected to the
 300           controller, or when the data request hits in the drive
 301           cache, there is the possibility that the drive returns a
 302           part or all of the requested data to the controller before
 303           the DMA start is issued.  In this case, the controller
 304           would become confused as to what to do with the data.  In
 305           the worst case when all the data is returned back to the
 306           controller, the controller could hang. In other cases it
 307           could return partial data returning in data
 308           corruption. This problem has been seen in PPC systems and
 309           can also appear on an system with very fast disks, where
 310           the SATA controller is sitting behind a number of bridges,
 311           and hence there is significant latency between the r/w
 312           command and the start command. */
 313        /* issue r/w command if the access is to ATA */
 314        if (qc->tf.protocol == ATA_PROT_DMA)
 315                ap->ops->sff_exec_command(ap, &qc->tf);
 316}
 317
 318
 319static u8 k2_stat_check_status(struct ata_port *ap)
 320{
 321        return readl(ap->ioaddr.status_addr);
 322}
 323
 324#ifdef CONFIG_PPC_OF
 325static int k2_sata_show_info(struct seq_file *m, struct Scsi_Host *shost)
 326{
 327        struct ata_port *ap;
 328        struct device_node *np;
 329        int index;
 330
 331        /* Find  the ata_port */
 332        ap = ata_shost_to_port(shost);
 333        if (ap == NULL)
 334                return 0;
 335
 336        /* Find the OF node for the PCI device proper */
 337        np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
 338        if (np == NULL)
 339                return 0;
 340
 341        /* Match it to a port node */
 342        index = (ap == ap->host->ports[0]) ? 0 : 1;
 343        for (np = np->child; np != NULL; np = np->sibling) {
 344                const u32 *reg = of_get_property(np, "reg", NULL);
 345                if (!reg)
 346                        continue;
 347                if (index == *reg) {
 348                        seq_printf(m, "devspec: %s\n", np->full_name);
 349                        break;
 350                }
 351        }
 352        return 0;
 353}
 354#endif /* CONFIG_PPC_OF */
 355
 356
 357static struct scsi_host_template k2_sata_sht = {
 358        ATA_BMDMA_SHT(DRV_NAME),
 359#ifdef CONFIG_PPC_OF
 360        .show_info              = k2_sata_show_info,
 361#endif
 362};
 363
 364
 365static struct ata_port_operations k2_sata_ops = {
 366        .inherits               = &ata_bmdma_port_ops,
 367        .softreset              = k2_sata_softreset,
 368        .hardreset              = k2_sata_hardreset,
 369        .sff_tf_load            = k2_sata_tf_load,
 370        .sff_tf_read            = k2_sata_tf_read,
 371        .sff_check_status       = k2_stat_check_status,
 372        .check_atapi_dma        = k2_sata_check_atapi_dma,
 373        .bmdma_setup            = k2_bmdma_setup_mmio,
 374        .bmdma_start            = k2_bmdma_start_mmio,
 375        .scr_read               = k2_sata_scr_read,
 376        .scr_write              = k2_sata_scr_write,
 377};
 378
 379static const struct ata_port_info k2_port_info[] = {
 380        /* chip_svw4 */
 381        {
 382                .flags          = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA,
 383                .pio_mask       = ATA_PIO4,
 384                .mwdma_mask     = ATA_MWDMA2,
 385                .udma_mask      = ATA_UDMA6,
 386                .port_ops       = &k2_sata_ops,
 387        },
 388        /* chip_svw8 */
 389        {
 390                .flags          = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA |
 391                                  K2_FLAG_SATA_8_PORTS,
 392                .pio_mask       = ATA_PIO4,
 393                .mwdma_mask     = ATA_MWDMA2,
 394                .udma_mask      = ATA_UDMA6,
 395                .port_ops       = &k2_sata_ops,
 396        },
 397        /* chip_svw42 */
 398        {
 399                .flags          = ATA_FLAG_SATA | K2_FLAG_BAR_POS_3,
 400                .pio_mask       = ATA_PIO4,
 401                .mwdma_mask     = ATA_MWDMA2,
 402                .udma_mask      = ATA_UDMA6,
 403                .port_ops       = &k2_sata_ops,
 404        },
 405        /* chip_svw43 */
 406        {
 407                .flags          = ATA_FLAG_SATA,
 408                .pio_mask       = ATA_PIO4,
 409                .mwdma_mask     = ATA_MWDMA2,
 410                .udma_mask      = ATA_UDMA6,
 411                .port_ops       = &k2_sata_ops,
 412        },
 413};
 414
 415static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
 416{
 417        port->cmd_addr          = base + K2_SATA_TF_CMD_OFFSET;
 418        port->data_addr         = base + K2_SATA_TF_DATA_OFFSET;
 419        port->feature_addr      =
 420        port->error_addr        = base + K2_SATA_TF_ERROR_OFFSET;
 421        port->nsect_addr        = base + K2_SATA_TF_NSECT_OFFSET;
 422        port->lbal_addr         = base + K2_SATA_TF_LBAL_OFFSET;
 423        port->lbam_addr         = base + K2_SATA_TF_LBAM_OFFSET;
 424        port->lbah_addr         = base + K2_SATA_TF_LBAH_OFFSET;
 425        port->device_addr       = base + K2_SATA_TF_DEVICE_OFFSET;
 426        port->command_addr      =
 427        port->status_addr       = base + K2_SATA_TF_CMDSTAT_OFFSET;
 428        port->altstatus_addr    =
 429        port->ctl_addr          = base + K2_SATA_TF_CTL_OFFSET;
 430        port->bmdma_addr        = base + K2_SATA_DMA_CMD_OFFSET;
 431        port->scr_addr          = base + K2_SATA_SCR_STATUS_OFFSET;
 432}
 433
 434
 435static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 436{
 437        const struct ata_port_info *ppi[] =
 438                { &k2_port_info[ent->driver_data], NULL };
 439        struct ata_host *host;
 440        void __iomem *mmio_base;
 441        int n_ports, i, rc, bar_pos;
 442
 443        ata_print_version_once(&pdev->dev, DRV_VERSION);
 444
 445        /* allocate host */
 446        n_ports = 4;
 447        if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
 448                n_ports = 8;
 449
 450        host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
 451        if (!host)
 452                return -ENOMEM;
 453
 454        bar_pos = 5;
 455        if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
 456                bar_pos = 3;
 457        /*
 458         * If this driver happens to only be useful on Apple's K2, then
 459         * we should check that here as it has a normal Serverworks ID
 460         */
 461        rc = pcim_enable_device(pdev);
 462        if (rc)
 463                return rc;
 464
 465        /*
 466         * Check if we have resources mapped at all (second function may
 467         * have been disabled by firmware)
 468         */
 469        if (pci_resource_len(pdev, bar_pos) == 0) {
 470                /* In IDE mode we need to pin the device to ensure that
 471                        pcim_release does not clear the busmaster bit in config
 472                        space, clearing causes busmaster DMA to fail on
 473                        ports 3 & 4 */
 474                pcim_pin_device(pdev);
 475                return -ENODEV;
 476        }
 477
 478        /* Request and iomap PCI regions */
 479        rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
 480        if (rc == -EBUSY)
 481                pcim_pin_device(pdev);
 482        if (rc)
 483                return rc;
 484        host->iomap = pcim_iomap_table(pdev);
 485        mmio_base = host->iomap[bar_pos];
 486
 487        /* different controllers have different number of ports - currently 4 or 8 */
 488        /* All ports are on the same function. Multi-function device is no
 489         * longer available. This should not be seen in any system. */
 490        for (i = 0; i < host->n_ports; i++) {
 491                struct ata_port *ap = host->ports[i];
 492                unsigned int offset = i * K2_SATA_PORT_OFFSET;
 493
 494                k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);
 495
 496                ata_port_pbar_desc(ap, 5, -1, "mmio");
 497                ata_port_pbar_desc(ap, 5, offset, "port");
 498        }
 499
 500        rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
 501        if (rc)
 502                return rc;
 503        rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
 504        if (rc)
 505                return rc;
 506
 507        /* Clear a magic bit in SCR1 according to Darwin, those help
 508         * some funky seagate drives (though so far, those were already
 509         * set by the firmware on the machines I had access to)
 510         */
 511        writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
 512               mmio_base + K2_SATA_SICR1_OFFSET);
 513
 514        /* Clear SATA error & interrupts we don't use */
 515        writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
 516        writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
 517
 518        pci_set_master(pdev);
 519        return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
 520                                 IRQF_SHARED, &k2_sata_sht);
 521}
 522
 523/* 0x240 is device ID for Apple K2 device
 524 * 0x241 is device ID for Serverworks Frodo4
 525 * 0x242 is device ID for Serverworks Frodo8
 526 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
 527 * controller
 528 * */
 529static const struct pci_device_id k2_sata_pci_tbl[] = {
 530        { PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
 531        { PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
 532        { PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
 533        { PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
 534        { PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
 535        { PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
 536        { PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },
 537
 538        { }
 539};
 540
 541static struct pci_driver k2_sata_pci_driver = {
 542        .name                   = DRV_NAME,
 543        .id_table               = k2_sata_pci_tbl,
 544        .probe                  = k2_sata_init_one,
 545        .remove                 = ata_pci_remove_one,
 546};
 547
 548module_pci_driver(k2_sata_pci_driver);
 549
 550MODULE_AUTHOR("Benjamin Herrenschmidt");
 551MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
 552MODULE_LICENSE("GPL");
 553MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
 554MODULE_VERSION(DRV_VERSION);
 555
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