linux/drivers/ata/sata_fsl.c
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   1/*
   2 * drivers/ata/sata_fsl.c
   3 *
   4 * Freescale 3.0Gbps SATA device driver
   5 *
   6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
   7 * Li Yang <leoli@freescale.com>
   8 *
   9 * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc.
  10 *
  11 * This program is free software; you can redistribute  it and/or modify it
  12 * under  the terms of  the GNU General  Public License as published by the
  13 * Free Software Foundation;  either version 2 of the  License, or (at your
  14 * option) any later version.
  15 *
  16 */
  17
  18#include <linux/kernel.h>
  19#include <linux/module.h>
  20#include <linux/platform_device.h>
  21#include <linux/slab.h>
  22
  23#include <scsi/scsi_host.h>
  24#include <scsi/scsi_cmnd.h>
  25#include <linux/libata.h>
  26#include <asm/io.h>
  27#include <linux/of_platform.h>
  28
  29static unsigned int intr_coalescing_count;
  30module_param(intr_coalescing_count, int, S_IRUGO);
  31MODULE_PARM_DESC(intr_coalescing_count,
  32                                 "INT coalescing count threshold (1..31)");
  33
  34static unsigned int intr_coalescing_ticks;
  35module_param(intr_coalescing_ticks, int, S_IRUGO);
  36MODULE_PARM_DESC(intr_coalescing_ticks,
  37                                 "INT coalescing timer threshold in AHB ticks");
  38/* Controller information */
  39enum {
  40        SATA_FSL_QUEUE_DEPTH    = 16,
  41        SATA_FSL_MAX_PRD        = 63,
  42        SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
  43        SATA_FSL_MAX_PRD_DIRECT = 16,   /* Direct PRDT entries */
  44
  45        SATA_FSL_HOST_FLAGS     = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
  46                                ATA_FLAG_PMP | ATA_FLAG_NCQ | ATA_FLAG_AN),
  47
  48        SATA_FSL_MAX_CMDS       = SATA_FSL_QUEUE_DEPTH,
  49        SATA_FSL_CMD_HDR_SIZE   = 16,   /* 4 DWORDS */
  50        SATA_FSL_CMD_SLOT_SIZE  = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
  51
  52        /*
  53         * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
  54         * chained indirect PRDEs up to a max count of 63.
  55         * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
  56         * be setup as an indirect descriptor, pointing to it's next
  57         * (contiguous) PRDE. Though chained indirect PRDE arrays are
  58         * supported,it will be more efficient to use a direct PRDT and
  59         * a single chain/link to indirect PRDE array/PRDT.
  60         */
  61
  62        SATA_FSL_CMD_DESC_CFIS_SZ       = 32,
  63        SATA_FSL_CMD_DESC_SFIS_SZ       = 32,
  64        SATA_FSL_CMD_DESC_ACMD_SZ       = 16,
  65        SATA_FSL_CMD_DESC_RSRVD         = 16,
  66
  67        SATA_FSL_CMD_DESC_SIZE  = (SATA_FSL_CMD_DESC_CFIS_SZ +
  68                                 SATA_FSL_CMD_DESC_SFIS_SZ +
  69                                 SATA_FSL_CMD_DESC_ACMD_SZ +
  70                                 SATA_FSL_CMD_DESC_RSRVD +
  71                                 SATA_FSL_MAX_PRD * 16),
  72
  73        SATA_FSL_CMD_DESC_OFFSET_TO_PRDT        =
  74                                (SATA_FSL_CMD_DESC_CFIS_SZ +
  75                                 SATA_FSL_CMD_DESC_SFIS_SZ +
  76                                 SATA_FSL_CMD_DESC_ACMD_SZ +
  77                                 SATA_FSL_CMD_DESC_RSRVD),
  78
  79        SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
  80        SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
  81                                        SATA_FSL_CMD_DESC_AR_SZ),
  82
  83        /*
  84         * MPC8315 has two SATA controllers, SATA1 & SATA2
  85         * (one port per controller)
  86         * MPC837x has 2/4 controllers, one port per controller
  87         */
  88
  89        SATA_FSL_MAX_PORTS      = 1,
  90
  91        SATA_FSL_IRQ_FLAG       = IRQF_SHARED,
  92};
  93
  94/*
  95 * Interrupt Coalescing Control Register bitdefs  */
  96enum {
  97        ICC_MIN_INT_COUNT_THRESHOLD     = 1,
  98        ICC_MAX_INT_COUNT_THRESHOLD     = ((1 << 5) - 1),
  99        ICC_MIN_INT_TICKS_THRESHOLD     = 0,
 100        ICC_MAX_INT_TICKS_THRESHOLD     = ((1 << 19) - 1),
 101        ICC_SAFE_INT_TICKS              = 1,
 102};
 103
 104/*
 105* Host Controller command register set - per port
 106*/
 107enum {
 108        CQ = 0,
 109        CA = 8,
 110        CC = 0x10,
 111        CE = 0x18,
 112        DE = 0x20,
 113        CHBA = 0x24,
 114        HSTATUS = 0x28,
 115        HCONTROL = 0x2C,
 116        CQPMP = 0x30,
 117        SIGNATURE = 0x34,
 118        ICC = 0x38,
 119
 120        /*
 121         * Host Status Register (HStatus) bitdefs
 122         */
 123        ONLINE = (1 << 31),
 124        GOING_OFFLINE = (1 << 30),
 125        BIST_ERR = (1 << 29),
 126        CLEAR_ERROR = (1 << 27),
 127
 128        FATAL_ERR_HC_MASTER_ERR = (1 << 18),
 129        FATAL_ERR_PARITY_ERR_TX = (1 << 17),
 130        FATAL_ERR_PARITY_ERR_RX = (1 << 16),
 131        FATAL_ERR_DATA_UNDERRUN = (1 << 13),
 132        FATAL_ERR_DATA_OVERRUN = (1 << 12),
 133        FATAL_ERR_CRC_ERR_TX = (1 << 11),
 134        FATAL_ERR_CRC_ERR_RX = (1 << 10),
 135        FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
 136        FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
 137
 138        FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
 139            FATAL_ERR_PARITY_ERR_TX |
 140            FATAL_ERR_PARITY_ERR_RX |
 141            FATAL_ERR_DATA_UNDERRUN |
 142            FATAL_ERR_DATA_OVERRUN |
 143            FATAL_ERR_CRC_ERR_TX |
 144            FATAL_ERR_CRC_ERR_RX |
 145            FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
 146
 147        INT_ON_DATA_LENGTH_MISMATCH = (1 << 12),
 148        INT_ON_FATAL_ERR = (1 << 5),
 149        INT_ON_PHYRDY_CHG = (1 << 4),
 150
 151        INT_ON_SIGNATURE_UPDATE = (1 << 3),
 152        INT_ON_SNOTIFY_UPDATE = (1 << 2),
 153        INT_ON_SINGL_DEVICE_ERR = (1 << 1),
 154        INT_ON_CMD_COMPLETE = 1,
 155
 156        INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
 157            INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
 158
 159        /*
 160         * Host Control Register (HControl) bitdefs
 161         */
 162        HCONTROL_ONLINE_PHY_RST = (1 << 31),
 163        HCONTROL_FORCE_OFFLINE = (1 << 30),
 164        HCONTROL_LEGACY = (1 << 28),
 165        HCONTROL_PARITY_PROT_MOD = (1 << 14),
 166        HCONTROL_DPATH_PARITY = (1 << 12),
 167        HCONTROL_SNOOP_ENABLE = (1 << 10),
 168        HCONTROL_PMP_ATTACHED = (1 << 9),
 169        HCONTROL_COPYOUT_STATFIS = (1 << 8),
 170        IE_ON_FATAL_ERR = (1 << 5),
 171        IE_ON_PHYRDY_CHG = (1 << 4),
 172        IE_ON_SIGNATURE_UPDATE = (1 << 3),
 173        IE_ON_SNOTIFY_UPDATE = (1 << 2),
 174        IE_ON_SINGL_DEVICE_ERR = (1 << 1),
 175        IE_ON_CMD_COMPLETE = 1,
 176
 177        DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
 178            IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
 179            IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
 180
 181        EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
 182        DATA_SNOOP_ENABLE_V1 = (1 << 22),
 183        DATA_SNOOP_ENABLE_V2 = (1 << 28),
 184};
 185
 186/*
 187 * SATA Superset Registers
 188 */
 189enum {
 190        SSTATUS = 0,
 191        SERROR = 4,
 192        SCONTROL = 8,
 193        SNOTIFY = 0xC,
 194};
 195
 196/*
 197 * Control Status Register Set
 198 */
 199enum {
 200        TRANSCFG = 0,
 201        TRANSSTATUS = 4,
 202        LINKCFG = 8,
 203        LINKCFG1 = 0xC,
 204        LINKCFG2 = 0x10,
 205        LINKSTATUS = 0x14,
 206        LINKSTATUS1 = 0x18,
 207        PHYCTRLCFG = 0x1C,
 208        COMMANDSTAT = 0x20,
 209};
 210
 211/* TRANSCFG (transport-layer) configuration control */
 212enum {
 213        TRANSCFG_RX_WATER_MARK = (1 << 4),
 214};
 215
 216/* PHY (link-layer) configuration control */
 217enum {
 218        PHY_BIST_ENABLE = 0x01,
 219};
 220
 221/*
 222 * Command Header Table entry, i.e, command slot
 223 * 4 Dwords per command slot, command header size ==  64 Dwords.
 224 */
 225struct cmdhdr_tbl_entry {
 226        u32 cda;
 227        u32 prde_fis_len;
 228        u32 ttl;
 229        u32 desc_info;
 230};
 231
 232/*
 233 * Description information bitdefs
 234 */
 235enum {
 236        CMD_DESC_RES = (1 << 11),
 237        VENDOR_SPECIFIC_BIST = (1 << 10),
 238        CMD_DESC_SNOOP_ENABLE = (1 << 9),
 239        FPDMA_QUEUED_CMD = (1 << 8),
 240        SRST_CMD = (1 << 7),
 241        BIST = (1 << 6),
 242        ATAPI_CMD = (1 << 5),
 243};
 244
 245/*
 246 * Command Descriptor
 247 */
 248struct command_desc {
 249        u8 cfis[8 * 4];
 250        u8 sfis[8 * 4];
 251        u8 acmd[4 * 4];
 252        u8 fill[4 * 4];
 253        u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
 254        u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
 255};
 256
 257/*
 258 * Physical region table descriptor(PRD)
 259 */
 260
 261struct prde {
 262        u32 dba;
 263        u8 fill[2 * 4];
 264        u32 ddc_and_ext;
 265};
 266
 267/*
 268 * ata_port private data
 269 * This is our per-port instance data.
 270 */
 271struct sata_fsl_port_priv {
 272        struct cmdhdr_tbl_entry *cmdslot;
 273        dma_addr_t cmdslot_paddr;
 274        struct command_desc *cmdentry;
 275        dma_addr_t cmdentry_paddr;
 276};
 277
 278/*
 279 * ata_port->host_set private data
 280 */
 281struct sata_fsl_host_priv {
 282        void __iomem *hcr_base;
 283        void __iomem *ssr_base;
 284        void __iomem *csr_base;
 285        int irq;
 286        int data_snoop;
 287        struct device_attribute intr_coalescing;
 288        struct device_attribute rx_watermark;
 289};
 290
 291static void fsl_sata_set_irq_coalescing(struct ata_host *host,
 292                unsigned int count, unsigned int ticks)
 293{
 294        struct sata_fsl_host_priv *host_priv = host->private_data;
 295        void __iomem *hcr_base = host_priv->hcr_base;
 296        unsigned long flags;
 297
 298        if (count > ICC_MAX_INT_COUNT_THRESHOLD)
 299                count = ICC_MAX_INT_COUNT_THRESHOLD;
 300        else if (count < ICC_MIN_INT_COUNT_THRESHOLD)
 301                count = ICC_MIN_INT_COUNT_THRESHOLD;
 302
 303        if (ticks > ICC_MAX_INT_TICKS_THRESHOLD)
 304                ticks = ICC_MAX_INT_TICKS_THRESHOLD;
 305        else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) &&
 306                        (count > ICC_MIN_INT_COUNT_THRESHOLD))
 307                ticks = ICC_SAFE_INT_TICKS;
 308
 309        spin_lock_irqsave(&host->lock, flags);
 310        iowrite32((count << 24 | ticks), hcr_base + ICC);
 311
 312        intr_coalescing_count = count;
 313        intr_coalescing_ticks = ticks;
 314        spin_unlock_irqrestore(&host->lock, flags);
 315
 316        DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n",
 317                        intr_coalescing_count, intr_coalescing_ticks);
 318        DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x\n",
 319                        hcr_base, ioread32(hcr_base + ICC));
 320}
 321
 322static ssize_t fsl_sata_intr_coalescing_show(struct device *dev,
 323                struct device_attribute *attr, char *buf)
 324{
 325        return sprintf(buf, "%d %d\n",
 326                        intr_coalescing_count, intr_coalescing_ticks);
 327}
 328
 329static ssize_t fsl_sata_intr_coalescing_store(struct device *dev,
 330                struct device_attribute *attr,
 331                const char *buf, size_t count)
 332{
 333        unsigned int coalescing_count,  coalescing_ticks;
 334
 335        if (sscanf(buf, "%d%d",
 336                                &coalescing_count,
 337                                &coalescing_ticks) != 2) {
 338                printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
 339                return -EINVAL;
 340        }
 341
 342        fsl_sata_set_irq_coalescing(dev_get_drvdata(dev),
 343                        coalescing_count, coalescing_ticks);
 344
 345        return strlen(buf);
 346}
 347
 348static ssize_t fsl_sata_rx_watermark_show(struct device *dev,
 349                struct device_attribute *attr, char *buf)
 350{
 351        unsigned int rx_watermark;
 352        unsigned long flags;
 353        struct ata_host *host = dev_get_drvdata(dev);
 354        struct sata_fsl_host_priv *host_priv = host->private_data;
 355        void __iomem *csr_base = host_priv->csr_base;
 356
 357        spin_lock_irqsave(&host->lock, flags);
 358        rx_watermark = ioread32(csr_base + TRANSCFG);
 359        rx_watermark &= 0x1f;
 360
 361        spin_unlock_irqrestore(&host->lock, flags);
 362        return sprintf(buf, "%d\n", rx_watermark);
 363}
 364
 365static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
 366                struct device_attribute *attr,
 367                const char *buf, size_t count)
 368{
 369        unsigned int rx_watermark;
 370        unsigned long flags;
 371        struct ata_host *host = dev_get_drvdata(dev);
 372        struct sata_fsl_host_priv *host_priv = host->private_data;
 373        void __iomem *csr_base = host_priv->csr_base;
 374        u32 temp;
 375
 376        if (sscanf(buf, "%d", &rx_watermark) != 1) {
 377                printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
 378                return -EINVAL;
 379        }
 380
 381        spin_lock_irqsave(&host->lock, flags);
 382        temp = ioread32(csr_base + TRANSCFG);
 383        temp &= 0xffffffe0;
 384        iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
 385
 386        spin_unlock_irqrestore(&host->lock, flags);
 387        return strlen(buf);
 388}
 389
 390static inline unsigned int sata_fsl_tag(unsigned int tag,
 391                                        void __iomem *hcr_base)
 392{
 393        /* We let libATA core do actual (queue) tag allocation */
 394
 395        /* all non NCQ/queued commands should have tag#0 */
 396        if (ata_tag_internal(tag)) {
 397                DPRINTK("mapping internal cmds to tag#0\n");
 398                return 0;
 399        }
 400
 401        if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
 402                DPRINTK("tag %d invalid : out of range\n", tag);
 403                return 0;
 404        }
 405
 406        if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
 407                DPRINTK("tag %d invalid : in use!!\n", tag);
 408                return 0;
 409        }
 410
 411        return tag;
 412}
 413
 414static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
 415                                         unsigned int tag, u32 desc_info,
 416                                         u32 data_xfer_len, u8 num_prde,
 417                                         u8 fis_len)
 418{
 419        dma_addr_t cmd_descriptor_address;
 420
 421        cmd_descriptor_address = pp->cmdentry_paddr +
 422            tag * SATA_FSL_CMD_DESC_SIZE;
 423
 424        /* NOTE: both data_xfer_len & fis_len are Dword counts */
 425
 426        pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
 427        pp->cmdslot[tag].prde_fis_len =
 428            cpu_to_le32((num_prde << 16) | (fis_len << 2));
 429        pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
 430        pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
 431
 432        VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
 433                pp->cmdslot[tag].cda,
 434                pp->cmdslot[tag].prde_fis_len,
 435                pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
 436
 437}
 438
 439static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
 440                                     u32 *ttl, dma_addr_t cmd_desc_paddr,
 441                                     int data_snoop)
 442{
 443        struct scatterlist *sg;
 444        unsigned int num_prde = 0;
 445        u32 ttl_dwords = 0;
 446
 447        /*
 448         * NOTE : direct & indirect prdt's are contiguously allocated
 449         */
 450        struct prde *prd = (struct prde *)&((struct command_desc *)
 451                                            cmd_desc)->prdt;
 452
 453        struct prde *prd_ptr_to_indirect_ext = NULL;
 454        unsigned indirect_ext_segment_sz = 0;
 455        dma_addr_t indirect_ext_segment_paddr;
 456        unsigned int si;
 457
 458        VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
 459
 460        indirect_ext_segment_paddr = cmd_desc_paddr +
 461            SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
 462
 463        for_each_sg(qc->sg, sg, qc->n_elem, si) {
 464                dma_addr_t sg_addr = sg_dma_address(sg);
 465                u32 sg_len = sg_dma_len(sg);
 466
 467                VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
 468                        (unsigned long long)sg_addr, sg_len);
 469
 470                /* warn if each s/g element is not dword aligned */
 471                if (unlikely(sg_addr & 0x03))
 472                        ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n",
 473                                     (unsigned long long)sg_addr);
 474                if (unlikely(sg_len & 0x03))
 475                        ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n",
 476                                     sg_len);
 477
 478                if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
 479                    sg_next(sg) != NULL) {
 480                        VPRINTK("setting indirect prde\n");
 481                        prd_ptr_to_indirect_ext = prd;
 482                        prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
 483                        indirect_ext_segment_sz = 0;
 484                        ++prd;
 485                        ++num_prde;
 486                }
 487
 488                ttl_dwords += sg_len;
 489                prd->dba = cpu_to_le32(sg_addr);
 490                prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03));
 491
 492                VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
 493                        ttl_dwords, prd->dba, prd->ddc_and_ext);
 494
 495                ++num_prde;
 496                ++prd;
 497                if (prd_ptr_to_indirect_ext)
 498                        indirect_ext_segment_sz += sg_len;
 499        }
 500
 501        if (prd_ptr_to_indirect_ext) {
 502                /* set indirect extension flag along with indirect ext. size */
 503                prd_ptr_to_indirect_ext->ddc_and_ext =
 504                    cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
 505                                 data_snoop |
 506                                 (indirect_ext_segment_sz & ~0x03)));
 507        }
 508
 509        *ttl = ttl_dwords;
 510        return num_prde;
 511}
 512
 513static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
 514{
 515        struct ata_port *ap = qc->ap;
 516        struct sata_fsl_port_priv *pp = ap->private_data;
 517        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 518        void __iomem *hcr_base = host_priv->hcr_base;
 519        unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
 520        struct command_desc *cd;
 521        u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
 522        u32 num_prde = 0;
 523        u32 ttl_dwords = 0;
 524        dma_addr_t cd_paddr;
 525
 526        cd = (struct command_desc *)pp->cmdentry + tag;
 527        cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
 528
 529        ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
 530
 531        VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
 532                cd->cfis[0], cd->cfis[1], cd->cfis[2]);
 533
 534        if (qc->tf.protocol == ATA_PROT_NCQ) {
 535                VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
 536                        cd->cfis[3], cd->cfis[11]);
 537        }
 538
 539        /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
 540        if (ata_is_atapi(qc->tf.protocol)) {
 541                desc_info |= ATAPI_CMD;
 542                memset((void *)&cd->acmd, 0, 32);
 543                memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
 544        }
 545
 546        if (qc->flags & ATA_QCFLAG_DMAMAP)
 547                num_prde = sata_fsl_fill_sg(qc, (void *)cd,
 548                                            &ttl_dwords, cd_paddr,
 549                                            host_priv->data_snoop);
 550
 551        if (qc->tf.protocol == ATA_PROT_NCQ)
 552                desc_info |= FPDMA_QUEUED_CMD;
 553
 554        sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
 555                                     num_prde, 5);
 556
 557        VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
 558                desc_info, ttl_dwords, num_prde);
 559}
 560
 561static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
 562{
 563        struct ata_port *ap = qc->ap;
 564        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 565        void __iomem *hcr_base = host_priv->hcr_base;
 566        unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
 567
 568        VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
 569                ioread32(CQ + hcr_base),
 570                ioread32(CA + hcr_base),
 571                ioread32(CE + hcr_base), ioread32(CC + hcr_base));
 572
 573        iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
 574
 575        /* Simply queue command to the controller/device */
 576        iowrite32(1 << tag, CQ + hcr_base);
 577
 578        VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
 579                tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
 580
 581        VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
 582                ioread32(CE + hcr_base),
 583                ioread32(DE + hcr_base),
 584                ioread32(CC + hcr_base),
 585                ioread32(COMMANDSTAT + host_priv->csr_base));
 586
 587        return 0;
 588}
 589
 590static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
 591{
 592        struct sata_fsl_port_priv *pp = qc->ap->private_data;
 593        struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
 594        void __iomem *hcr_base = host_priv->hcr_base;
 595        unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
 596        struct command_desc *cd;
 597
 598        cd = pp->cmdentry + tag;
 599
 600        ata_tf_from_fis(cd->sfis, &qc->result_tf);
 601        return true;
 602}
 603
 604static int sata_fsl_scr_write(struct ata_link *link,
 605                              unsigned int sc_reg_in, u32 val)
 606{
 607        struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
 608        void __iomem *ssr_base = host_priv->ssr_base;
 609        unsigned int sc_reg;
 610
 611        switch (sc_reg_in) {
 612        case SCR_STATUS:
 613        case SCR_ERROR:
 614        case SCR_CONTROL:
 615        case SCR_ACTIVE:
 616                sc_reg = sc_reg_in;
 617                break;
 618        default:
 619                return -EINVAL;
 620        }
 621
 622        VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
 623
 624        iowrite32(val, ssr_base + (sc_reg * 4));
 625        return 0;
 626}
 627
 628static int sata_fsl_scr_read(struct ata_link *link,
 629                             unsigned int sc_reg_in, u32 *val)
 630{
 631        struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
 632        void __iomem *ssr_base = host_priv->ssr_base;
 633        unsigned int sc_reg;
 634
 635        switch (sc_reg_in) {
 636        case SCR_STATUS:
 637        case SCR_ERROR:
 638        case SCR_CONTROL:
 639        case SCR_ACTIVE:
 640                sc_reg = sc_reg_in;
 641                break;
 642        default:
 643                return -EINVAL;
 644        }
 645
 646        VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
 647
 648        *val = ioread32(ssr_base + (sc_reg * 4));
 649        return 0;
 650}
 651
 652static void sata_fsl_freeze(struct ata_port *ap)
 653{
 654        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 655        void __iomem *hcr_base = host_priv->hcr_base;
 656        u32 temp;
 657
 658        VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
 659                ioread32(CQ + hcr_base),
 660                ioread32(CA + hcr_base),
 661                ioread32(CE + hcr_base), ioread32(DE + hcr_base));
 662        VPRINTK("CmdStat = 0x%x\n",
 663                ioread32(host_priv->csr_base + COMMANDSTAT));
 664
 665        /* disable interrupts on the controller/port */
 666        temp = ioread32(hcr_base + HCONTROL);
 667        iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
 668
 669        VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
 670                ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
 671}
 672
 673static void sata_fsl_thaw(struct ata_port *ap)
 674{
 675        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 676        void __iomem *hcr_base = host_priv->hcr_base;
 677        u32 temp;
 678
 679        /* ack. any pending IRQs for this controller/port */
 680        temp = ioread32(hcr_base + HSTATUS);
 681
 682        VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
 683
 684        if (temp & 0x3F)
 685                iowrite32((temp & 0x3F), hcr_base + HSTATUS);
 686
 687        /* enable interrupts on the controller/port */
 688        temp = ioread32(hcr_base + HCONTROL);
 689        iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
 690
 691        VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
 692                ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
 693}
 694
 695static void sata_fsl_pmp_attach(struct ata_port *ap)
 696{
 697        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 698        void __iomem *hcr_base = host_priv->hcr_base;
 699        u32 temp;
 700
 701        temp = ioread32(hcr_base + HCONTROL);
 702        iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
 703}
 704
 705static void sata_fsl_pmp_detach(struct ata_port *ap)
 706{
 707        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 708        void __iomem *hcr_base = host_priv->hcr_base;
 709        u32 temp;
 710
 711        temp = ioread32(hcr_base + HCONTROL);
 712        temp &= ~HCONTROL_PMP_ATTACHED;
 713        iowrite32(temp, hcr_base + HCONTROL);
 714
 715        /* enable interrupts on the controller/port */
 716        temp = ioread32(hcr_base + HCONTROL);
 717        iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
 718
 719}
 720
 721static int sata_fsl_port_start(struct ata_port *ap)
 722{
 723        struct device *dev = ap->host->dev;
 724        struct sata_fsl_port_priv *pp;
 725        void *mem;
 726        dma_addr_t mem_dma;
 727        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 728        void __iomem *hcr_base = host_priv->hcr_base;
 729        u32 temp;
 730
 731        pp = kzalloc(sizeof(*pp), GFP_KERNEL);
 732        if (!pp)
 733                return -ENOMEM;
 734
 735        mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
 736                                 GFP_KERNEL);
 737        if (!mem) {
 738                kfree(pp);
 739                return -ENOMEM;
 740        }
 741        memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
 742
 743        pp->cmdslot = mem;
 744        pp->cmdslot_paddr = mem_dma;
 745
 746        mem += SATA_FSL_CMD_SLOT_SIZE;
 747        mem_dma += SATA_FSL_CMD_SLOT_SIZE;
 748
 749        pp->cmdentry = mem;
 750        pp->cmdentry_paddr = mem_dma;
 751
 752        ap->private_data = pp;
 753
 754        VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
 755                pp->cmdslot_paddr, pp->cmdentry_paddr);
 756
 757        /* Now, update the CHBA register in host controller cmd register set */
 758        iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
 759
 760        /*
 761         * Now, we can bring the controller on-line & also initiate
 762         * the COMINIT sequence, we simply return here and the boot-probing
 763         * & device discovery process is re-initiated by libATA using a
 764         * Softreset EH (dummy) session. Hence, boot probing and device
 765         * discovey will be part of sata_fsl_softreset() callback.
 766         */
 767
 768        temp = ioread32(hcr_base + HCONTROL);
 769        iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
 770
 771        VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
 772        VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
 773        VPRINTK("CHBA  = 0x%x\n", ioread32(hcr_base + CHBA));
 774
 775#ifdef CONFIG_MPC8315_DS
 776        /*
 777         * Workaround for 8315DS board 3gbps link-up issue,
 778         * currently limit SATA port to GEN1 speed
 779         */
 780        sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
 781        temp &= ~(0xF << 4);
 782        temp |= (0x1 << 4);
 783        sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp);
 784
 785        sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
 786        dev_warn(dev, "scr_control, speed limited to %x\n", temp);
 787#endif
 788
 789        return 0;
 790}
 791
 792static void sata_fsl_port_stop(struct ata_port *ap)
 793{
 794        struct device *dev = ap->host->dev;
 795        struct sata_fsl_port_priv *pp = ap->private_data;
 796        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 797        void __iomem *hcr_base = host_priv->hcr_base;
 798        u32 temp;
 799
 800        /*
 801         * Force host controller to go off-line, aborting current operations
 802         */
 803        temp = ioread32(hcr_base + HCONTROL);
 804        temp &= ~HCONTROL_ONLINE_PHY_RST;
 805        temp |= HCONTROL_FORCE_OFFLINE;
 806        iowrite32(temp, hcr_base + HCONTROL);
 807
 808        /* Poll for controller to go offline - should happen immediately */
 809        ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
 810
 811        ap->private_data = NULL;
 812        dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
 813                          pp->cmdslot, pp->cmdslot_paddr);
 814
 815        kfree(pp);
 816}
 817
 818static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
 819{
 820        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 821        void __iomem *hcr_base = host_priv->hcr_base;
 822        struct ata_taskfile tf;
 823        u32 temp;
 824
 825        temp = ioread32(hcr_base + SIGNATURE);
 826
 827        VPRINTK("raw sig = 0x%x\n", temp);
 828        VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
 829        VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
 830
 831        tf.lbah = (temp >> 24) & 0xff;
 832        tf.lbam = (temp >> 16) & 0xff;
 833        tf.lbal = (temp >> 8) & 0xff;
 834        tf.nsect = temp & 0xff;
 835
 836        return ata_dev_classify(&tf);
 837}
 838
 839static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
 840                                        unsigned long deadline)
 841{
 842        struct ata_port *ap = link->ap;
 843        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 844        void __iomem *hcr_base = host_priv->hcr_base;
 845        u32 temp;
 846        int i = 0;
 847        unsigned long start_jiffies;
 848
 849        DPRINTK("in xx_hardreset\n");
 850
 851try_offline_again:
 852        /*
 853         * Force host controller to go off-line, aborting current operations
 854         */
 855        temp = ioread32(hcr_base + HCONTROL);
 856        temp &= ~HCONTROL_ONLINE_PHY_RST;
 857        iowrite32(temp, hcr_base + HCONTROL);
 858
 859        /* Poll for controller to go offline */
 860        temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
 861                                 1, 500);
 862
 863        if (temp & ONLINE) {
 864                ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i);
 865
 866                /*
 867                 * Try to offline controller atleast twice
 868                 */
 869                i++;
 870                if (i == 2)
 871                        goto err;
 872                else
 873                        goto try_offline_again;
 874        }
 875
 876        DPRINTK("hardreset, controller off-lined\n");
 877        VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
 878        VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
 879
 880        /*
 881         * PHY reset should remain asserted for atleast 1ms
 882         */
 883        ata_msleep(ap, 1);
 884
 885        /*
 886         * Now, bring the host controller online again, this can take time
 887         * as PHY reset and communication establishment, 1st D2H FIS and
 888         * device signature update is done, on safe side assume 500ms
 889         * NOTE : Host online status may be indicated immediately!!
 890         */
 891
 892        temp = ioread32(hcr_base + HCONTROL);
 893        temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
 894        temp |= HCONTROL_PMP_ATTACHED;
 895        iowrite32(temp, hcr_base + HCONTROL);
 896
 897        temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
 898
 899        if (!(temp & ONLINE)) {
 900                ata_port_err(ap, "Hardreset failed, not on-lined\n");
 901                goto err;
 902        }
 903
 904        DPRINTK("hardreset, controller off-lined & on-lined\n");
 905        VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
 906        VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
 907
 908        /*
 909         * First, wait for the PHYRDY change to occur before waiting for
 910         * the signature, and also verify if SStatus indicates device
 911         * presence
 912         */
 913
 914        temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
 915        if ((!(temp & 0x10)) || ata_link_offline(link)) {
 916                ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n",
 917                              ioread32(hcr_base + HSTATUS));
 918                *class = ATA_DEV_NONE;
 919                return 0;
 920        }
 921
 922        /*
 923         * Wait for the first D2H from device,i.e,signature update notification
 924         */
 925        start_jiffies = jiffies;
 926        temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
 927                        500, jiffies_to_msecs(deadline - start_jiffies));
 928
 929        if ((temp & 0xFF) != 0x18) {
 930                ata_port_warn(ap, "No Signature Update\n");
 931                *class = ATA_DEV_NONE;
 932                goto do_followup_srst;
 933        } else {
 934                ata_port_info(ap, "Signature Update detected @ %d msecs\n",
 935                              jiffies_to_msecs(jiffies - start_jiffies));
 936                *class = sata_fsl_dev_classify(ap);
 937                return 0;
 938        }
 939
 940do_followup_srst:
 941        /*
 942         * request libATA to perform follow-up softreset
 943         */
 944        return -EAGAIN;
 945
 946err:
 947        return -EIO;
 948}
 949
 950static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
 951                                        unsigned long deadline)
 952{
 953        struct ata_port *ap = link->ap;
 954        struct sata_fsl_port_priv *pp = ap->private_data;
 955        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 956        void __iomem *hcr_base = host_priv->hcr_base;
 957        int pmp = sata_srst_pmp(link);
 958        u32 temp;
 959        struct ata_taskfile tf;
 960        u8 *cfis;
 961        u32 Serror;
 962
 963        DPRINTK("in xx_softreset\n");
 964
 965        if (ata_link_offline(link)) {
 966                DPRINTK("PHY reports no device\n");
 967                *class = ATA_DEV_NONE;
 968                return 0;
 969        }
 970
 971        /*
 972         * Send a device reset (SRST) explicitly on command slot #0
 973         * Check : will the command queue (reg) be cleared during offlining ??
 974         * Also we will be online only if Phy commn. has been established
 975         * and device presence has been detected, therefore if we have
 976         * reached here, we can send a command to the target device
 977         */
 978
 979        DPRINTK("Sending SRST/device reset\n");
 980
 981        ata_tf_init(link->device, &tf);
 982        cfis = (u8 *) &pp->cmdentry->cfis;
 983
 984        /* device reset/SRST is a control register update FIS, uses tag0 */
 985        sata_fsl_setup_cmd_hdr_entry(pp, 0,
 986                SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
 987
 988        tf.ctl |= ATA_SRST;     /* setup SRST bit in taskfile control reg */
 989        ata_tf_to_fis(&tf, pmp, 0, cfis);
 990
 991        DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
 992                cfis[0], cfis[1], cfis[2], cfis[3]);
 993
 994        /*
 995         * Queue SRST command to the controller/device, ensure that no
 996         * other commands are active on the controller/device
 997         */
 998
 999        DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
1000                ioread32(CQ + hcr_base),
1001                ioread32(CA + hcr_base), ioread32(CC + hcr_base));
1002
1003        iowrite32(0xFFFF, CC + hcr_base);
1004        if (pmp != SATA_PMP_CTRL_PORT)
1005                iowrite32(pmp, CQPMP + hcr_base);
1006        iowrite32(1, CQ + hcr_base);
1007
1008        temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
1009        if (temp & 0x1) {
1010                ata_port_warn(ap, "ATA_SRST issue failed\n");
1011
1012                DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
1013                        ioread32(CQ + hcr_base),
1014                        ioread32(CA + hcr_base), ioread32(CC + hcr_base));
1015
1016                sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
1017
1018                DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1019                DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1020                DPRINTK("Serror = 0x%x\n", Serror);
1021                goto err;
1022        }
1023
1024        ata_msleep(ap, 1);
1025
1026        /*
1027         * SATA device enters reset state after receiving a Control register
1028         * FIS with SRST bit asserted and it awaits another H2D Control reg.
1029         * FIS with SRST bit cleared, then the device does internal diags &
1030         * initialization, followed by indicating it's initialization status
1031         * using ATA signature D2H register FIS to the host controller.
1032         */
1033
1034        sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
1035                                      0, 0, 5);
1036
1037        tf.ctl &= ~ATA_SRST;    /* 2nd H2D Ctl. register FIS */
1038        ata_tf_to_fis(&tf, pmp, 0, cfis);
1039
1040        if (pmp != SATA_PMP_CTRL_PORT)
1041                iowrite32(pmp, CQPMP + hcr_base);
1042        iowrite32(1, CQ + hcr_base);
1043        ata_msleep(ap, 150);            /* ?? */
1044
1045        /*
1046         * The above command would have signalled an interrupt on command
1047         * complete, which needs special handling, by clearing the Nth
1048         * command bit of the CCreg
1049         */
1050        iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
1051
1052        DPRINTK("SATA FSL : Now checking device signature\n");
1053
1054        *class = ATA_DEV_NONE;
1055
1056        /* Verify if SStatus indicates device presence */
1057        if (ata_link_online(link)) {
1058                /*
1059                 * if we are here, device presence has been detected,
1060                 * 1st D2H FIS would have been received, but sfis in
1061                 * command desc. is not updated, but signature register
1062                 * would have been updated
1063                 */
1064
1065                *class = sata_fsl_dev_classify(ap);
1066
1067                DPRINTK("class = %d\n", *class);
1068                VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
1069                VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
1070        }
1071
1072        return 0;
1073
1074err:
1075        return -EIO;
1076}
1077
1078static void sata_fsl_error_handler(struct ata_port *ap)
1079{
1080
1081        DPRINTK("in xx_error_handler\n");
1082        sata_pmp_error_handler(ap);
1083
1084}
1085
1086static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
1087{
1088        if (qc->flags & ATA_QCFLAG_FAILED)
1089                qc->err_mask |= AC_ERR_OTHER;
1090
1091        if (qc->err_mask) {
1092                /* make DMA engine forget about the failed command */
1093
1094        }
1095}
1096
1097static void sata_fsl_error_intr(struct ata_port *ap)
1098{
1099        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1100        void __iomem *hcr_base = host_priv->hcr_base;
1101        u32 hstatus, dereg=0, cereg = 0, SError = 0;
1102        unsigned int err_mask = 0, action = 0;
1103        int freeze = 0, abort=0;
1104        struct ata_link *link = NULL;
1105        struct ata_queued_cmd *qc = NULL;
1106        struct ata_eh_info *ehi;
1107
1108        hstatus = ioread32(hcr_base + HSTATUS);
1109        cereg = ioread32(hcr_base + CE);
1110
1111        /* first, analyze and record host port events */
1112        link = &ap->link;
1113        ehi = &link->eh_info;
1114        ata_ehi_clear_desc(ehi);
1115
1116        /*
1117         * Handle & Clear SError
1118         */
1119
1120        sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1121        if (unlikely(SError & 0xFFFF0000))
1122                sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
1123
1124        DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1125                hstatus, cereg, ioread32(hcr_base + DE), SError);
1126
1127        /* handle fatal errors */
1128        if (hstatus & FATAL_ERROR_DECODE) {
1129                ehi->err_mask |= AC_ERR_ATA_BUS;
1130                ehi->action |= ATA_EH_SOFTRESET;
1131
1132                freeze = 1;
1133        }
1134
1135        /* Handle SDB FIS receive & notify update */
1136        if (hstatus & INT_ON_SNOTIFY_UPDATE)
1137                sata_async_notification(ap);
1138
1139        /* Handle PHYRDY change notification */
1140        if (hstatus & INT_ON_PHYRDY_CHG) {
1141                DPRINTK("SATA FSL: PHYRDY change indication\n");
1142
1143                /* Setup a soft-reset EH action */
1144                ata_ehi_hotplugged(ehi);
1145                ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
1146                freeze = 1;
1147        }
1148
1149        /* handle single device errors */
1150        if (cereg) {
1151                /*
1152                 * clear the command error, also clears queue to the device
1153                 * in error, and we can (re)issue commands to this device.
1154                 * When a device is in error all commands queued into the
1155                 * host controller and at the device are considered aborted
1156                 * and the queue for that device is stopped. Now, after
1157                 * clearing the device error, we can issue commands to the
1158                 * device to interrogate it to find the source of the error.
1159                 */
1160                abort = 1;
1161
1162                DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1163                        ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1164
1165                /* find out the offending link and qc */
1166                if (ap->nr_pmp_links) {
1167                        unsigned int dev_num;
1168
1169                        dereg = ioread32(hcr_base + DE);
1170                        iowrite32(dereg, hcr_base + DE);
1171                        iowrite32(cereg, hcr_base + CE);
1172
1173                        dev_num = ffs(dereg) - 1;
1174                        if (dev_num < ap->nr_pmp_links && dereg != 0) {
1175                                link = &ap->pmp_link[dev_num];
1176                                ehi = &link->eh_info;
1177                                qc = ata_qc_from_tag(ap, link->active_tag);
1178                                /*
1179                                 * We should consider this as non fatal error,
1180                                 * and TF must be updated as done below.
1181                                 */
1182
1183                                err_mask |= AC_ERR_DEV;
1184
1185                        } else {
1186                                err_mask |= AC_ERR_HSM;
1187                                action |= ATA_EH_HARDRESET;
1188                                freeze = 1;
1189                        }
1190                } else {
1191                        dereg = ioread32(hcr_base + DE);
1192                        iowrite32(dereg, hcr_base + DE);
1193                        iowrite32(cereg, hcr_base + CE);
1194
1195                        qc = ata_qc_from_tag(ap, link->active_tag);
1196                        /*
1197                         * We should consider this as non fatal error,
1198                         * and TF must be updated as done below.
1199                        */
1200                        err_mask |= AC_ERR_DEV;
1201                }
1202        }
1203
1204        /* record error info */
1205        if (qc)
1206                qc->err_mask |= err_mask;
1207        else
1208                ehi->err_mask |= err_mask;
1209
1210        ehi->action |= action;
1211
1212        /* freeze or abort */
1213        if (freeze)
1214                ata_port_freeze(ap);
1215        else if (abort) {
1216                if (qc)
1217                        ata_link_abort(qc->dev->link);
1218                else
1219                        ata_port_abort(ap);
1220        }
1221}
1222
1223static void sata_fsl_host_intr(struct ata_port *ap)
1224{
1225        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1226        void __iomem *hcr_base = host_priv->hcr_base;
1227        u32 hstatus, done_mask = 0;
1228        struct ata_queued_cmd *qc;
1229        u32 SError;
1230        u32 tag;
1231        u32 status_mask = INT_ON_ERROR;
1232
1233        hstatus = ioread32(hcr_base + HSTATUS);
1234
1235        sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1236
1237        /* Read command completed register */
1238        done_mask = ioread32(hcr_base + CC);
1239
1240        /* Workaround for data length mismatch errata */
1241        if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) {
1242                for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
1243                        qc = ata_qc_from_tag(ap, tag);
1244                        if (qc && ata_is_atapi(qc->tf.protocol)) {
1245                                u32 hcontrol;
1246                                /* Set HControl[27] to clear error registers */
1247                                hcontrol = ioread32(hcr_base + HCONTROL);
1248                                iowrite32(hcontrol | CLEAR_ERROR,
1249                                                hcr_base + HCONTROL);
1250
1251                                /* Clear HControl[27] */
1252                                iowrite32(hcontrol & ~CLEAR_ERROR,
1253                                                hcr_base + HCONTROL);
1254
1255                                /* Clear SError[E] bit */
1256                                sata_fsl_scr_write(&ap->link, SCR_ERROR,
1257                                                SError);
1258
1259                                /* Ignore fatal error and device error */
1260                                status_mask &= ~(INT_ON_SINGL_DEVICE_ERR
1261                                                | INT_ON_FATAL_ERR);
1262                                break;
1263                        }
1264                }
1265        }
1266
1267        if (unlikely(SError & 0xFFFF0000)) {
1268                DPRINTK("serror @host_intr : 0x%x\n", SError);
1269                sata_fsl_error_intr(ap);
1270        }
1271
1272        if (unlikely(hstatus & status_mask)) {
1273                DPRINTK("error interrupt!!\n");
1274                sata_fsl_error_intr(ap);
1275                return;
1276        }
1277
1278        VPRINTK("Status of all queues :\n");
1279        VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
1280                done_mask,
1281                ioread32(hcr_base + CA),
1282                ioread32(hcr_base + CE),
1283                ioread32(hcr_base + CQ),
1284                ap->qc_active);
1285
1286        if (done_mask & ap->qc_active) {
1287                int i;
1288                /* clear CC bit, this will also complete the interrupt */
1289                iowrite32(done_mask, hcr_base + CC);
1290
1291                DPRINTK("Status of all queues :\n");
1292                DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1293                        done_mask, ioread32(hcr_base + CA),
1294                        ioread32(hcr_base + CE));
1295
1296                for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1297                        if (done_mask & (1 << i))
1298                                DPRINTK
1299                                    ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1300                                     i, ioread32(hcr_base + CC),
1301                                     ioread32(hcr_base + CA));
1302                }
1303                ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
1304                return;
1305
1306        } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) {
1307                iowrite32(1, hcr_base + CC);
1308                qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1309
1310                DPRINTK("completing non-ncq cmd, CC=0x%x\n",
1311                         ioread32(hcr_base + CC));
1312
1313                if (qc) {
1314                        ata_qc_complete(qc);
1315                }
1316        } else {
1317                /* Spurious Interrupt!! */
1318                DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1319                        ioread32(hcr_base + CC));
1320                iowrite32(done_mask, hcr_base + CC);
1321                return;
1322        }
1323}
1324
1325static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1326{
1327        struct ata_host *host = dev_instance;
1328        struct sata_fsl_host_priv *host_priv = host->private_data;
1329        void __iomem *hcr_base = host_priv->hcr_base;
1330        u32 interrupt_enables;
1331        unsigned handled = 0;
1332        struct ata_port *ap;
1333
1334        /* ack. any pending IRQs for this controller/port */
1335        interrupt_enables = ioread32(hcr_base + HSTATUS);
1336        interrupt_enables &= 0x3F;
1337
1338        DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1339
1340        if (!interrupt_enables)
1341                return IRQ_NONE;
1342
1343        spin_lock(&host->lock);
1344
1345        /* Assuming one port per host controller */
1346
1347        ap = host->ports[0];
1348        if (ap) {
1349                sata_fsl_host_intr(ap);
1350        } else {
1351                dev_warn(host->dev, "interrupt on disabled port 0\n");
1352        }
1353
1354        iowrite32(interrupt_enables, hcr_base + HSTATUS);
1355        handled = 1;
1356
1357        spin_unlock(&host->lock);
1358
1359        return IRQ_RETVAL(handled);
1360}
1361
1362/*
1363 * Multiple ports are represented by multiple SATA controllers with
1364 * one port per controller
1365 */
1366static int sata_fsl_init_controller(struct ata_host *host)
1367{
1368        struct sata_fsl_host_priv *host_priv = host->private_data;
1369        void __iomem *hcr_base = host_priv->hcr_base;
1370        u32 temp;
1371
1372        /*
1373         * NOTE : We cannot bring the controller online before setting
1374         * the CHBA, hence main controller initialization is done as
1375         * part of the port_start() callback
1376         */
1377
1378        /* sata controller to operate in enterprise mode */
1379        temp = ioread32(hcr_base + HCONTROL);
1380        iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL);
1381
1382        /* ack. any pending IRQs for this controller/port */
1383        temp = ioread32(hcr_base + HSTATUS);
1384        if (temp & 0x3F)
1385                iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1386
1387        /* Keep interrupts disabled on the controller */
1388        temp = ioread32(hcr_base + HCONTROL);
1389        iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1390
1391        /* Disable interrupt coalescing control(icc), for the moment */
1392        DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1393        iowrite32(0x01000000, hcr_base + ICC);
1394
1395        /* clear error registers, SError is cleared by libATA  */
1396        iowrite32(0x00000FFFF, hcr_base + CE);
1397        iowrite32(0x00000FFFF, hcr_base + DE);
1398
1399        /*
1400         * reset the number of command complete bits which will cause the
1401         * interrupt to be signaled
1402         */
1403        fsl_sata_set_irq_coalescing(host, intr_coalescing_count,
1404                        intr_coalescing_ticks);
1405
1406        /*
1407         * host controller will be brought on-line, during xx_port_start()
1408         * callback, that should also initiate the OOB, COMINIT sequence
1409         */
1410
1411        DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1412        DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1413
1414        return 0;
1415}
1416
1417/*
1418 * scsi mid-layer and libata interface structures
1419 */
1420static struct scsi_host_template sata_fsl_sht = {
1421        ATA_NCQ_SHT("sata_fsl"),
1422        .can_queue = SATA_FSL_QUEUE_DEPTH,
1423        .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1424        .dma_boundary = ATA_DMA_BOUNDARY,
1425};
1426
1427static struct ata_port_operations sata_fsl_ops = {
1428        .inherits               = &sata_pmp_port_ops,
1429
1430        .qc_defer = ata_std_qc_defer,
1431        .qc_prep = sata_fsl_qc_prep,
1432        .qc_issue = sata_fsl_qc_issue,
1433        .qc_fill_rtf = sata_fsl_qc_fill_rtf,
1434
1435        .scr_read = sata_fsl_scr_read,
1436        .scr_write = sata_fsl_scr_write,
1437
1438        .freeze = sata_fsl_freeze,
1439        .thaw = sata_fsl_thaw,
1440        .softreset = sata_fsl_softreset,
1441        .hardreset = sata_fsl_hardreset,
1442        .pmp_softreset = sata_fsl_softreset,
1443        .error_handler = sata_fsl_error_handler,
1444        .post_internal_cmd = sata_fsl_post_internal_cmd,
1445
1446        .port_start = sata_fsl_port_start,
1447        .port_stop = sata_fsl_port_stop,
1448
1449        .pmp_attach = sata_fsl_pmp_attach,
1450        .pmp_detach = sata_fsl_pmp_detach,
1451};
1452
1453static const struct ata_port_info sata_fsl_port_info[] = {
1454        {
1455         .flags = SATA_FSL_HOST_FLAGS,
1456         .pio_mask = ATA_PIO4,
1457         .udma_mask = ATA_UDMA6,
1458         .port_ops = &sata_fsl_ops,
1459         },
1460};
1461
1462static int sata_fsl_probe(struct platform_device *ofdev)
1463{
1464        int retval = -ENXIO;
1465        void __iomem *hcr_base = NULL;
1466        void __iomem *ssr_base = NULL;
1467        void __iomem *csr_base = NULL;
1468        struct sata_fsl_host_priv *host_priv = NULL;
1469        int irq;
1470        struct ata_host *host = NULL;
1471        u32 temp;
1472
1473        struct ata_port_info pi = sata_fsl_port_info[0];
1474        const struct ata_port_info *ppi[] = { &pi, NULL };
1475
1476        dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n");
1477
1478        hcr_base = of_iomap(ofdev->dev.of_node, 0);
1479        if (!hcr_base)
1480                goto error_exit_with_cleanup;
1481
1482        ssr_base = hcr_base + 0x100;
1483        csr_base = hcr_base + 0x140;
1484
1485        if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
1486                temp = ioread32(csr_base + TRANSCFG);
1487                temp = temp & 0xffffffe0;
1488                iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
1489        }
1490
1491        DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1492        DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1493        DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1494
1495        host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1496        if (!host_priv)
1497                goto error_exit_with_cleanup;
1498
1499        host_priv->hcr_base = hcr_base;
1500        host_priv->ssr_base = ssr_base;
1501        host_priv->csr_base = csr_base;
1502
1503        irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1504        if (irq < 0) {
1505                dev_err(&ofdev->dev, "invalid irq from platform\n");
1506                goto error_exit_with_cleanup;
1507        }
1508        host_priv->irq = irq;
1509
1510        if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2"))
1511                host_priv->data_snoop = DATA_SNOOP_ENABLE_V2;
1512        else
1513                host_priv->data_snoop = DATA_SNOOP_ENABLE_V1;
1514
1515        /* allocate host structure */
1516        host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1517        if (!host) {
1518                retval = -ENOMEM;
1519                goto error_exit_with_cleanup;
1520        }
1521
1522        /* host->iomap is not used currently */
1523        host->private_data = host_priv;
1524
1525        /* initialize host controller */
1526        sata_fsl_init_controller(host);
1527
1528        /*
1529         * Now, register with libATA core, this will also initiate the
1530         * device discovery process, invoking our port_start() handler &
1531         * error_handler() to execute a dummy Softreset EH session
1532         */
1533        ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1534                          &sata_fsl_sht);
1535
1536        platform_set_drvdata(ofdev, host);
1537
1538        host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show;
1539        host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store;
1540        sysfs_attr_init(&host_priv->intr_coalescing.attr);
1541        host_priv->intr_coalescing.attr.name = "intr_coalescing";
1542        host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR;
1543        retval = device_create_file(host->dev, &host_priv->intr_coalescing);
1544        if (retval)
1545                goto error_exit_with_cleanup;
1546
1547        host_priv->rx_watermark.show = fsl_sata_rx_watermark_show;
1548        host_priv->rx_watermark.store = fsl_sata_rx_watermark_store;
1549        sysfs_attr_init(&host_priv->rx_watermark.attr);
1550        host_priv->rx_watermark.attr.name = "rx_watermark";
1551        host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR;
1552        retval = device_create_file(host->dev, &host_priv->rx_watermark);
1553        if (retval) {
1554                device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1555                goto error_exit_with_cleanup;
1556        }
1557
1558        return 0;
1559
1560error_exit_with_cleanup:
1561
1562        if (host)
1563                ata_host_detach(host);
1564
1565        if (hcr_base)
1566                iounmap(hcr_base);
1567        kfree(host_priv);
1568
1569        return retval;
1570}
1571
1572static int sata_fsl_remove(struct platform_device *ofdev)
1573{
1574        struct ata_host *host = platform_get_drvdata(ofdev);
1575        struct sata_fsl_host_priv *host_priv = host->private_data;
1576
1577        device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1578        device_remove_file(&ofdev->dev, &host_priv->rx_watermark);
1579
1580        ata_host_detach(host);
1581
1582        irq_dispose_mapping(host_priv->irq);
1583        iounmap(host_priv->hcr_base);
1584        kfree(host_priv);
1585
1586        return 0;
1587}
1588
1589#ifdef CONFIG_PM
1590static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
1591{
1592        struct ata_host *host = platform_get_drvdata(op);
1593        return ata_host_suspend(host, state);
1594}
1595
1596static int sata_fsl_resume(struct platform_device *op)
1597{
1598        struct ata_host *host = platform_get_drvdata(op);
1599        struct sata_fsl_host_priv *host_priv = host->private_data;
1600        int ret;
1601        void __iomem *hcr_base = host_priv->hcr_base;
1602        struct ata_port *ap = host->ports[0];
1603        struct sata_fsl_port_priv *pp = ap->private_data;
1604
1605        ret = sata_fsl_init_controller(host);
1606        if (ret) {
1607                dev_err(&op->dev, "Error initializing hardware\n");
1608                return ret;
1609        }
1610
1611        /* Recovery the CHBA register in host controller cmd register set */
1612        iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1613
1614        iowrite32((ioread32(hcr_base + HCONTROL)
1615                                | HCONTROL_ONLINE_PHY_RST
1616                                | HCONTROL_SNOOP_ENABLE
1617                                | HCONTROL_PMP_ATTACHED),
1618                        hcr_base + HCONTROL);
1619
1620        ata_host_resume(host);
1621        return 0;
1622}
1623#endif
1624
1625static struct of_device_id fsl_sata_match[] = {
1626        {
1627                .compatible = "fsl,pq-sata",
1628        },
1629        {
1630                .compatible = "fsl,pq-sata-v2",
1631        },
1632        {},
1633};
1634
1635MODULE_DEVICE_TABLE(of, fsl_sata_match);
1636
1637static struct platform_driver fsl_sata_driver = {
1638        .driver = {
1639                .name = "fsl-sata",
1640                .owner = THIS_MODULE,
1641                .of_match_table = fsl_sata_match,
1642        },
1643        .probe          = sata_fsl_probe,
1644        .remove         = sata_fsl_remove,
1645#ifdef CONFIG_PM
1646        .suspend        = sata_fsl_suspend,
1647        .resume         = sata_fsl_resume,
1648#endif
1649};
1650
1651module_platform_driver(fsl_sata_driver);
1652
1653MODULE_LICENSE("GPL");
1654MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1655MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1656MODULE_VERSION("1.10");
1657
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