linux/drivers/ata/ata_piix.c
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   1/*
   2 *    ata_piix.c - Intel PATA/SATA controllers
   3 *
   4 *    Maintained by:  Tejun Heo <tj@kernel.org>
   5 *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6 *                  on emails.
   7 *
   8 *
   9 *      Copyright 2003-2005 Red Hat Inc
  10 *      Copyright 2003-2005 Jeff Garzik
  11 *
  12 *
  13 *      Copyright header from piix.c:
  14 *
  15 *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
  16 *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  17 *  Copyright (C) 2003 Red Hat Inc
  18 *
  19 *
  20 *  This program is free software; you can redistribute it and/or modify
  21 *  it under the terms of the GNU General Public License as published by
  22 *  the Free Software Foundation; either version 2, or (at your option)
  23 *  any later version.
  24 *
  25 *  This program is distributed in the hope that it will be useful,
  26 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  27 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28 *  GNU General Public License for more details.
  29 *
  30 *  You should have received a copy of the GNU General Public License
  31 *  along with this program; see the file COPYING.  If not, write to
  32 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  33 *
  34 *
  35 *  libata documentation is available via 'make {ps|pdf}docs',
  36 *  as Documentation/DocBook/libata.*
  37 *
  38 *  Hardware documentation available at http://developer.intel.com/
  39 *
  40 * Documentation
  41 *      Publicly available from Intel web site. Errata documentation
  42 * is also publicly available. As an aide to anyone hacking on this
  43 * driver the list of errata that are relevant is below, going back to
  44 * PIIX4. Older device documentation is now a bit tricky to find.
  45 *
  46 * The chipsets all follow very much the same design. The original Triton
  47 * series chipsets do _not_ support independent device timings, but this
  48 * is fixed in Triton II. With the odd mobile exception the chips then
  49 * change little except in gaining more modes until SATA arrives. This
  50 * driver supports only the chips with independent timing (that is those
  51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
  52 * for the early chip drivers.
  53 *
  54 * Errata of note:
  55 *
  56 * Unfixable
  57 *      PIIX4    errata #9      - Only on ultra obscure hw
  58 *      ICH3     errata #13     - Not observed to affect real hw
  59 *                                by Intel
  60 *
  61 * Things we must deal with
  62 *      PIIX4   errata #10      - BM IDE hang with non UDMA
  63 *                                (must stop/start dma to recover)
  64 *      440MX   errata #15      - As PIIX4 errata #10
  65 *      PIIX4   errata #15      - Must not read control registers
  66 *                                during a PIO transfer
  67 *      440MX   errata #13      - As PIIX4 errata #15
  68 *      ICH2    errata #21      - DMA mode 0 doesn't work right
  69 *      ICH0/1  errata #55      - As ICH2 errata #21
  70 *      ICH2    spec c #9       - Extra operations needed to handle
  71 *                                drive hotswap [NOT YET SUPPORTED]
  72 *      ICH2    spec c #20      - IDE PRD must not cross a 64K boundary
  73 *                                and must be dword aligned
  74 *      ICH2    spec c #24      - UDMA mode 4,5 t85/86 should be 6ns not 3.3
  75 *      ICH7    errata #16      - MWDMA1 timings are incorrect
  76 *
  77 * Should have been BIOS fixed:
  78 *      450NX:  errata #19      - DMA hangs on old 450NX
  79 *      450NX:  errata #20      - DMA hangs on old 450NX
  80 *      450NX:  errata #25      - Corruption with DMA on old 450NX
  81 *      ICH3    errata #15      - IDE deadlock under high load
  82 *                                (BIOS must set dev 31 fn 0 bit 23)
  83 *      ICH3    errata #18      - Don't use native mode
  84 */
  85
  86#include <linux/kernel.h>
  87#include <linux/module.h>
  88#include <linux/pci.h>
  89#include <linux/init.h>
  90#include <linux/blkdev.h>
  91#include <linux/delay.h>
  92#include <linux/device.h>
  93#include <linux/gfp.h>
  94#include <scsi/scsi_host.h>
  95#include <linux/libata.h>
  96#include <linux/dmi.h>
  97
  98#define DRV_NAME        "ata_piix"
  99#define DRV_VERSION     "2.13"
 100
 101enum {
 102        PIIX_IOCFG              = 0x54, /* IDE I/O configuration register */
 103        ICH5_PMR                = 0x90, /* port mapping register */
 104        ICH5_PCS                = 0x92, /* port control and status */
 105        PIIX_SIDPR_BAR          = 5,
 106        PIIX_SIDPR_LEN          = 16,
 107        PIIX_SIDPR_IDX          = 0,
 108        PIIX_SIDPR_DATA         = 4,
 109
 110        PIIX_FLAG_CHECKINTR     = (1 << 28), /* make sure PCI INTx enabled */
 111        PIIX_FLAG_SIDPR         = (1 << 29), /* SATA idx/data pair regs */
 112
 113        PIIX_PATA_FLAGS         = ATA_FLAG_SLAVE_POSS,
 114        PIIX_SATA_FLAGS         = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
 115
 116        PIIX_FLAG_PIO16         = (1 << 30), /*support 16bit PIO only*/
 117
 118        PIIX_80C_PRI            = (1 << 5) | (1 << 4),
 119        PIIX_80C_SEC            = (1 << 7) | (1 << 6),
 120
 121        /* constants for mapping table */
 122        P0                      = 0,  /* port 0 */
 123        P1                      = 1,  /* port 1 */
 124        P2                      = 2,  /* port 2 */
 125        P3                      = 3,  /* port 3 */
 126        IDE                     = -1, /* IDE */
 127        NA                      = -2, /* not available */
 128        RV                      = -3, /* reserved */
 129
 130        PIIX_AHCI_DEVICE        = 6,
 131
 132        /* host->flags bits */
 133        PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
 134};
 135
 136enum piix_controller_ids {
 137        /* controller IDs */
 138        piix_pata_mwdma,        /* PIIX3 MWDMA only */
 139        piix_pata_33,           /* PIIX4 at 33Mhz */
 140        ich_pata_33,            /* ICH up to UDMA 33 only */
 141        ich_pata_66,            /* ICH up to 66 Mhz */
 142        ich_pata_100,           /* ICH up to UDMA 100 */
 143        ich_pata_100_nomwdma1,  /* ICH up to UDMA 100 but with no MWDMA1*/
 144        ich5_sata,
 145        ich6_sata,
 146        ich6m_sata,
 147        ich8_sata,
 148        ich8_2port_sata,
 149        ich8m_apple_sata,       /* locks up on second port enable */
 150        tolapai_sata,
 151        piix_pata_vmw,                  /* PIIX4 for VMware, spurious DMA_ERR */
 152        ich8_sata_snb,
 153        ich8_2port_sata_snb,
 154        ich8_2port_sata_byt,
 155};
 156
 157struct piix_map_db {
 158        const u32 mask;
 159        const u16 port_enable;
 160        const int map[][4];
 161};
 162
 163struct piix_host_priv {
 164        const int *map;
 165        u32 saved_iocfg;
 166        void __iomem *sidpr;
 167};
 168
 169static unsigned int in_module_init = 1;
 170
 171static const struct pci_device_id piix_pci_tbl[] = {
 172        /* Intel PIIX3 for the 430HX etc */
 173        { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
 174        /* VMware ICH4 */
 175        { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
 176        /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
 177        /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
 178        { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 179        /* Intel PIIX4 */
 180        { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 181        /* Intel PIIX4 */
 182        { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 183        /* Intel PIIX */
 184        { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 185        /* Intel ICH (i810, i815, i840) UDMA 66*/
 186        { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
 187        /* Intel ICH0 : UDMA 33*/
 188        { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
 189        /* Intel ICH2M */
 190        { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 191        /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
 192        { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 193        /*  Intel ICH3M */
 194        { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 195        /* Intel ICH3 (E7500/1) UDMA 100 */
 196        { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 197        /* Intel ICH4-L */
 198        { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 199        /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
 200        { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 201        { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 202        /* Intel ICH5 */
 203        { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 204        /* C-ICH (i810E2) */
 205        { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 206        /* ESB (855GME/875P + 6300ESB) UDMA 100  */
 207        { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 208        /* ICH6 (and 6) (i915) UDMA 100 */
 209        { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 210        /* ICH7/7-R (i945, i975) UDMA 100*/
 211        { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
 212        { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
 213        /* ICH8 Mobile PATA Controller */
 214        { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 215
 216        /* SATA ports */
 217
 218        /* 82801EB (ICH5) */
 219        { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 220        /* 82801EB (ICH5) */
 221        { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 222        /* 6300ESB (ICH5 variant with broken PCS present bits) */
 223        { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 224        /* 6300ESB pretending RAID */
 225        { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 226        /* 82801FB/FW (ICH6/ICH6W) */
 227        { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 228        /* 82801FR/FRW (ICH6R/ICH6RW) */
 229        { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 230        /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
 231         * Attach iff the controller is in IDE mode. */
 232        { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
 233          PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
 234        /* 82801GB/GR/GH (ICH7, identical to ICH6) */
 235        { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 236        /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
 237        { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
 238        /* Enterprise Southbridge 2 (631xESB/632xESB) */
 239        { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 240        /* SATA Controller 1 IDE (ICH8) */
 241        { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 242        /* SATA Controller 2 IDE (ICH8) */
 243        { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 244        /* Mobile SATA Controller IDE (ICH8M), Apple */
 245        { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
 246        { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
 247        { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
 248        /* Mobile SATA Controller IDE (ICH8M) */
 249        { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 250        /* SATA Controller IDE (ICH9) */
 251        { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 252        /* SATA Controller IDE (ICH9) */
 253        { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 254        /* SATA Controller IDE (ICH9) */
 255        { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 256        /* SATA Controller IDE (ICH9M) */
 257        { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 258        /* SATA Controller IDE (ICH9M) */
 259        { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 260        /* SATA Controller IDE (ICH9M) */
 261        { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 262        /* SATA Controller IDE (Tolapai) */
 263        { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
 264        /* SATA Controller IDE (ICH10) */
 265        { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 266        /* SATA Controller IDE (ICH10) */
 267        { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 268        /* SATA Controller IDE (ICH10) */
 269        { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 270        /* SATA Controller IDE (ICH10) */
 271        { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 272        /* SATA Controller IDE (PCH) */
 273        { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 274        /* SATA Controller IDE (PCH) */
 275        { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 276        /* SATA Controller IDE (PCH) */
 277        { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 278        /* SATA Controller IDE (PCH) */
 279        { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 280        /* SATA Controller IDE (PCH) */
 281        { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 282        /* SATA Controller IDE (PCH) */
 283        { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 284        /* SATA Controller IDE (CPT) */
 285        { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 286        /* SATA Controller IDE (CPT) */
 287        { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 288        /* SATA Controller IDE (CPT) */
 289        { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 290        /* SATA Controller IDE (CPT) */
 291        { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 292        /* SATA Controller IDE (PBG) */
 293        { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 294        /* SATA Controller IDE (PBG) */
 295        { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 296        /* SATA Controller IDE (Panther Point) */
 297        { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 298        /* SATA Controller IDE (Panther Point) */
 299        { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 300        /* SATA Controller IDE (Panther Point) */
 301        { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 302        /* SATA Controller IDE (Panther Point) */
 303        { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 304        /* SATA Controller IDE (Lynx Point) */
 305        { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 306        /* SATA Controller IDE (Lynx Point) */
 307        { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 308        /* SATA Controller IDE (Lynx Point) */
 309        { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
 310        /* SATA Controller IDE (Lynx Point) */
 311        { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 312        /* SATA Controller IDE (Lynx Point-LP) */
 313        { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 314        /* SATA Controller IDE (Lynx Point-LP) */
 315        { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 316        /* SATA Controller IDE (Lynx Point-LP) */
 317        { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 318        /* SATA Controller IDE (Lynx Point-LP) */
 319        { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 320        /* SATA Controller IDE (DH89xxCC) */
 321        { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 322        /* SATA Controller IDE (Avoton) */
 323        { 0x8086, 0x1f20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 324        /* SATA Controller IDE (Avoton) */
 325        { 0x8086, 0x1f21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 326        /* SATA Controller IDE (Avoton) */
 327        { 0x8086, 0x1f30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 328        /* SATA Controller IDE (Avoton) */
 329        { 0x8086, 0x1f31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 330        /* SATA Controller IDE (Wellsburg) */
 331        { 0x8086, 0x8d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 332        /* SATA Controller IDE (Wellsburg) */
 333        { 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
 334        /* SATA Controller IDE (Wellsburg) */
 335        { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 336        /* SATA Controller IDE (Wellsburg) */
 337        { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 338        /* SATA Controller IDE (BayTrail) */
 339        { 0x8086, 0x0F20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
 340        { 0x8086, 0x0F21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
 341        /* SATA Controller IDE (Coleto Creek) */
 342        { 0x8086, 0x23a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 343
 344        { }     /* terminate list */
 345};
 346
 347static const struct piix_map_db ich5_map_db = {
 348        .mask = 0x7,
 349        .port_enable = 0x3,
 350        .map = {
 351                /* PM   PS   SM   SS       MAP  */
 352                {  P0,  NA,  P1,  NA }, /* 000b */
 353                {  P1,  NA,  P0,  NA }, /* 001b */
 354                {  RV,  RV,  RV,  RV },
 355                {  RV,  RV,  RV,  RV },
 356                {  P0,  P1, IDE, IDE }, /* 100b */
 357                {  P1,  P0, IDE, IDE }, /* 101b */
 358                { IDE, IDE,  P0,  P1 }, /* 110b */
 359                { IDE, IDE,  P1,  P0 }, /* 111b */
 360        },
 361};
 362
 363static const struct piix_map_db ich6_map_db = {
 364        .mask = 0x3,
 365        .port_enable = 0xf,
 366        .map = {
 367                /* PM   PS   SM   SS       MAP */
 368                {  P0,  P2,  P1,  P3 }, /* 00b */
 369                { IDE, IDE,  P1,  P3 }, /* 01b */
 370                {  P0,  P2, IDE, IDE }, /* 10b */
 371                {  RV,  RV,  RV,  RV },
 372        },
 373};
 374
 375static const struct piix_map_db ich6m_map_db = {
 376        .mask = 0x3,
 377        .port_enable = 0x5,
 378
 379        /* Map 01b isn't specified in the doc but some notebooks use
 380         * it anyway.  MAP 01b have been spotted on both ICH6M and
 381         * ICH7M.
 382         */
 383        .map = {
 384                /* PM   PS   SM   SS       MAP */
 385                {  P0,  P2,  NA,  NA }, /* 00b */
 386                { IDE, IDE,  P1,  P3 }, /* 01b */
 387                {  P0,  P2, IDE, IDE }, /* 10b */
 388                {  RV,  RV,  RV,  RV },
 389        },
 390};
 391
 392static const struct piix_map_db ich8_map_db = {
 393        .mask = 0x3,
 394        .port_enable = 0xf,
 395        .map = {
 396                /* PM   PS   SM   SS       MAP */
 397                {  P0,  P2,  P1,  P3 }, /* 00b (hardwired when in AHCI) */
 398                {  RV,  RV,  RV,  RV },
 399                {  P0,  P2, IDE, IDE }, /* 10b (IDE mode) */
 400                {  RV,  RV,  RV,  RV },
 401        },
 402};
 403
 404static const struct piix_map_db ich8_2port_map_db = {
 405        .mask = 0x3,
 406        .port_enable = 0x3,
 407        .map = {
 408                /* PM   PS   SM   SS       MAP */
 409                {  P0,  NA,  P1,  NA }, /* 00b */
 410                {  RV,  RV,  RV,  RV }, /* 01b */
 411                {  RV,  RV,  RV,  RV }, /* 10b */
 412                {  RV,  RV,  RV,  RV },
 413        },
 414};
 415
 416static const struct piix_map_db ich8m_apple_map_db = {
 417        .mask = 0x3,
 418        .port_enable = 0x1,
 419        .map = {
 420                /* PM   PS   SM   SS       MAP */
 421                {  P0,  NA,  NA,  NA }, /* 00b */
 422                {  RV,  RV,  RV,  RV },
 423                {  P0,  P2, IDE, IDE }, /* 10b */
 424                {  RV,  RV,  RV,  RV },
 425        },
 426};
 427
 428static const struct piix_map_db tolapai_map_db = {
 429        .mask = 0x3,
 430        .port_enable = 0x3,
 431        .map = {
 432                /* PM   PS   SM   SS       MAP */
 433                {  P0,  NA,  P1,  NA }, /* 00b */
 434                {  RV,  RV,  RV,  RV }, /* 01b */
 435                {  RV,  RV,  RV,  RV }, /* 10b */
 436                {  RV,  RV,  RV,  RV },
 437        },
 438};
 439
 440static const struct piix_map_db *piix_map_db_table[] = {
 441        [ich5_sata]             = &ich5_map_db,
 442        [ich6_sata]             = &ich6_map_db,
 443        [ich6m_sata]            = &ich6m_map_db,
 444        [ich8_sata]             = &ich8_map_db,
 445        [ich8_2port_sata]       = &ich8_2port_map_db,
 446        [ich8m_apple_sata]      = &ich8m_apple_map_db,
 447        [tolapai_sata]          = &tolapai_map_db,
 448        [ich8_sata_snb]         = &ich8_map_db,
 449        [ich8_2port_sata_snb]   = &ich8_2port_map_db,
 450        [ich8_2port_sata_byt]   = &ich8_2port_map_db,
 451};
 452
 453static struct pci_bits piix_enable_bits[] = {
 454        { 0x41U, 1U, 0x80UL, 0x80UL },  /* port 0 */
 455        { 0x43U, 1U, 0x80UL, 0x80UL },  /* port 1 */
 456};
 457
 458MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
 459MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
 460MODULE_LICENSE("GPL");
 461MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
 462MODULE_VERSION(DRV_VERSION);
 463
 464struct ich_laptop {
 465        u16 device;
 466        u16 subvendor;
 467        u16 subdevice;
 468};
 469
 470/*
 471 *      List of laptops that use short cables rather than 80 wire
 472 */
 473
 474static const struct ich_laptop ich_laptop[] = {
 475        /* devid, subvendor, subdev */
 476        { 0x27DF, 0x0005, 0x0280 },     /* ICH7 on Acer 5602WLMi */
 477        { 0x27DF, 0x1025, 0x0102 },     /* ICH7 on Acer 5602aWLMi */
 478        { 0x27DF, 0x1025, 0x0110 },     /* ICH7 on Acer 3682WLMi */
 479        { 0x27DF, 0x1028, 0x02b0 },     /* ICH7 on unknown Dell */
 480        { 0x27DF, 0x1043, 0x1267 },     /* ICH7 on Asus W5F */
 481        { 0x27DF, 0x103C, 0x30A1 },     /* ICH7 on HP Compaq nc2400 */
 482        { 0x27DF, 0x103C, 0x361a },     /* ICH7 on unknown HP  */
 483        { 0x27DF, 0x1071, 0xD221 },     /* ICH7 on Hercules EC-900 */
 484        { 0x27DF, 0x152D, 0x0778 },     /* ICH7 on unknown Intel */
 485        { 0x24CA, 0x1025, 0x0061 },     /* ICH4 on ACER Aspire 2023WLMi */
 486        { 0x24CA, 0x1025, 0x003d },     /* ICH4 on ACER TM290 */
 487        { 0x266F, 0x1025, 0x0066 },     /* ICH6 on ACER Aspire 1694WLMi */
 488        { 0x2653, 0x1043, 0x82D8 },     /* ICH6M on Asus Eee 701 */
 489        { 0x27df, 0x104d, 0x900e },     /* ICH7 on Sony TZ-90 */
 490        /* end marker */
 491        { 0, }
 492};
 493
 494static int piix_port_start(struct ata_port *ap)
 495{
 496        if (!(ap->flags & PIIX_FLAG_PIO16))
 497                ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
 498
 499        return ata_bmdma_port_start(ap);
 500}
 501
 502/**
 503 *      ich_pata_cable_detect - Probe host controller cable detect info
 504 *      @ap: Port for which cable detect info is desired
 505 *
 506 *      Read 80c cable indicator from ATA PCI device's PCI config
 507 *      register.  This register is normally set by firmware (BIOS).
 508 *
 509 *      LOCKING:
 510 *      None (inherited from caller).
 511 */
 512
 513static int ich_pata_cable_detect(struct ata_port *ap)
 514{
 515        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 516        struct piix_host_priv *hpriv = ap->host->private_data;
 517        const struct ich_laptop *lap = &ich_laptop[0];
 518        u8 mask;
 519
 520        /* Check for specials - Acer Aspire 5602WLMi */
 521        while (lap->device) {
 522                if (lap->device == pdev->device &&
 523                    lap->subvendor == pdev->subsystem_vendor &&
 524                    lap->subdevice == pdev->subsystem_device)
 525                        return ATA_CBL_PATA40_SHORT;
 526
 527                lap++;
 528        }
 529
 530        /* check BIOS cable detect results */
 531        mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
 532        if ((hpriv->saved_iocfg & mask) == 0)
 533                return ATA_CBL_PATA40;
 534        return ATA_CBL_PATA80;
 535}
 536
 537/**
 538 *      piix_pata_prereset - prereset for PATA host controller
 539 *      @link: Target link
 540 *      @deadline: deadline jiffies for the operation
 541 *
 542 *      LOCKING:
 543 *      None (inherited from caller).
 544 */
 545static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
 546{
 547        struct ata_port *ap = link->ap;
 548        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 549
 550        if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
 551                return -ENOENT;
 552        return ata_sff_prereset(link, deadline);
 553}
 554
 555static DEFINE_SPINLOCK(piix_lock);
 556
 557static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
 558                             u8 pio)
 559{
 560        struct pci_dev *dev     = to_pci_dev(ap->host->dev);
 561        unsigned long flags;
 562        unsigned int is_slave   = (adev->devno != 0);
 563        unsigned int master_port= ap->port_no ? 0x42 : 0x40;
 564        unsigned int slave_port = 0x44;
 565        u16 master_data;
 566        u8 slave_data;
 567        u8 udma_enable;
 568        int control = 0;
 569
 570        /*
 571         *      See Intel Document 298600-004 for the timing programing rules
 572         *      for ICH controllers.
 573         */
 574
 575        static const     /* ISP  RTC */
 576        u8 timings[][2] = { { 0, 0 },
 577                            { 0, 0 },
 578                            { 1, 0 },
 579                            { 2, 1 },
 580                            { 2, 3 }, };
 581
 582        if (pio >= 2)
 583                control |= 1;   /* TIME1 enable */
 584        if (ata_pio_need_iordy(adev))
 585                control |= 2;   /* IE enable */
 586        /* Intel specifies that the PPE functionality is for disk only */
 587        if (adev->class == ATA_DEV_ATA)
 588                control |= 4;   /* PPE enable */
 589        /*
 590         * If the drive MWDMA is faster than it can do PIO then
 591         * we must force PIO into PIO0
 592         */
 593        if (adev->pio_mode < XFER_PIO_0 + pio)
 594                /* Enable DMA timing only */
 595                control |= 8;   /* PIO cycles in PIO0 */
 596
 597        spin_lock_irqsave(&piix_lock, flags);
 598
 599        /* PIO configuration clears DTE unconditionally.  It will be
 600         * programmed in set_dmamode which is guaranteed to be called
 601         * after set_piomode if any DMA mode is available.
 602         */
 603        pci_read_config_word(dev, master_port, &master_data);
 604        if (is_slave) {
 605                /* clear TIME1|IE1|PPE1|DTE1 */
 606                master_data &= 0xff0f;
 607                /* enable PPE1, IE1 and TIME1 as needed */
 608                master_data |= (control << 4);
 609                pci_read_config_byte(dev, slave_port, &slave_data);
 610                slave_data &= (ap->port_no ? 0x0f : 0xf0);
 611                /* Load the timing nibble for this slave */
 612                slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
 613                                                << (ap->port_no ? 4 : 0);
 614        } else {
 615                /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
 616                master_data &= 0xccf0;
 617                /* Enable PPE, IE and TIME as appropriate */
 618                master_data |= control;
 619                /* load ISP and RCT */
 620                master_data |=
 621                        (timings[pio][0] << 12) |
 622                        (timings[pio][1] << 8);
 623        }
 624
 625        /* Enable SITRE (separate slave timing register) */
 626        master_data |= 0x4000;
 627        pci_write_config_word(dev, master_port, master_data);
 628        if (is_slave)
 629                pci_write_config_byte(dev, slave_port, slave_data);
 630
 631        /* Ensure the UDMA bit is off - it will be turned back on if
 632           UDMA is selected */
 633
 634        if (ap->udma_mask) {
 635                pci_read_config_byte(dev, 0x48, &udma_enable);
 636                udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
 637                pci_write_config_byte(dev, 0x48, udma_enable);
 638        }
 639
 640        spin_unlock_irqrestore(&piix_lock, flags);
 641}
 642
 643/**
 644 *      piix_set_piomode - Initialize host controller PATA PIO timings
 645 *      @ap: Port whose timings we are configuring
 646 *      @adev: Drive in question
 647 *
 648 *      Set PIO mode for device, in host controller PCI config space.
 649 *
 650 *      LOCKING:
 651 *      None (inherited from caller).
 652 */
 653
 654static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
 655{
 656        piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
 657}
 658
 659/**
 660 *      do_pata_set_dmamode - Initialize host controller PATA PIO timings
 661 *      @ap: Port whose timings we are configuring
 662 *      @adev: Drive in question
 663 *      @isich: set if the chip is an ICH device
 664 *
 665 *      Set UDMA mode for device, in host controller PCI config space.
 666 *
 667 *      LOCKING:
 668 *      None (inherited from caller).
 669 */
 670
 671static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
 672{
 673        struct pci_dev *dev     = to_pci_dev(ap->host->dev);
 674        unsigned long flags;
 675        u8 speed                = adev->dma_mode;
 676        int devid               = adev->devno + 2 * ap->port_no;
 677        u8 udma_enable          = 0;
 678
 679        if (speed >= XFER_UDMA_0) {
 680                unsigned int udma = speed - XFER_UDMA_0;
 681                u16 udma_timing;
 682                u16 ideconf;
 683                int u_clock, u_speed;
 684
 685                spin_lock_irqsave(&piix_lock, flags);
 686
 687                pci_read_config_byte(dev, 0x48, &udma_enable);
 688
 689                /*
 690                 * UDMA is handled by a combination of clock switching and
 691                 * selection of dividers
 692                 *
 693                 * Handy rule: Odd modes are UDMATIMx 01, even are 02
 694                 *             except UDMA0 which is 00
 695                 */
 696                u_speed = min(2 - (udma & 1), udma);
 697                if (udma == 5)
 698                        u_clock = 0x1000;       /* 100Mhz */
 699                else if (udma > 2)
 700                        u_clock = 1;            /* 66Mhz */
 701                else
 702                        u_clock = 0;            /* 33Mhz */
 703
 704                udma_enable |= (1 << devid);
 705
 706                /* Load the CT/RP selection */
 707                pci_read_config_word(dev, 0x4A, &udma_timing);
 708                udma_timing &= ~(3 << (4 * devid));
 709                udma_timing |= u_speed << (4 * devid);
 710                pci_write_config_word(dev, 0x4A, udma_timing);
 711
 712                if (isich) {
 713                        /* Select a 33/66/100Mhz clock */
 714                        pci_read_config_word(dev, 0x54, &ideconf);
 715                        ideconf &= ~(0x1001 << devid);
 716                        ideconf |= u_clock << devid;
 717                        /* For ICH or later we should set bit 10 for better
 718                           performance (WR_PingPong_En) */
 719                        pci_write_config_word(dev, 0x54, ideconf);
 720                }
 721
 722                pci_write_config_byte(dev, 0x48, udma_enable);
 723
 724                spin_unlock_irqrestore(&piix_lock, flags);
 725        } else {
 726                /* MWDMA is driven by the PIO timings. */
 727                unsigned int mwdma = speed - XFER_MW_DMA_0;
 728                const unsigned int needed_pio[3] = {
 729                        XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
 730                };
 731                int pio = needed_pio[mwdma] - XFER_PIO_0;
 732
 733                /* XFER_PIO_0 is never used currently */
 734                piix_set_timings(ap, adev, pio);
 735        }
 736}
 737
 738/**
 739 *      piix_set_dmamode - Initialize host controller PATA DMA timings
 740 *      @ap: Port whose timings we are configuring
 741 *      @adev: um
 742 *
 743 *      Set MW/UDMA mode for device, in host controller PCI config space.
 744 *
 745 *      LOCKING:
 746 *      None (inherited from caller).
 747 */
 748
 749static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 750{
 751        do_pata_set_dmamode(ap, adev, 0);
 752}
 753
 754/**
 755 *      ich_set_dmamode - Initialize host controller PATA DMA timings
 756 *      @ap: Port whose timings we are configuring
 757 *      @adev: um
 758 *
 759 *      Set MW/UDMA mode for device, in host controller PCI config space.
 760 *
 761 *      LOCKING:
 762 *      None (inherited from caller).
 763 */
 764
 765static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 766{
 767        do_pata_set_dmamode(ap, adev, 1);
 768}
 769
 770/*
 771 * Serial ATA Index/Data Pair Superset Registers access
 772 *
 773 * Beginning from ICH8, there's a sane way to access SCRs using index
 774 * and data register pair located at BAR5 which means that we have
 775 * separate SCRs for master and slave.  This is handled using libata
 776 * slave_link facility.
 777 */
 778static const int piix_sidx_map[] = {
 779        [SCR_STATUS]    = 0,
 780        [SCR_ERROR]     = 2,
 781        [SCR_CONTROL]   = 1,
 782};
 783
 784static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
 785{
 786        struct ata_port *ap = link->ap;
 787        struct piix_host_priv *hpriv = ap->host->private_data;
 788
 789        iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
 790                  hpriv->sidpr + PIIX_SIDPR_IDX);
 791}
 792
 793static int piix_sidpr_scr_read(struct ata_link *link,
 794                               unsigned int reg, u32 *val)
 795{
 796        struct piix_host_priv *hpriv = link->ap->host->private_data;
 797
 798        if (reg >= ARRAY_SIZE(piix_sidx_map))
 799                return -EINVAL;
 800
 801        piix_sidpr_sel(link, reg);
 802        *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
 803        return 0;
 804}
 805
 806static int piix_sidpr_scr_write(struct ata_link *link,
 807                                unsigned int reg, u32 val)
 808{
 809        struct piix_host_priv *hpriv = link->ap->host->private_data;
 810
 811        if (reg >= ARRAY_SIZE(piix_sidx_map))
 812                return -EINVAL;
 813
 814        piix_sidpr_sel(link, reg);
 815        iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
 816        return 0;
 817}
 818
 819static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
 820                              unsigned hints)
 821{
 822        return sata_link_scr_lpm(link, policy, false);
 823}
 824
 825static bool piix_irq_check(struct ata_port *ap)
 826{
 827        if (unlikely(!ap->ioaddr.bmdma_addr))
 828                return false;
 829
 830        return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
 831}
 832
 833#ifdef CONFIG_PM
 834static int piix_broken_suspend(void)
 835{
 836        static const struct dmi_system_id sysids[] = {
 837                {
 838                        .ident = "TECRA M3",
 839                        .matches = {
 840                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 841                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
 842                        },
 843                },
 844                {
 845                        .ident = "TECRA M3",
 846                        .matches = {
 847                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 848                                DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
 849                        },
 850                },
 851                {
 852                        .ident = "TECRA M4",
 853                        .matches = {
 854                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 855                                DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
 856                        },
 857                },
 858                {
 859                        .ident = "TECRA M4",
 860                        .matches = {
 861                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 862                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
 863                        },
 864                },
 865                {
 866                        .ident = "TECRA M5",
 867                        .matches = {
 868                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 869                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
 870                        },
 871                },
 872                {
 873                        .ident = "TECRA M6",
 874                        .matches = {
 875                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 876                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
 877                        },
 878                },
 879                {
 880                        .ident = "TECRA M7",
 881                        .matches = {
 882                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 883                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
 884                        },
 885                },
 886                {
 887                        .ident = "TECRA A8",
 888                        .matches = {
 889                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 890                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
 891                        },
 892                },
 893                {
 894                        .ident = "Satellite R20",
 895                        .matches = {
 896                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 897                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
 898                        },
 899                },
 900                {
 901                        .ident = "Satellite R25",
 902                        .matches = {
 903                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 904                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
 905                        },
 906                },
 907                {
 908                        .ident = "Satellite U200",
 909                        .matches = {
 910                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 911                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
 912                        },
 913                },
 914                {
 915                        .ident = "Satellite U200",
 916                        .matches = {
 917                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 918                                DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
 919                        },
 920                },
 921                {
 922                        .ident = "Satellite Pro U200",
 923                        .matches = {
 924                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 925                                DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
 926                        },
 927                },
 928                {
 929                        .ident = "Satellite U205",
 930                        .matches = {
 931                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 932                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
 933                        },
 934                },
 935                {
 936                        .ident = "SATELLITE U205",
 937                        .matches = {
 938                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 939                                DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
 940                        },
 941                },
 942                {
 943                        .ident = "Satellite Pro A120",
 944                        .matches = {
 945                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 946                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"),
 947                        },
 948                },
 949                {
 950                        .ident = "Portege M500",
 951                        .matches = {
 952                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 953                                DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
 954                        },
 955                },
 956                {
 957                        .ident = "VGN-BX297XP",
 958                        .matches = {
 959                                DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
 960                                DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
 961                        },
 962                },
 963
 964                { }     /* terminate list */
 965        };
 966        static const char *oemstrs[] = {
 967                "Tecra M3,",
 968        };
 969        int i;
 970
 971        if (dmi_check_system(sysids))
 972                return 1;
 973
 974        for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
 975                if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
 976                        return 1;
 977
 978        /* TECRA M4 sometimes forgets its identify and reports bogus
 979         * DMI information.  As the bogus information is a bit
 980         * generic, match as many entries as possible.  This manual
 981         * matching is necessary because dmi_system_id.matches is
 982         * limited to four entries.
 983         */
 984        if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
 985            dmi_match(DMI_PRODUCT_NAME, "000000") &&
 986            dmi_match(DMI_PRODUCT_VERSION, "000000") &&
 987            dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
 988            dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
 989            dmi_match(DMI_BOARD_NAME, "Portable PC") &&
 990            dmi_match(DMI_BOARD_VERSION, "Version A0"))
 991                return 1;
 992
 993        return 0;
 994}
 995
 996static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 997{
 998        struct ata_host *host = pci_get_drvdata(pdev);
 999        unsigned long flags;
1000        int rc = 0;
1001
1002        rc = ata_host_suspend(host, mesg);
1003        if (rc)
1004                return rc;
1005
1006        /* Some braindamaged ACPI suspend implementations expect the
1007         * controller to be awake on entry; otherwise, it burns cpu
1008         * cycles and power trying to do something to the sleeping
1009         * beauty.
1010         */
1011        if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1012                pci_save_state(pdev);
1013
1014                /* mark its power state as "unknown", since we don't
1015                 * know if e.g. the BIOS will change its device state
1016                 * when we suspend.
1017                 */
1018                if (pdev->current_state == PCI_D0)
1019                        pdev->current_state = PCI_UNKNOWN;
1020
1021                /* tell resume that it's waking up from broken suspend */
1022                spin_lock_irqsave(&host->lock, flags);
1023                host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1024                spin_unlock_irqrestore(&host->lock, flags);
1025        } else
1026                ata_pci_device_do_suspend(pdev, mesg);
1027
1028        return 0;
1029}
1030
1031static int piix_pci_device_resume(struct pci_dev *pdev)
1032{
1033        struct ata_host *host = pci_get_drvdata(pdev);
1034        unsigned long flags;
1035        int rc;
1036
1037        if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1038                spin_lock_irqsave(&host->lock, flags);
1039                host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1040                spin_unlock_irqrestore(&host->lock, flags);
1041
1042                pci_set_power_state(pdev, PCI_D0);
1043                pci_restore_state(pdev);
1044
1045                /* PCI device wasn't disabled during suspend.  Use
1046                 * pci_reenable_device() to avoid affecting the enable
1047                 * count.
1048                 */
1049                rc = pci_reenable_device(pdev);
1050                if (rc)
1051                        dev_err(&pdev->dev,
1052                                "failed to enable device after resume (%d)\n",
1053                                rc);
1054        } else
1055                rc = ata_pci_device_do_resume(pdev);
1056
1057        if (rc == 0)
1058                ata_host_resume(host);
1059
1060        return rc;
1061}
1062#endif
1063
1064static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1065{
1066        return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1067}
1068
1069static struct scsi_host_template piix_sht = {
1070        ATA_BMDMA_SHT(DRV_NAME),
1071};
1072
1073static struct ata_port_operations piix_sata_ops = {
1074        .inherits               = &ata_bmdma32_port_ops,
1075        .sff_irq_check          = piix_irq_check,
1076        .port_start             = piix_port_start,
1077};
1078
1079static struct ata_port_operations piix_pata_ops = {
1080        .inherits               = &piix_sata_ops,
1081        .cable_detect           = ata_cable_40wire,
1082        .set_piomode            = piix_set_piomode,
1083        .set_dmamode            = piix_set_dmamode,
1084        .prereset               = piix_pata_prereset,
1085};
1086
1087static struct ata_port_operations piix_vmw_ops = {
1088        .inherits               = &piix_pata_ops,
1089        .bmdma_status           = piix_vmw_bmdma_status,
1090};
1091
1092static struct ata_port_operations ich_pata_ops = {
1093        .inherits               = &piix_pata_ops,
1094        .cable_detect           = ich_pata_cable_detect,
1095        .set_dmamode            = ich_set_dmamode,
1096};
1097
1098static struct device_attribute *piix_sidpr_shost_attrs[] = {
1099        &dev_attr_link_power_management_policy,
1100        NULL
1101};
1102
1103static struct scsi_host_template piix_sidpr_sht = {
1104        ATA_BMDMA_SHT(DRV_NAME),
1105        .shost_attrs            = piix_sidpr_shost_attrs,
1106};
1107
1108static struct ata_port_operations piix_sidpr_sata_ops = {
1109        .inherits               = &piix_sata_ops,
1110        .hardreset              = sata_std_hardreset,
1111        .scr_read               = piix_sidpr_scr_read,
1112        .scr_write              = piix_sidpr_scr_write,
1113        .set_lpm                = piix_sidpr_set_lpm,
1114};
1115
1116static struct ata_port_info piix_port_info[] = {
1117        [piix_pata_mwdma] =     /* PIIX3 MWDMA only */
1118        {
1119                .flags          = PIIX_PATA_FLAGS,
1120                .pio_mask       = ATA_PIO4,
1121                .mwdma_mask     = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1122                .port_ops       = &piix_pata_ops,
1123        },
1124
1125        [piix_pata_33] =        /* PIIX4 at 33MHz */
1126        {
1127                .flags          = PIIX_PATA_FLAGS,
1128                .pio_mask       = ATA_PIO4,
1129                .mwdma_mask     = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1130                .udma_mask      = ATA_UDMA2,
1131                .port_ops       = &piix_pata_ops,
1132        },
1133
1134        [ich_pata_33] =         /* ICH0 - ICH at 33Mhz*/
1135        {
1136                .flags          = PIIX_PATA_FLAGS,
1137                .pio_mask       = ATA_PIO4,
1138                .mwdma_mask     = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok  */
1139                .udma_mask      = ATA_UDMA2,
1140                .port_ops       = &ich_pata_ops,
1141        },
1142
1143        [ich_pata_66] =         /* ICH controllers up to 66MHz */
1144        {
1145                .flags          = PIIX_PATA_FLAGS,
1146                .pio_mask       = ATA_PIO4,
1147                .mwdma_mask     = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
1148                .udma_mask      = ATA_UDMA4,
1149                .port_ops       = &ich_pata_ops,
1150        },
1151
1152        [ich_pata_100] =
1153        {
1154                .flags          = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1155                .pio_mask       = ATA_PIO4,
1156                .mwdma_mask     = ATA_MWDMA12_ONLY,
1157                .udma_mask      = ATA_UDMA5,
1158                .port_ops       = &ich_pata_ops,
1159        },
1160
1161        [ich_pata_100_nomwdma1] =
1162        {
1163                .flags          = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1164                .pio_mask       = ATA_PIO4,
1165                .mwdma_mask     = ATA_MWDMA2_ONLY,
1166                .udma_mask      = ATA_UDMA5,
1167                .port_ops       = &ich_pata_ops,
1168        },
1169
1170        [ich5_sata] =
1171        {
1172                .flags          = PIIX_SATA_FLAGS,
1173                .pio_mask       = ATA_PIO4,
1174                .mwdma_mask     = ATA_MWDMA2,
1175                .udma_mask      = ATA_UDMA6,
1176                .port_ops       = &piix_sata_ops,
1177        },
1178
1179        [ich6_sata] =
1180        {
1181                .flags          = PIIX_SATA_FLAGS,
1182                .pio_mask       = ATA_PIO4,
1183                .mwdma_mask     = ATA_MWDMA2,
1184                .udma_mask      = ATA_UDMA6,
1185                .port_ops       = &piix_sata_ops,
1186        },
1187
1188        [ich6m_sata] =
1189        {
1190                .flags          = PIIX_SATA_FLAGS,
1191                .pio_mask       = ATA_PIO4,
1192                .mwdma_mask     = ATA_MWDMA2,
1193                .udma_mask      = ATA_UDMA6,
1194                .port_ops       = &piix_sata_ops,
1195        },
1196
1197        [ich8_sata] =
1198        {
1199                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1200                .pio_mask       = ATA_PIO4,
1201                .mwdma_mask     = ATA_MWDMA2,
1202                .udma_mask      = ATA_UDMA6,
1203                .port_ops       = &piix_sata_ops,
1204        },
1205
1206        [ich8_2port_sata] =
1207        {
1208                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1209                .pio_mask       = ATA_PIO4,
1210                .mwdma_mask     = ATA_MWDMA2,
1211                .udma_mask      = ATA_UDMA6,
1212                .port_ops       = &piix_sata_ops,
1213        },
1214
1215        [tolapai_sata] =
1216        {
1217                .flags          = PIIX_SATA_FLAGS,
1218                .pio_mask       = ATA_PIO4,
1219                .mwdma_mask     = ATA_MWDMA2,
1220                .udma_mask      = ATA_UDMA6,
1221                .port_ops       = &piix_sata_ops,
1222        },
1223
1224        [ich8m_apple_sata] =
1225        {
1226                .flags          = PIIX_SATA_FLAGS,
1227                .pio_mask       = ATA_PIO4,
1228                .mwdma_mask     = ATA_MWDMA2,
1229                .udma_mask      = ATA_UDMA6,
1230                .port_ops       = &piix_sata_ops,
1231        },
1232
1233        [piix_pata_vmw] =
1234        {
1235                .flags          = PIIX_PATA_FLAGS,
1236                .pio_mask       = ATA_PIO4,
1237                .mwdma_mask     = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1238                .udma_mask      = ATA_UDMA2,
1239                .port_ops       = &piix_vmw_ops,
1240        },
1241
1242        /*
1243         * some Sandybridge chipsets have broken 32 mode up to now,
1244         * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
1245         */
1246        [ich8_sata_snb] =
1247        {
1248                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1249                .pio_mask       = ATA_PIO4,
1250                .mwdma_mask     = ATA_MWDMA2,
1251                .udma_mask      = ATA_UDMA6,
1252                .port_ops       = &piix_sata_ops,
1253        },
1254
1255        [ich8_2port_sata_snb] =
1256        {
1257                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR
1258                                        | PIIX_FLAG_PIO16,
1259                .pio_mask       = ATA_PIO4,
1260                .mwdma_mask     = ATA_MWDMA2,
1261                .udma_mask      = ATA_UDMA6,
1262                .port_ops       = &piix_sata_ops,
1263        },
1264
1265        [ich8_2port_sata_byt] =
1266        {
1267                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1268                .pio_mask       = ATA_PIO4,
1269                .mwdma_mask     = ATA_MWDMA2,
1270                .udma_mask      = ATA_UDMA6,
1271                .port_ops       = &piix_sata_ops,
1272        },
1273
1274};
1275
1276#define AHCI_PCI_BAR 5
1277#define AHCI_GLOBAL_CTL 0x04
1278#define AHCI_ENABLE (1 << 31)
1279static int piix_disable_ahci(struct pci_dev *pdev)
1280{
1281        void __iomem *mmio;
1282        u32 tmp;
1283        int rc = 0;
1284
1285        /* BUG: pci_enable_device has not yet been called.  This
1286         * works because this device is usually set up by BIOS.
1287         */
1288
1289        if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1290            !pci_resource_len(pdev, AHCI_PCI_BAR))
1291                return 0;
1292
1293        mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1294        if (!mmio)
1295                return -ENOMEM;
1296
1297        tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1298        if (tmp & AHCI_ENABLE) {
1299                tmp &= ~AHCI_ENABLE;
1300                iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1301
1302                tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1303                if (tmp & AHCI_ENABLE)
1304                        rc = -EIO;
1305        }
1306
1307        pci_iounmap(pdev, mmio);
1308        return rc;
1309}
1310
1311/**
1312 *      piix_check_450nx_errata -       Check for problem 450NX setup
1313 *      @ata_dev: the PCI device to check
1314 *
1315 *      Check for the present of 450NX errata #19 and errata #25. If
1316 *      they are found return an error code so we can turn off DMA
1317 */
1318
1319static int piix_check_450nx_errata(struct pci_dev *ata_dev)
1320{
1321        struct pci_dev *pdev = NULL;
1322        u16 cfg;
1323        int no_piix_dma = 0;
1324
1325        while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1326                /* Look for 450NX PXB. Check for problem configurations
1327                   A PCI quirk checks bit 6 already */
1328                pci_read_config_word(pdev, 0x41, &cfg);
1329                /* Only on the original revision: IDE DMA can hang */
1330                if (pdev->revision == 0x00)
1331                        no_piix_dma = 1;
1332                /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1333                else if (cfg & (1<<14) && pdev->revision < 5)
1334                        no_piix_dma = 2;
1335        }
1336        if (no_piix_dma)
1337                dev_warn(&ata_dev->dev,
1338                         "450NX errata present, disabling IDE DMA%s\n",
1339                         no_piix_dma == 2 ? " - a BIOS update may resolve this"
1340                         : "");
1341
1342        return no_piix_dma;
1343}
1344
1345static void piix_init_pcs(struct ata_host *host,
1346                          const struct piix_map_db *map_db)
1347{
1348        struct pci_dev *pdev = to_pci_dev(host->dev);
1349        u16 pcs, new_pcs;
1350
1351        pci_read_config_word(pdev, ICH5_PCS, &pcs);
1352
1353        new_pcs = pcs | map_db->port_enable;
1354
1355        if (new_pcs != pcs) {
1356                DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1357                pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1358                msleep(150);
1359        }
1360}
1361
1362static const int *piix_init_sata_map(struct pci_dev *pdev,
1363                                     struct ata_port_info *pinfo,
1364                                     const struct piix_map_db *map_db)
1365{
1366        const int *map;
1367        int i, invalid_map = 0;
1368        u8 map_value;
1369
1370        pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1371
1372        map = map_db->map[map_value & map_db->mask];
1373
1374        dev_info(&pdev->dev, "MAP [");
1375        for (i = 0; i < 4; i++) {
1376                switch (map[i]) {
1377                case RV:
1378                        invalid_map = 1;
1379                        pr_cont(" XX");
1380                        break;
1381
1382                case NA:
1383                        pr_cont(" --");
1384                        break;
1385
1386                case IDE:
1387                        WARN_ON((i & 1) || map[i + 1] != IDE);
1388                        pinfo[i / 2] = piix_port_info[ich_pata_100];
1389                        i++;
1390                        pr_cont(" IDE IDE");
1391                        break;
1392
1393                default:
1394                        pr_cont(" P%d", map[i]);
1395                        if (i & 1)
1396                                pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1397                        break;
1398                }
1399        }
1400        pr_cont(" ]\n");
1401
1402        if (invalid_map)
1403                dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1404
1405        return map;
1406}
1407
1408static bool piix_no_sidpr(struct ata_host *host)
1409{
1410        struct pci_dev *pdev = to_pci_dev(host->dev);
1411
1412        /*
1413         * Samsung DB-P70 only has three ATA ports exposed and
1414         * curiously the unconnected first port reports link online
1415         * while not responding to SRST protocol causing excessive
1416         * detection delay.
1417         *
1418         * Unfortunately, the system doesn't carry enough DMI
1419         * information to identify the machine but does have subsystem
1420         * vendor and device set.  As it's unclear whether the
1421         * subsystem vendor/device is used only for this specific
1422         * board, the port can't be disabled solely with the
1423         * information; however, turning off SIDPR access works around
1424         * the problem.  Turn it off.
1425         *
1426         * This problem is reported in bnc#441240.
1427         *
1428         * https://bugzilla.novell.com/show_bug.cgi?id=441420
1429         */
1430        if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1431            pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1432            pdev->subsystem_device == 0xb049) {
1433                dev_warn(host->dev,
1434                         "Samsung DB-P70 detected, disabling SIDPR\n");
1435                return true;
1436        }
1437
1438        return false;
1439}
1440
1441static int piix_init_sidpr(struct ata_host *host)
1442{
1443        struct pci_dev *pdev = to_pci_dev(host->dev);
1444        struct piix_host_priv *hpriv = host->private_data;
1445        struct ata_link *link0 = &host->ports[0]->link;
1446        u32 scontrol;
1447        int i, rc;
1448
1449        /* check for availability */
1450        for (i = 0; i < 4; i++)
1451                if (hpriv->map[i] == IDE)
1452                        return 0;
1453
1454        /* is it blacklisted? */
1455        if (piix_no_sidpr(host))
1456                return 0;
1457
1458        if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1459                return 0;
1460
1461        if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1462            pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1463                return 0;
1464
1465        if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1466                return 0;
1467
1468        hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1469
1470        /* SCR access via SIDPR doesn't work on some configurations.
1471         * Give it a test drive by inhibiting power save modes which
1472         * we'll do anyway.
1473         */
1474        piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1475
1476        /* if IPM is already 3, SCR access is probably working.  Don't
1477         * un-inhibit power save modes as BIOS might have inhibited
1478         * them for a reason.
1479         */
1480        if ((scontrol & 0xf00) != 0x300) {
1481                scontrol |= 0x300;
1482                piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1483                piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1484
1485                if ((scontrol & 0xf00) != 0x300) {
1486                        dev_info(host->dev,
1487                                 "SCR access via SIDPR is available but doesn't work\n");
1488                        return 0;
1489                }
1490        }
1491
1492        /* okay, SCRs available, set ops and ask libata for slave_link */
1493        for (i = 0; i < 2; i++) {
1494                struct ata_port *ap = host->ports[i];
1495
1496                ap->ops = &piix_sidpr_sata_ops;
1497
1498                if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1499                        rc = ata_slave_link_init(ap);
1500                        if (rc)
1501                                return rc;
1502                }
1503        }
1504
1505        return 0;
1506}
1507
1508static void piix_iocfg_bit18_quirk(struct ata_host *host)
1509{
1510        static const struct dmi_system_id sysids[] = {
1511                {
1512                        /* Clevo M570U sets IOCFG bit 18 if the cdrom
1513                         * isn't used to boot the system which
1514                         * disables the channel.
1515                         */
1516                        .ident = "M570U",
1517                        .matches = {
1518                                DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1519                                DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1520                        },
1521                },
1522
1523                { }     /* terminate list */
1524        };
1525        struct pci_dev *pdev = to_pci_dev(host->dev);
1526        struct piix_host_priv *hpriv = host->private_data;
1527
1528        if (!dmi_check_system(sysids))
1529                return;
1530
1531        /* The datasheet says that bit 18 is NOOP but certain systems
1532         * seem to use it to disable a channel.  Clear the bit on the
1533         * affected systems.
1534         */
1535        if (hpriv->saved_iocfg & (1 << 18)) {
1536                dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1537                pci_write_config_dword(pdev, PIIX_IOCFG,
1538                                       hpriv->saved_iocfg & ~(1 << 18));
1539        }
1540}
1541
1542static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1543{
1544        static const struct dmi_system_id broken_systems[] = {
1545                {
1546                        .ident = "HP Compaq 2510p",
1547                        .matches = {
1548                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1549                                DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1550                        },
1551                        /* PCI slot number of the controller */
1552                        .driver_data = (void *)0x1FUL,
1553                },
1554                {
1555                        .ident = "HP Compaq nc6000",
1556                        .matches = {
1557                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1558                                DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1559                        },
1560                        /* PCI slot number of the controller */
1561                        .driver_data = (void *)0x1FUL,
1562                },
1563
1564                { }     /* terminate list */
1565        };
1566        const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1567
1568        if (dmi) {
1569                unsigned long slot = (unsigned long)dmi->driver_data;
1570                /* apply the quirk only to on-board controllers */
1571                return slot == PCI_SLOT(pdev->devfn);
1572        }
1573
1574        return false;
1575}
1576
1577static int prefer_ms_hyperv = 1;
1578module_param(prefer_ms_hyperv, int, 0);
1579MODULE_PARM_DESC(prefer_ms_hyperv,
1580        "Prefer Hyper-V paravirtualization drivers instead of ATA, "
1581        "0 - Use ATA drivers, "
1582        "1 (Default) - Use the paravirtualization drivers.");
1583
1584static void piix_ignore_devices_quirk(struct ata_host *host)
1585{
1586#if IS_ENABLED(CONFIG_HYPERV_STORAGE)
1587        static const struct dmi_system_id ignore_hyperv[] = {
1588                {
1589                        /* On Hyper-V hypervisors the disks are exposed on
1590                         * both the emulated SATA controller and on the
1591                         * paravirtualised drivers.  The CD/DVD devices
1592                         * are only exposed on the emulated controller.
1593                         * Request we ignore ATA devices on this host.
1594                         */
1595                        .ident = "Hyper-V Virtual Machine",
1596                        .matches = {
1597                                DMI_MATCH(DMI_SYS_VENDOR,
1598                                                "Microsoft Corporation"),
1599                                DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1600                        },
1601                },
1602                { }     /* terminate list */
1603        };
1604        static const struct dmi_system_id allow_virtual_pc[] = {
1605                {
1606                        /* In MS Virtual PC guests the DMI ident is nearly
1607                         * identical to a Hyper-V guest. One difference is the
1608                         * product version which is used here to identify
1609                         * a Virtual PC guest. This entry allows ata_piix to
1610                         * drive the emulated hardware.
1611                         */
1612                        .ident = "MS Virtual PC 2007",
1613                        .matches = {
1614                                DMI_MATCH(DMI_SYS_VENDOR,
1615                                                "Microsoft Corporation"),
1616                                DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1617                                DMI_MATCH(DMI_PRODUCT_VERSION, "VS2005R2"),
1618                        },
1619                },
1620                { }     /* terminate list */
1621        };
1622        const struct dmi_system_id *ignore = dmi_first_match(ignore_hyperv);
1623        const struct dmi_system_id *allow = dmi_first_match(allow_virtual_pc);
1624
1625        if (ignore && !allow && prefer_ms_hyperv) {
1626                host->flags |= ATA_HOST_IGNORE_ATA;
1627                dev_info(host->dev, "%s detected, ATA device ignore set\n",
1628                        ignore->ident);
1629        }
1630#endif
1631}
1632
1633/**
1634 *      piix_init_one - Register PIIX ATA PCI device with kernel services
1635 *      @pdev: PCI device to register
1636 *      @ent: Entry in piix_pci_tbl matching with @pdev
1637 *
1638 *      Called from kernel PCI layer.  We probe for combined mode (sigh),
1639 *      and then hand over control to libata, for it to do the rest.
1640 *
1641 *      LOCKING:
1642 *      Inherited from PCI layer (may sleep).
1643 *
1644 *      RETURNS:
1645 *      Zero on success, or -ERRNO value.
1646 */
1647
1648static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1649{
1650        struct device *dev = &pdev->dev;
1651        struct ata_port_info port_info[2];
1652        const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1653        struct scsi_host_template *sht = &piix_sht;
1654        unsigned long port_flags;
1655        struct ata_host *host;
1656        struct piix_host_priv *hpriv;
1657        int rc;
1658
1659        ata_print_version_once(&pdev->dev, DRV_VERSION);
1660
1661        /* no hotplugging support for later devices (FIXME) */
1662        if (!in_module_init && ent->driver_data >= ich5_sata)
1663                return -ENODEV;
1664
1665        if (piix_broken_system_poweroff(pdev)) {
1666                piix_port_info[ent->driver_data].flags |=
1667                                ATA_FLAG_NO_POWEROFF_SPINDOWN |
1668                                        ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1669                dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1670                                "on poweroff and hibernation\n");
1671        }
1672
1673        port_info[0] = piix_port_info[ent->driver_data];
1674        port_info[1] = piix_port_info[ent->driver_data];
1675
1676        port_flags = port_info[0].flags;
1677
1678        /* enable device and prepare host */
1679        rc = pcim_enable_device(pdev);
1680        if (rc)
1681                return rc;
1682
1683        hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1684        if (!hpriv)
1685                return -ENOMEM;
1686
1687        /* Save IOCFG, this will be used for cable detection, quirk
1688         * detection and restoration on detach.  This is necessary
1689         * because some ACPI implementations mess up cable related
1690         * bits on _STM.  Reported on kernel bz#11879.
1691         */
1692        pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1693
1694        /* ICH6R may be driven by either ata_piix or ahci driver
1695         * regardless of BIOS configuration.  Make sure AHCI mode is
1696         * off.
1697         */
1698        if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1699                rc = piix_disable_ahci(pdev);
1700                if (rc)
1701                        return rc;
1702        }
1703
1704        /* SATA map init can change port_info, do it before prepping host */
1705        if (port_flags & ATA_FLAG_SATA)
1706                hpriv->map = piix_init_sata_map(pdev, port_info,
1707                                        piix_map_db_table[ent->driver_data]);
1708
1709        rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1710        if (rc)
1711                return rc;
1712        host->private_data = hpriv;
1713
1714        /* initialize controller */
1715        if (port_flags & ATA_FLAG_SATA) {
1716                piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1717                rc = piix_init_sidpr(host);
1718                if (rc)
1719                        return rc;
1720                if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1721                        sht = &piix_sidpr_sht;
1722        }
1723
1724        /* apply IOCFG bit18 quirk */
1725        piix_iocfg_bit18_quirk(host);
1726
1727        /* On ICH5, some BIOSen disable the interrupt using the
1728         * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1729         * On ICH6, this bit has the same effect, but only when
1730         * MSI is disabled (and it is disabled, as we don't use
1731         * message-signalled interrupts currently).
1732         */
1733        if (port_flags & PIIX_FLAG_CHECKINTR)
1734                pci_intx(pdev, 1);
1735
1736        if (piix_check_450nx_errata(pdev)) {
1737                /* This writes into the master table but it does not
1738                   really matter for this errata as we will apply it to
1739                   all the PIIX devices on the board */
1740                host->ports[0]->mwdma_mask = 0;
1741                host->ports[0]->udma_mask = 0;
1742                host->ports[1]->mwdma_mask = 0;
1743                host->ports[1]->udma_mask = 0;
1744        }
1745        host->flags |= ATA_HOST_PARALLEL_SCAN;
1746
1747        /* Allow hosts to specify device types to ignore when scanning. */
1748        piix_ignore_devices_quirk(host);
1749
1750        pci_set_master(pdev);
1751        return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
1752}
1753
1754static void piix_remove_one(struct pci_dev *pdev)
1755{
1756        struct ata_host *host = pci_get_drvdata(pdev);
1757        struct piix_host_priv *hpriv = host->private_data;
1758
1759        pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1760
1761        ata_pci_remove_one(pdev);
1762}
1763
1764static struct pci_driver piix_pci_driver = {
1765        .name                   = DRV_NAME,
1766        .id_table               = piix_pci_tbl,
1767        .probe                  = piix_init_one,
1768        .remove                 = piix_remove_one,
1769#ifdef CONFIG_PM
1770        .suspend                = piix_pci_device_suspend,
1771        .resume                 = piix_pci_device_resume,
1772#endif
1773};
1774
1775static int __init piix_init(void)
1776{
1777        int rc;
1778
1779        DPRINTK("pci_register_driver\n");
1780        rc = pci_register_driver(&piix_pci_driver);
1781        if (rc)
1782                return rc;
1783
1784        in_module_init = 0;
1785
1786        DPRINTK("done\n");
1787        return 0;
1788}
1789
1790static void __exit piix_exit(void)
1791{
1792        pci_unregister_driver(&piix_pci_driver);
1793}
1794
1795module_init(piix_init);
1796module_exit(piix_exit);
1797
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