linux/Documentation/pinctrl.txt
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   1PINCTRL (PIN CONTROL) subsystem
   2This document outlines the pin control subsystem in Linux
   3
   4This subsystem deals with:
   5
   6- Enumerating and naming controllable pins
   7
   8- Multiplexing of pins, pads, fingers (etc) see below for details
   9
  10- Configuration of pins, pads, fingers (etc), such as software-controlled
  11  biasing and driving mode specific pins, such as pull-up/down, open drain,
  12  load capacitance etc.
  13
  14Top-level interface
  15===================
  16
  17Definition of PIN CONTROLLER:
  18
  19- A pin controller is a piece of hardware, usually a set of registers, that
  20  can control PINs. It may be able to multiplex, bias, set load capacitance,
  21  set drive strength etc for individual pins or groups of pins.
  22
  23Definition of PIN:
  24
  25- PINS are equal to pads, fingers, balls or whatever packaging input or
  26  output line you want to control and these are denoted by unsigned integers
  27  in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
  28  there may be several such number spaces in a system. This pin space may
  29  be sparse - i.e. there may be gaps in the space with numbers where no
  30  pin exists.
  31
  32When a PIN CONTROLLER is instantiated, it will register a descriptor to the
  33pin control framework, and this descriptor contains an array of pin descriptors
  34describing the pins handled by this specific pin controller.
  35
  36Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
  37
  38        A   B   C   D   E   F   G   H
  39
  40   8    o   o   o   o   o   o   o   o
  41
  42   7    o   o   o   o   o   o   o   o
  43
  44   6    o   o   o   o   o   o   o   o
  45
  46   5    o   o   o   o   o   o   o   o
  47
  48   4    o   o   o   o   o   o   o   o
  49
  50   3    o   o   o   o   o   o   o   o
  51
  52   2    o   o   o   o   o   o   o   o
  53
  54   1    o   o   o   o   o   o   o   o
  55
  56To register a pin controller and name all the pins on this package we can do
  57this in our driver:
  58
  59#include <linux/pinctrl/pinctrl.h>
  60
  61const struct pinctrl_pin_desc foo_pins[] = {
  62      PINCTRL_PIN(0, "A8"),
  63      PINCTRL_PIN(1, "B8"),
  64      PINCTRL_PIN(2, "C8"),
  65      ...
  66      PINCTRL_PIN(61, "F1"),
  67      PINCTRL_PIN(62, "G1"),
  68      PINCTRL_PIN(63, "H1"),
  69};
  70
  71static struct pinctrl_desc foo_desc = {
  72        .name = "foo",
  73        .pins = foo_pins,
  74        .npins = ARRAY_SIZE(foo_pins),
  75        .maxpin = 63,
  76        .owner = THIS_MODULE,
  77};
  78
  79int __init foo_probe(void)
  80{
  81        struct pinctrl_dev *pctl;
  82
  83        pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
  84        if (!pctl)
  85                pr_err("could not register foo pin driver\n");
  86}
  87
  88To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
  89selected drivers, you need to select them from your machine's Kconfig entry,
  90since these are so tightly integrated with the machines they are used on.
  91See for example arch/arm/mach-u300/Kconfig for an example.
  92
  93Pins usually have fancier names than this. You can find these in the dataheet
  94for your chip. Notice that the core pinctrl.h file provides a fancy macro
  95called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
  96the pins from 0 in the upper left corner to 63 in the lower right corner.
  97This enumeration was arbitrarily chosen, in practice you need to think
  98through your numbering system so that it matches the layout of registers
  99and such things in your driver, or the code may become complicated. You must
 100also consider matching of offsets to the GPIO ranges that may be handled by
 101the pin controller.
 102
 103For a padring with 467 pads, as opposed to actual pins, I used an enumeration
 104like this, walking around the edge of the chip, which seems to be industry
 105standard too (all these pads had names, too):
 106
 107
 108     0 ..... 104
 109   466        105
 110     .        .
 111     .        .
 112   358        224
 113    357 .... 225
 114
 115
 116Pin groups
 117==========
 118
 119Many controllers need to deal with groups of pins, so the pin controller
 120subsystem has a mechanism for enumerating groups of pins and retrieving the
 121actual enumerated pins that are part of a certain group.
 122
 123For example, say that we have a group of pins dealing with an SPI interface
 124on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
 125on { 24, 25 }.
 126
 127These two groups are presented to the pin control subsystem by implementing
 128some generic pinctrl_ops like this:
 129
 130#include <linux/pinctrl/pinctrl.h>
 131
 132struct foo_group {
 133        const char *name;
 134        const unsigned int *pins;
 135        const unsigned num_pins;
 136};
 137
 138static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
 139static const unsigned int i2c0_pins[] = { 24, 25 };
 140
 141static const struct foo_group foo_groups[] = {
 142        {
 143                .name = "spi0_grp",
 144                .pins = spi0_pins,
 145                .num_pins = ARRAY_SIZE(spi0_pins),
 146        },
 147        {
 148                .name = "i2c0_grp",
 149                .pins = i2c0_pins,
 150                .num_pins = ARRAY_SIZE(i2c0_pins),
 151        },
 152};
 153
 154
 155static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 156{
 157        return ARRAY_SIZE(foo_groups);
 158}
 159
 160static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
 161                                       unsigned selector)
 162{
 163        return foo_groups[selector].name;
 164}
 165
 166static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 167                               unsigned ** const pins,
 168                               unsigned * const num_pins)
 169{
 170        *pins = (unsigned *) foo_groups[selector].pins;
 171        *num_pins = foo_groups[selector].num_pins;
 172        return 0;
 173}
 174
 175static struct pinctrl_ops foo_pctrl_ops = {
 176        .get_groups_count = foo_get_groups_count,
 177        .get_group_name = foo_get_group_name,
 178        .get_group_pins = foo_get_group_pins,
 179};
 180
 181
 182static struct pinctrl_desc foo_desc = {
 183       ...
 184       .pctlops = &foo_pctrl_ops,
 185};
 186
 187The pin control subsystem will call the .get_groups_count() function to
 188determine total number of legal selectors, then it will call the other functions
 189to retrieve the name and pins of the group. Maintaining the data structure of
 190the groups is up to the driver, this is just a simple example - in practice you
 191may need more entries in your group structure, for example specific register
 192ranges associated with each group and so on.
 193
 194
 195Pin configuration
 196=================
 197
 198Pins can sometimes be software-configured in an various ways, mostly related
 199to their electronic properties when used as inputs or outputs. For example you
 200may be able to make an output pin high impedance, or "tristate" meaning it is
 201effectively disconnected. You may be able to connect an input pin to VDD or GND
 202using a certain resistor value - pull up and pull down - so that the pin has a
 203stable value when nothing is driving the rail it is connected to, or when it's
 204unconnected.
 205
 206Pin configuration can be programmed by adding configuration entries into the
 207mapping table; see section "Board/machine configuration" below.
 208
 209The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
 210above, is entirely defined by the pin controller driver.
 211
 212The pin configuration driver implements callbacks for changing pin
 213configuration in the pin controller ops like this:
 214
 215#include <linux/pinctrl/pinctrl.h>
 216#include <linux/pinctrl/pinconf.h>
 217#include "platform_x_pindefs.h"
 218
 219static int foo_pin_config_get(struct pinctrl_dev *pctldev,
 220                    unsigned offset,
 221                    unsigned long *config)
 222{
 223        struct my_conftype conf;
 224
 225        ... Find setting for pin @ offset ...
 226
 227        *config = (unsigned long) conf;
 228}
 229
 230static int foo_pin_config_set(struct pinctrl_dev *pctldev,
 231                    unsigned offset,
 232                    unsigned long config)
 233{
 234        struct my_conftype *conf = (struct my_conftype *) config;
 235
 236        switch (conf) {
 237                case PLATFORM_X_PULL_UP:
 238                ...
 239                }
 240        }
 241}
 242
 243static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
 244                    unsigned selector,
 245                    unsigned long *config)
 246{
 247        ...
 248}
 249
 250static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
 251                    unsigned selector,
 252                    unsigned long config)
 253{
 254        ...
 255}
 256
 257static struct pinconf_ops foo_pconf_ops = {
 258        .pin_config_get = foo_pin_config_get,
 259        .pin_config_set = foo_pin_config_set,
 260        .pin_config_group_get = foo_pin_config_group_get,
 261        .pin_config_group_set = foo_pin_config_group_set,
 262};
 263
 264/* Pin config operations are handled by some pin controller */
 265static struct pinctrl_desc foo_desc = {
 266        ...
 267        .confops = &foo_pconf_ops,
 268};
 269
 270Since some controllers have special logic for handling entire groups of pins
 271they can exploit the special whole-group pin control function. The
 272pin_config_group_set() callback is allowed to return the error code -EAGAIN,
 273for groups it does not want to handle, or if it just wants to do some
 274group-level handling and then fall through to iterate over all pins, in which
 275case each individual pin will be treated by separate pin_config_set() calls as
 276well.
 277
 278
 279Interaction with the GPIO subsystem
 280===================================
 281
 282The GPIO drivers may want to perform operations of various types on the same
 283physical pins that are also registered as pin controller pins.
 284
 285First and foremost, the two subsystems can be used as completely orthogonal,
 286see the section named "pin control requests from drivers" and
 287"drivers needing both pin control and GPIOs" below for details. But in some
 288situations a cross-subsystem mapping between pins and GPIOs is needed.
 289
 290Since the pin controller subsystem have its pinspace local to the pin
 291controller we need a mapping so that the pin control subsystem can figure out
 292which pin controller handles control of a certain GPIO pin. Since a single
 293pin controller may be muxing several GPIO ranges (typically SoCs that have
 294one set of pins but internally several GPIO silicon blocks, each modelled as
 295a struct gpio_chip) any number of GPIO ranges can be added to a pin controller
 296instance like this:
 297
 298struct gpio_chip chip_a;
 299struct gpio_chip chip_b;
 300
 301static struct pinctrl_gpio_range gpio_range_a = {
 302        .name = "chip a",
 303        .id = 0,
 304        .base = 32,
 305        .pin_base = 32,
 306        .npins = 16,
 307        .gc = &chip_a;
 308};
 309
 310static struct pinctrl_gpio_range gpio_range_b = {
 311        .name = "chip b",
 312        .id = 0,
 313        .base = 48,
 314        .pin_base = 64,
 315        .npins = 8,
 316        .gc = &chip_b;
 317};
 318
 319{
 320        struct pinctrl_dev *pctl;
 321        ...
 322        pinctrl_add_gpio_range(pctl, &gpio_range_a);
 323        pinctrl_add_gpio_range(pctl, &gpio_range_b);
 324}
 325
 326So this complex system has one pin controller handling two different
 327GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
 328"chip b" have different .pin_base, which means a start pin number of the
 329GPIO range.
 330
 331The GPIO range of "chip a" starts from the GPIO base of 32 and actual
 332pin range also starts from 32. However "chip b" has different starting
 333offset for the GPIO range and pin range. The GPIO range of "chip b" starts
 334from GPIO number 48, while the pin range of "chip b" starts from 64.
 335
 336We can convert a gpio number to actual pin number using this "pin_base".
 337They are mapped in the global GPIO pin space at:
 338
 339chip a:
 340 - GPIO range : [32 .. 47]
 341 - pin range  : [32 .. 47]
 342chip b:
 343 - GPIO range : [48 .. 55]
 344 - pin range  : [64 .. 71]
 345
 346The above examples assume the mapping between the GPIOs and pins is
 347linear. If the mapping is sparse or haphazard, an array of arbitrary pin
 348numbers can be encoded in the range like this:
 349
 350static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };
 351
 352static struct pinctrl_gpio_range gpio_range = {
 353        .name = "chip",
 354        .id = 0,
 355        .base = 32,
 356        .pins = &range_pins,
 357        .npins = ARRAY_SIZE(range_pins),
 358        .gc = &chip;
 359};
 360
 361In this case the pin_base property will be ignored.
 362
 363When GPIO-specific functions in the pin control subsystem are called, these
 364ranges will be used to look up the appropriate pin controller by inspecting
 365and matching the pin to the pin ranges across all controllers. When a
 366pin controller handling the matching range is found, GPIO-specific functions
 367will be called on that specific pin controller.
 368
 369For all functionalities dealing with pin biasing, pin muxing etc, the pin
 370controller subsystem will look up the corresponding pin number from the passed
 371in gpio number, and use the range's internals to retrive a pin number. After
 372that, the subsystem passes it on to the pin control driver, so the driver
 373will get an pin number into its handled number range. Further it is also passed
 374the range ID value, so that the pin controller knows which range it should
 375deal with.
 376
 377Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see
 378section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind
 379pinctrl and gpio drivers.
 380
 381
 382PINMUX interfaces
 383=================
 384
 385These calls use the pinmux_* naming prefix.  No other calls should use that
 386prefix.
 387
 388
 389What is pinmuxing?
 390==================
 391
 392PINMUX, also known as padmux, ballmux, alternate functions or mission modes
 393is a way for chip vendors producing some kind of electrical packages to use
 394a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
 395functions, depending on the application. By "application" in this context
 396we usually mean a way of soldering or wiring the package into an electronic
 397system, even though the framework makes it possible to also change the function
 398at runtime.
 399
 400Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
 401
 402        A   B   C   D   E   F   G   H
 403      +---+
 404   8  | o | o   o   o   o   o   o   o
 405      |   |
 406   7  | o | o   o   o   o   o   o   o
 407      |   |
 408   6  | o | o   o   o   o   o   o   o
 409      +---+---+
 410   5  | o | o | o   o   o   o   o   o
 411      +---+---+               +---+
 412   4    o   o   o   o   o   o | o | o
 413                              |   |
 414   3    o   o   o   o   o   o | o | o
 415                              |   |
 416   2    o   o   o   o   o   o | o | o
 417      +-------+-------+-------+---+---+
 418   1  | o   o | o   o | o   o | o | o |
 419      +-------+-------+-------+---+---+
 420
 421This is not tetris. The game to think of is chess. Not all PGA/BGA packages
 422are chessboard-like, big ones have "holes" in some arrangement according to
 423different design patterns, but we're using this as a simple example. Of the
 424pins you see some will be taken by things like a few VCC and GND to feed power
 425to the chip, and quite a few will be taken by large ports like an external
 426memory interface. The remaining pins will often be subject to pin multiplexing.
 427
 428The example 8x8 PGA package above will have pin numbers 0 thru 63 assigned to
 429its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
 430pinctrl_register_pins() and a suitable data set as shown earlier.
 431
 432In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
 433(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
 434some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
 435be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
 436we cannot use the SPI port and I2C port at the same time. However in the inside
 437of the package the silicon performing the SPI logic can alternatively be routed
 438out on pins { G4, G3, G2, G1 }.
 439
 440On the botton row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
 441special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
 442consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
 443{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
 444port on pins { G4, G3, G2, G1 } of course.
 445
 446This way the silicon blocks present inside the chip can be multiplexed "muxed"
 447out on different pin ranges. Often contemporary SoC (systems on chip) will
 448contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
 449different pins by pinmux settings.
 450
 451Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
 452common to be able to use almost any pin as a GPIO pin if it is not currently
 453in use by some other I/O port.
 454
 455
 456Pinmux conventions
 457==================
 458
 459The purpose of the pinmux functionality in the pin controller subsystem is to
 460abstract and provide pinmux settings to the devices you choose to instantiate
 461in your machine configuration. It is inspired by the clk, GPIO and regulator
 462subsystems, so devices will request their mux setting, but it's also possible
 463to request a single pin for e.g. GPIO.
 464
 465Definitions:
 466
 467- FUNCTIONS can be switched in and out by a driver residing with the pin
 468  control subsystem in the drivers/pinctrl/* directory of the kernel. The
 469  pin control driver knows the possible functions. In the example above you can
 470  identify three pinmux functions, one for spi, one for i2c and one for mmc.
 471
 472- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
 473  In this case the array could be something like: { spi0, i2c0, mmc0 }
 474  for the three available functions.
 475
 476- FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
 477  function is *always* associated with a certain set of pin groups, could
 478  be just a single one, but could also be many. In the example above the
 479  function i2c is associated with the pins { A5, B5 }, enumerated as
 480  { 24, 25 } in the controller pin space.
 481
 482  The Function spi is associated with pin groups { A8, A7, A6, A5 }
 483  and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
 484  { 38, 46, 54, 62 } respectively.
 485
 486  Group names must be unique per pin controller, no two groups on the same
 487  controller may have the same name.
 488
 489- The combination of a FUNCTION and a PIN GROUP determine a certain function
 490  for a certain set of pins. The knowledge of the functions and pin groups
 491  and their machine-specific particulars are kept inside the pinmux driver,
 492  from the outside only the enumerators are known, and the driver core can:
 493
 494  - Request the name of a function with a certain selector (>= 0)
 495  - A list of groups associated with a certain function
 496  - Request that a certain group in that list to be activated for a certain
 497    function
 498
 499  As already described above, pin groups are in turn self-descriptive, so
 500  the core will retrieve the actual pin range in a certain group from the
 501  driver.
 502
 503- FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
 504  device by the board file, device tree or similar machine setup configuration
 505  mechanism, similar to how regulators are connected to devices, usually by
 506  name. Defining a pin controller, function and group thus uniquely identify
 507  the set of pins to be used by a certain device. (If only one possible group
 508  of pins is available for the function, no group name need to be supplied -
 509  the core will simply select the first and only group available.)
 510
 511  In the example case we can define that this particular machine shall
 512  use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
 513  fi2c0 group gi2c0, on the primary pin controller, we get mappings
 514  like these:
 515
 516  {
 517    {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
 518    {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
 519  }
 520
 521  Every map must be assigned a state name, pin controller, device and
 522  function. The group is not compulsory - if it is omitted the first group
 523  presented by the driver as applicable for the function will be selected,
 524  which is useful for simple cases.
 525
 526  It is possible to map several groups to the same combination of device,
 527  pin controller and function. This is for cases where a certain function on
 528  a certain pin controller may use different sets of pins in different
 529  configurations.
 530
 531- PINS for a certain FUNCTION using a certain PIN GROUP on a certain
 532  PIN CONTROLLER are provided on a first-come first-serve basis, so if some
 533  other device mux setting or GPIO pin request has already taken your physical
 534  pin, you will be denied the use of it. To get (activate) a new setting, the
 535  old one has to be put (deactivated) first.
 536
 537Sometimes the documentation and hardware registers will be oriented around
 538pads (or "fingers") rather than pins - these are the soldering surfaces on the
 539silicon inside the package, and may or may not match the actual number of
 540pins/balls underneath the capsule. Pick some enumeration that makes sense to
 541you. Define enumerators only for the pins you can control if that makes sense.
 542
 543Assumptions:
 544
 545We assume that the number of possible function maps to pin groups is limited by
 546the hardware. I.e. we assume that there is no system where any function can be
 547mapped to any pin, like in a phone exchange. So the available pins groups for
 548a certain function will be limited to a few choices (say up to eight or so),
 549not hundreds or any amount of choices. This is the characteristic we have found
 550by inspecting available pinmux hardware, and a necessary assumption since we
 551expect pinmux drivers to present *all* possible function vs pin group mappings
 552to the subsystem.
 553
 554
 555Pinmux drivers
 556==============
 557
 558The pinmux core takes care of preventing conflicts on pins and calling
 559the pin controller driver to execute different settings.
 560
 561It is the responsibility of the pinmux driver to impose further restrictions
 562(say for example infer electronic limitations due to load etc) to determine
 563whether or not the requested function can actually be allowed, and in case it
 564is possible to perform the requested mux setting, poke the hardware so that
 565this happens.
 566
 567Pinmux drivers are required to supply a few callback functions, some are
 568optional. Usually the enable() and disable() functions are implemented,
 569writing values into some certain registers to activate a certain mux setting
 570for a certain pin.
 571
 572A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
 573into some register named MUX to select a certain function with a certain
 574group of pins would work something like this:
 575
 576#include <linux/pinctrl/pinctrl.h>
 577#include <linux/pinctrl/pinmux.h>
 578
 579struct foo_group {
 580        const char *name;
 581        const unsigned int *pins;
 582        const unsigned num_pins;
 583};
 584
 585static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
 586static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
 587static const unsigned i2c0_pins[] = { 24, 25 };
 588static const unsigned mmc0_1_pins[] = { 56, 57 };
 589static const unsigned mmc0_2_pins[] = { 58, 59 };
 590static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
 591
 592static const struct foo_group foo_groups[] = {
 593        {
 594                .name = "spi0_0_grp",
 595                .pins = spi0_0_pins,
 596                .num_pins = ARRAY_SIZE(spi0_0_pins),
 597        },
 598        {
 599                .name = "spi0_1_grp",
 600                .pins = spi0_1_pins,
 601                .num_pins = ARRAY_SIZE(spi0_1_pins),
 602        },
 603        {
 604                .name = "i2c0_grp",
 605                .pins = i2c0_pins,
 606                .num_pins = ARRAY_SIZE(i2c0_pins),
 607        },
 608        {
 609                .name = "mmc0_1_grp",
 610                .pins = mmc0_1_pins,
 611                .num_pins = ARRAY_SIZE(mmc0_1_pins),
 612        },
 613        {
 614                .name = "mmc0_2_grp",
 615                .pins = mmc0_2_pins,
 616                .num_pins = ARRAY_SIZE(mmc0_2_pins),
 617        },
 618        {
 619                .name = "mmc0_3_grp",
 620                .pins = mmc0_3_pins,
 621                .num_pins = ARRAY_SIZE(mmc0_3_pins),
 622        },
 623};
 624
 625
 626static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 627{
 628        return ARRAY_SIZE(foo_groups);
 629}
 630
 631static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
 632                                       unsigned selector)
 633{
 634        return foo_groups[selector].name;
 635}
 636
 637static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 638                               unsigned ** const pins,
 639                               unsigned * const num_pins)
 640{
 641        *pins = (unsigned *) foo_groups[selector].pins;
 642        *num_pins = foo_groups[selector].num_pins;
 643        return 0;
 644}
 645
 646static struct pinctrl_ops foo_pctrl_ops = {
 647        .get_groups_count = foo_get_groups_count,
 648        .get_group_name = foo_get_group_name,
 649        .get_group_pins = foo_get_group_pins,
 650};
 651
 652struct foo_pmx_func {
 653        const char *name;
 654        const char * const *groups;
 655        const unsigned num_groups;
 656};
 657
 658static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
 659static const char * const i2c0_groups[] = { "i2c0_grp" };
 660static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
 661                                        "mmc0_3_grp" };
 662
 663static const struct foo_pmx_func foo_functions[] = {
 664        {
 665                .name = "spi0",
 666                .groups = spi0_groups,
 667                .num_groups = ARRAY_SIZE(spi0_groups),
 668        },
 669        {
 670                .name = "i2c0",
 671                .groups = i2c0_groups,
 672                .num_groups = ARRAY_SIZE(i2c0_groups),
 673        },
 674        {
 675                .name = "mmc0",
 676                .groups = mmc0_groups,
 677                .num_groups = ARRAY_SIZE(mmc0_groups),
 678        },
 679};
 680
 681int foo_get_functions_count(struct pinctrl_dev *pctldev)
 682{
 683        return ARRAY_SIZE(foo_functions);
 684}
 685
 686const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
 687{
 688        return foo_functions[selector].name;
 689}
 690
 691static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 692                          const char * const **groups,
 693                          unsigned * const num_groups)
 694{
 695        *groups = foo_functions[selector].groups;
 696        *num_groups = foo_functions[selector].num_groups;
 697        return 0;
 698}
 699
 700int foo_enable(struct pinctrl_dev *pctldev, unsigned selector,
 701                unsigned group)
 702{
 703        u8 regbit = (1 << selector + group);
 704
 705        writeb((readb(MUX)|regbit), MUX)
 706        return 0;
 707}
 708
 709void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
 710                unsigned group)
 711{
 712        u8 regbit = (1 << selector + group);
 713
 714        writeb((readb(MUX) & ~(regbit)), MUX)
 715        return 0;
 716}
 717
 718struct pinmux_ops foo_pmxops = {
 719        .get_functions_count = foo_get_functions_count,
 720        .get_function_name = foo_get_fname,
 721        .get_function_groups = foo_get_groups,
 722        .enable = foo_enable,
 723        .disable = foo_disable,
 724};
 725
 726/* Pinmux operations are handled by some pin controller */
 727static struct pinctrl_desc foo_desc = {
 728        ...
 729        .pctlops = &foo_pctrl_ops,
 730        .pmxops = &foo_pmxops,
 731};
 732
 733In the example activating muxing 0 and 1 at the same time setting bits
 7340 and 1, uses one pin in common so they would collide.
 735
 736The beauty of the pinmux subsystem is that since it keeps track of all
 737pins and who is using them, it will already have denied an impossible
 738request like that, so the driver does not need to worry about such
 739things - when it gets a selector passed in, the pinmux subsystem makes
 740sure no other device or GPIO assignment is already using the selected
 741pins. Thus bits 0 and 1 in the control register will never be set at the
 742same time.
 743
 744All the above functions are mandatory to implement for a pinmux driver.
 745
 746
 747Pin control interaction with the GPIO subsystem
 748===============================================
 749
 750Note that the following implies that the use case is to use a certain pin
 751from the Linux kernel using the API in <linux/gpio.h> with gpio_request()
 752and similar functions. There are cases where you may be using something
 753that your datasheet calls "GPIO mode" but actually is just an electrical
 754configuration for a certain device. See the section below named
 755"GPIO mode pitfalls" for more details on this scenario.
 756
 757The public pinmux API contains two functions named pinctrl_request_gpio()
 758and pinctrl_free_gpio(). These two functions shall *ONLY* be called from
 759gpiolib-based drivers as part of their gpio_request() and
 760gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
 761shall only be called from within respective gpio_direction_[input|output]
 762gpiolib implementation.
 763
 764NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
 765controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
 766that driver request proper muxing and other control for its pins.
 767
 768The function list could become long, especially if you can convert every
 769individual pin into a GPIO pin independent of any other pins, and then try
 770the approach to define every pin as a function.
 771
 772In this case, the function array would become 64 entries for each GPIO
 773setting and then the device functions.
 774
 775For this reason there are two functions a pin control driver can implement
 776to enable only GPIO on an individual pin: .gpio_request_enable() and
 777.gpio_disable_free().
 778
 779This function will pass in the affected GPIO range identified by the pin
 780controller core, so you know which GPIO pins are being affected by the request
 781operation.
 782
 783If your driver needs to have an indication from the framework of whether the
 784GPIO pin shall be used for input or output you can implement the
 785.gpio_set_direction() function. As described this shall be called from the
 786gpiolib driver and the affected GPIO range, pin offset and desired direction
 787will be passed along to this function.
 788
 789Alternatively to using these special functions, it is fully allowed to use
 790named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to
 791obtain the function "gpioN" where "N" is the global GPIO pin number if no
 792special GPIO-handler is registered.
 793
 794
 795GPIO mode pitfalls
 796==================
 797
 798Due to the naming conventions used by hardware engineers, where "GPIO"
 799is taken to mean different things than what the kernel does, the developer
 800may be confused by a datasheet talking about a pin being possible to set
 801into "GPIO mode". It appears that what hardware engineers mean with
 802"GPIO mode" is not necessarily the use case that is implied in the kernel
 803interface <linux/gpio.h>: a pin that you grab from kernel code and then
 804either listen for input or drive high/low to assert/deassert some
 805external line.
 806
 807Rather hardware engineers think that "GPIO mode" means that you can
 808software-control a few electrical properties of the pin that you would
 809not be able to control if the pin was in some other mode, such as muxed in
 810for a device.
 811
 812The GPIO portions of a pin and its relation to a certain pin controller
 813configuration and muxing logic can be constructed in several ways. Here
 814are two examples:
 815
 816(A)
 817                       pin config
 818                       logic regs
 819                       |               +- SPI
 820     Physical pins --- pad --- pinmux -+- I2C
 821                               |       +- mmc
 822                               |       +- GPIO
 823                               pin
 824                               multiplex
 825                               logic regs
 826
 827Here some electrical properties of the pin can be configured no matter
 828whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
 829pin, you can also drive it high/low from "GPIO" registers.
 830Alternatively, the pin can be controlled by a certain peripheral, while
 831still applying desired pin config properties. GPIO functionality is thus
 832orthogonal to any other device using the pin.
 833
 834In this arrangement the registers for the GPIO portions of the pin controller,
 835or the registers for the GPIO hardware module are likely to reside in a
 836separate memory range only intended for GPIO driving, and the register
 837range dealing with pin config and pin multiplexing get placed into a
 838different memory range and a separate section of the data sheet.
 839
 840(B)
 841
 842                       pin config
 843                       logic regs
 844                       |               +- SPI
 845     Physical pins --- pad --- pinmux -+- I2C
 846                       |       |       +- mmc
 847                       |       |
 848                       GPIO    pin
 849                               multiplex
 850                               logic regs
 851
 852In this arrangement, the GPIO functionality can always be enabled, such that
 853e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
 854pulsed out. It is likely possible to disrupt the traffic on the pin by doing
 855wrong things on the GPIO block, as it is never really disconnected. It is
 856possible that the GPIO, pin config and pin multiplex registers are placed into
 857the same memory range and the same section of the data sheet, although that
 858need not be the case.
 859
 860From a kernel point of view, however, these are different aspects of the
 861hardware and shall be put into different subsystems:
 862
 863- Registers (or fields within registers) that control electrical
 864  properties of the pin such as biasing and drive strength should be
 865  exposed through the pinctrl subsystem, as "pin configuration" settings.
 866
 867- Registers (or fields within registers) that control muxing of signals
 868  from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
 869  be exposed through the pinctrl subssytem, as mux functions.
 870
 871- Registers (or fields within registers) that control GPIO functionality
 872  such as setting a GPIO's output value, reading a GPIO's input value, or
 873  setting GPIO pin direction should be exposed through the GPIO subsystem,
 874  and if they also support interrupt capabilities, through the irqchip
 875  abstraction.
 876
 877Depending on the exact HW register design, some functions exposed by the
 878GPIO subsystem may call into the pinctrl subsystem in order to
 879co-ordinate register settings across HW modules. In particular, this may
 880be needed for HW with separate GPIO and pin controller HW modules, where
 881e.g. GPIO direction is determined by a register in the pin controller HW
 882module rather than the GPIO HW module.
 883
 884Electrical properties of the pin such as biasing and drive strength
 885may be placed at some pin-specific register in all cases or as part
 886of the GPIO register in case (B) especially. This doesn't mean that such
 887properties necessarily pertain to what the Linux kernel calls "GPIO".
 888
 889Example: a pin is usually muxed in to be used as a UART TX line. But during
 890system sleep, we need to put this pin into "GPIO mode" and ground it.
 891
 892If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
 893to think that you need to come up with something real complex, that the
 894pin shall be used for UART TX and GPIO at the same time, that you will grab
 895a pin control handle and set it to a certain state to enable UART TX to be
 896muxed in, then twist it over to GPIO mode and use gpio_direction_output()
 897to drive it low during sleep, then mux it over to UART TX again when you
 898wake up and maybe even gpio_request/gpio_free as part of this cycle. This
 899all gets very complicated.
 900
 901The solution is to not think that what the datasheet calls "GPIO mode"
 902has to be handled by the <linux/gpio.h> interface. Instead view this as
 903a certain pin config setting. Look in e.g. <linux/pinctrl/pinconf-generic.h>
 904and you find this in the documentation:
 905
 906  PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument
 907     1 to indicate high level, argument 0 to indicate low level.
 908
 909So it is perfectly possible to push a pin into "GPIO mode" and drive the
 910line low as part of the usual pin control map. So for example your UART
 911driver may look like this:
 912
 913#include <linux/pinctrl/consumer.h>
 914
 915struct pinctrl          *pinctrl;
 916struct pinctrl_state    *pins_default;
 917struct pinctrl_state    *pins_sleep;
 918
 919pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
 920pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);
 921
 922/* Normal mode */
 923retval = pinctrl_select_state(pinctrl, pins_default);
 924/* Sleep mode */
 925retval = pinctrl_select_state(pinctrl, pins_sleep);
 926
 927And your machine configuration may look like this:
 928--------------------------------------------------
 929
 930static unsigned long uart_default_mode[] = {
 931    PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
 932};
 933
 934static unsigned long uart_sleep_mode[] = {
 935    PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
 936};
 937
 938static struct pinctrl_map pinmap[] __initdata = {
 939    PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
 940                      "u0_group", "u0"),
 941    PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
 942                        "UART_TX_PIN", uart_default_mode),
 943    PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
 944                      "u0_group", "gpio-mode"),
 945    PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
 946                        "UART_TX_PIN", uart_sleep_mode),
 947};
 948
 949foo_init(void) {
 950    pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
 951}
 952
 953Here the pins we want to control are in the "u0_group" and there is some
 954function called "u0" that can be enabled on this group of pins, and then
 955everything is UART business as usual. But there is also some function
 956named "gpio-mode" that can be mapped onto the same pins to move them into
 957GPIO mode.
 958
 959This will give the desired effect without any bogus interaction with the
 960GPIO subsystem. It is just an electrical configuration used by that device
 961when going to sleep, it might imply that the pin is set into something the
 962datasheet calls "GPIO mode" but that is not the point: it is still used
 963by that UART device to control the pins that pertain to that very UART
 964driver, putting them into modes needed by the UART. GPIO in the Linux
 965kernel sense are just some 1-bit line, and is a different use case.
 966
 967How the registers are poked to attain the push/pull and output low
 968configuration and the muxing of the "u0" or "gpio-mode" group onto these
 969pins is a question for the driver.
 970
 971Some datasheets will be more helpful and refer to the "GPIO mode" as
 972"low power mode" rather than anything to do with GPIO. This often means
 973the same thing electrically speaking, but in this latter case the
 974software engineers will usually quickly identify that this is some
 975specific muxing/configuration rather than anything related to the GPIO
 976API.
 977
 978
 979Board/machine configuration
 980==================================
 981
 982Boards and machines define how a certain complete running system is put
 983together, including how GPIOs and devices are muxed, how regulators are
 984constrained and how the clock tree looks. Of course pinmux settings are also
 985part of this.
 986
 987A pin controller configuration for a machine looks pretty much like a simple
 988regulator configuration, so for the example array above we want to enable i2c
 989and spi on the second function mapping:
 990
 991#include <linux/pinctrl/machine.h>
 992
 993static const struct pinctrl_map mapping[] __initconst = {
 994        {
 995                .dev_name = "foo-spi.0",
 996                .name = PINCTRL_STATE_DEFAULT,
 997                .type = PIN_MAP_TYPE_MUX_GROUP,
 998                .ctrl_dev_name = "pinctrl-foo",
 999                .data.mux.function = "spi0",
1000        },
1001        {
1002                .dev_name = "foo-i2c.0",
1003                .name = PINCTRL_STATE_DEFAULT,
1004                .type = PIN_MAP_TYPE_MUX_GROUP,
1005                .ctrl_dev_name = "pinctrl-foo",
1006                .data.mux.function = "i2c0",
1007        },
1008        {
1009                .dev_name = "foo-mmc.0",
1010                .name = PINCTRL_STATE_DEFAULT,
1011                .type = PIN_MAP_TYPE_MUX_GROUP,
1012                .ctrl_dev_name = "pinctrl-foo",
1013                .data.mux.function = "mmc0",
1014        },
1015};
1016
1017The dev_name here matches to the unique device name that can be used to look
1018up the device struct (just like with clockdev or regulators). The function name
1019must match a function provided by the pinmux driver handling this pin range.
1020
1021As you can see we may have several pin controllers on the system and thus
1022we need to specify which one of them that contain the functions we wish
1023to map.
1024
1025You register this pinmux mapping to the pinmux subsystem by simply:
1026
1027       ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
1028
1029Since the above construct is pretty common there is a helper macro to make
1030it even more compact which assumes you want to use pinctrl-foo and position
10310 for mapping, for example:
1032
1033static struct pinctrl_map mapping[] __initdata = {
1034        PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"),
1035};
1036
1037The mapping table may also contain pin configuration entries. It's common for
1038each pin/group to have a number of configuration entries that affect it, so
1039the table entries for configuration reference an array of config parameters
1040and values. An example using the convenience macros is shown below:
1041
1042static unsigned long i2c_grp_configs[] = {
1043        FOO_PIN_DRIVEN,
1044        FOO_PIN_PULLUP,
1045};
1046
1047static unsigned long i2c_pin_configs[] = {
1048        FOO_OPEN_COLLECTOR,
1049        FOO_SLEW_RATE_SLOW,
1050};
1051
1052static struct pinctrl_map mapping[] __initdata = {
1053        PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"),
1054        PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
1055        PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
1056        PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs),
1057};
1058
1059Finally, some devices expect the mapping table to contain certain specific
1060named states. When running on hardware that doesn't need any pin controller
1061configuration, the mapping table must still contain those named states, in
1062order to explicitly indicate that the states were provided and intended to
1063be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
1064a named state without causing any pin controller to be programmed:
1065
1066static struct pinctrl_map mapping[] __initdata = {
1067        PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
1068};
1069
1070
1071Complex mappings
1072================
1073
1074As it is possible to map a function to different groups of pins an optional
1075.group can be specified like this:
1076
1077...
1078{
1079        .dev_name = "foo-spi.0",
1080        .name = "spi0-pos-A",
1081        .type = PIN_MAP_TYPE_MUX_GROUP,
1082        .ctrl_dev_name = "pinctrl-foo",
1083        .function = "spi0",
1084        .group = "spi0_0_grp",
1085},
1086{
1087        .dev_name = "foo-spi.0",
1088        .name = "spi0-pos-B",
1089        .type = PIN_MAP_TYPE_MUX_GROUP,
1090        .ctrl_dev_name = "pinctrl-foo",
1091        .function = "spi0",
1092        .group = "spi0_1_grp",
1093},
1094...
1095
1096This example mapping is used to switch between two positions for spi0 at
1097runtime, as described further below under the heading "Runtime pinmuxing".
1098
1099Further it is possible for one named state to affect the muxing of several
1100groups of pins, say for example in the mmc0 example above, where you can
1101additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
1102three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
1103case), we define a mapping like this:
1104
1105...
1106{
1107        .dev_name = "foo-mmc.0",
1108        .name = "2bit"
1109        .type = PIN_MAP_TYPE_MUX_GROUP,
1110        .ctrl_dev_name = "pinctrl-foo",
1111        .function = "mmc0",
1112        .group = "mmc0_1_grp",
1113},
1114{
1115        .dev_name = "foo-mmc.0",
1116        .name = "4bit"
1117        .type = PIN_MAP_TYPE_MUX_GROUP,
1118        .ctrl_dev_name = "pinctrl-foo",
1119        .function = "mmc0",
1120        .group = "mmc0_1_grp",
1121},
1122{
1123        .dev_name = "foo-mmc.0",
1124        .name = "4bit"
1125        .type = PIN_MAP_TYPE_MUX_GROUP,
1126        .ctrl_dev_name = "pinctrl-foo",
1127        .function = "mmc0",
1128        .group = "mmc0_2_grp",
1129},
1130{
1131        .dev_name = "foo-mmc.0",
1132        .name = "8bit"
1133        .type = PIN_MAP_TYPE_MUX_GROUP,
1134        .ctrl_dev_name = "pinctrl-foo",
1135        .function = "mmc0",
1136        .group = "mmc0_1_grp",
1137},
1138{
1139        .dev_name = "foo-mmc.0",
1140        .name = "8bit"
1141        .type = PIN_MAP_TYPE_MUX_GROUP,
1142        .ctrl_dev_name = "pinctrl-foo",
1143        .function = "mmc0",
1144        .group = "mmc0_2_grp",
1145},
1146{
1147        .dev_name = "foo-mmc.0",
1148        .name = "8bit"
1149        .type = PIN_MAP_TYPE_MUX_GROUP,
1150        .ctrl_dev_name = "pinctrl-foo",
1151        .function = "mmc0",
1152        .group = "mmc0_3_grp",
1153},
1154...
1155
1156The result of grabbing this mapping from the device with something like
1157this (see next paragraph):
1158
1159        p = devm_pinctrl_get(dev);
1160        s = pinctrl_lookup_state(p, "8bit");
1161        ret = pinctrl_select_state(p, s);
1162
1163or more simply:
1164
1165        p = devm_pinctrl_get_select(dev, "8bit");
1166
1167Will be that you activate all the three bottom records in the mapping at
1168once. Since they share the same name, pin controller device, function and
1169device, and since we allow multiple groups to match to a single device, they
1170all get selected, and they all get enabled and disable simultaneously by the
1171pinmux core.
1172
1173
1174Pin control requests from drivers
1175=================================
1176
1177When a device driver is about to probe the device core will automatically
1178attempt to issue pinctrl_get_select_default() on these devices.
1179This way driver writers do not need to add any of the boilerplate code
1180of the type found below. However when doing fine-grained state selection
1181and not using the "default" state, you may have to do some device driver
1182handling of the pinctrl handles and states.
1183
1184So if you just want to put the pins for a certain device into the default
1185state and be done with it, there is nothing you need to do besides
1186providing the proper mapping table. The device core will take care of
1187the rest.
1188
1189Generally it is discouraged to let individual drivers get and enable pin
1190control. So if possible, handle the pin control in platform code or some other
1191place where you have access to all the affected struct device * pointers. In
1192some cases where a driver needs to e.g. switch between different mux mappings
1193at runtime this is not possible.
1194
1195A typical case is if a driver needs to switch bias of pins from normal
1196operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
1197PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
1198current in sleep mode.
1199
1200A driver may request a certain control state to be activated, usually just the
1201default state like this:
1202
1203#include <linux/pinctrl/consumer.h>
1204
1205struct foo_state {
1206       struct pinctrl *p;
1207       struct pinctrl_state *s;
1208       ...
1209};
1210
1211foo_probe()
1212{
1213        /* Allocate a state holder named "foo" etc */
1214        struct foo_state *foo = ...;
1215
1216        foo->p = devm_pinctrl_get(&device);
1217        if (IS_ERR(foo->p)) {
1218                /* FIXME: clean up "foo" here */
1219                return PTR_ERR(foo->p);
1220        }
1221
1222        foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1223        if (IS_ERR(foo->s)) {
1224                /* FIXME: clean up "foo" here */
1225                return PTR_ERR(s);
1226        }
1227
1228        ret = pinctrl_select_state(foo->s);
1229        if (ret < 0) {
1230                /* FIXME: clean up "foo" here */
1231                return ret;
1232        }
1233}
1234
1235This get/lookup/select/put sequence can just as well be handled by bus drivers
1236if you don't want each and every driver to handle it and you know the
1237arrangement on your bus.
1238
1239The semantics of the pinctrl APIs are:
1240
1241- pinctrl_get() is called in process context to obtain a handle to all pinctrl
1242  information for a given client device. It will allocate a struct from the
1243  kernel memory to hold the pinmux state. All mapping table parsing or similar
1244  slow operations take place within this API.
1245
1246- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1247  to be called automatically on the retrieved pointer when the associated
1248  device is removed. It is recommended to use this function over plain
1249  pinctrl_get().
1250
1251- pinctrl_lookup_state() is called in process context to obtain a handle to a
1252  specific state for a the client device. This operation may be slow too.
1253
1254- pinctrl_select_state() programs pin controller hardware according to the
1255  definition of the state as given by the mapping table. In theory this is a
1256  fast-path operation, since it only involved blasting some register settings
1257  into hardware. However, note that some pin controllers may have their
1258  registers on a slow/IRQ-based bus, so client devices should not assume they
1259  can call pinctrl_select_state() from non-blocking contexts.
1260
1261- pinctrl_put() frees all information associated with a pinctrl handle.
1262
1263- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1264  explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1265  However, use of this function will be rare, due to the automatic cleanup
1266  that will occur even without calling it.
1267
1268  pinctrl_get() must be paired with a plain pinctrl_put().
1269  pinctrl_get() may not be paired with devm_pinctrl_put().
1270  devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1271  devm_pinctrl_get() may not be paired with plain pinctrl_put().
1272
1273Usually the pin control core handled the get/put pair and call out to the
1274device drivers bookkeeping operations, like checking available functions and
1275the associated pins, whereas the enable/disable pass on to the pin controller
1276driver which takes care of activating and/or deactivating the mux setting by
1277quickly poking some registers.
1278
1279The pins are allocated for your device when you issue the devm_pinctrl_get()
1280call, after this you should be able to see this in the debugfs listing of all
1281pins.
1282
1283NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1284requested pinctrl handles, for example if the pinctrl driver has not yet
1285registered. Thus make sure that the error path in your driver gracefully
1286cleans up and is ready to retry the probing later in the startup process.
1287
1288
1289Drivers needing both pin control and GPIOs
1290==========================================
1291
1292Again, it is discouraged to let drivers lookup and select pin control states
1293themselves, but again sometimes this is unavoidable.
1294
1295So say that your driver is fetching its resources like this:
1296
1297#include <linux/pinctrl/consumer.h>
1298#include <linux/gpio.h>
1299
1300struct pinctrl *pinctrl;
1301int gpio;
1302
1303pinctrl = devm_pinctrl_get_select_default(&dev);
1304gpio = devm_gpio_request(&dev, 14, "foo");
1305
1306Here we first request a certain pin state and then request GPIO 14 to be
1307used. If you're using the subsystems orthogonally like this, you should
1308nominally always get your pinctrl handle and select the desired pinctrl
1309state BEFORE requesting the GPIO. This is a semantic convention to avoid
1310situations that can be electrically unpleasant, you will certainly want to
1311mux in and bias pins in a certain way before the GPIO subsystems starts to
1312deal with them.
1313
1314The above can be hidden: using the device core, the pinctrl core may be
1315setting up the config and muxing for the pins right before the device is
1316probing, nevertheless orthogonal to the GPIO subsystem.
1317
1318But there are also situations where it makes sense for the GPIO subsystem
1319to communicate directly with the pinctrl subsystem, using the latter as a
1320back-end. This is when the GPIO driver may call out to the functions
1321described in the section "Pin control interaction with the GPIO subsystem"
1322above. This only involves per-pin multiplexing, and will be completely
1323hidden behind the gpio_*() function namespace. In this case, the driver
1324need not interact with the pin control subsystem at all.
1325
1326If a pin control driver and a GPIO driver is dealing with the same pins
1327and the use cases involve multiplexing, you MUST implement the pin controller
1328as a back-end for the GPIO driver like this, unless your hardware design
1329is such that the GPIO controller can override the pin controller's
1330multiplexing state through hardware without the need to interact with the
1331pin control system.
1332
1333
1334System pin control hogging
1335==========================
1336
1337Pin control map entries can be hogged by the core when the pin controller
1338is registered. This means that the core will attempt to call pinctrl_get(),
1339lookup_state() and select_state() on it immediately after the pin control
1340device has been registered.
1341
1342This occurs for mapping table entries where the client device name is equal
1343to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT.
1344
1345{
1346        .dev_name = "pinctrl-foo",
1347        .name = PINCTRL_STATE_DEFAULT,
1348        .type = PIN_MAP_TYPE_MUX_GROUP,
1349        .ctrl_dev_name = "pinctrl-foo",
1350        .function = "power_func",
1351},
1352
1353Since it may be common to request the core to hog a few always-applicable
1354mux settings on the primary pin controller, there is a convenience macro for
1355this:
1356
1357PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func")
1358
1359This gives the exact same result as the above construction.
1360
1361
1362Runtime pinmuxing
1363=================
1364
1365It is possible to mux a certain function in and out at runtime, say to move
1366an SPI port from one set of pins to another set of pins. Say for example for
1367spi0 in the example above, we expose two different groups of pins for the same
1368function, but with different named in the mapping as described under
1369"Advanced mapping" above. So that for an SPI device, we have two states named
1370"pos-A" and "pos-B".
1371
1372This snippet first muxes the function in the pins defined by group A, enables
1373it, disables and releases it, and muxes it in on the pins defined by group B:
1374
1375#include <linux/pinctrl/consumer.h>
1376
1377struct pinctrl *p;
1378struct pinctrl_state *s1, *s2;
1379
1380foo_probe()
1381{
1382        /* Setup */
1383        p = devm_pinctrl_get(&device);
1384        if (IS_ERR(p))
1385                ...
1386
1387        s1 = pinctrl_lookup_state(foo->p, "pos-A");
1388        if (IS_ERR(s1))
1389                ...
1390
1391        s2 = pinctrl_lookup_state(foo->p, "pos-B");
1392        if (IS_ERR(s2))
1393                ...
1394}
1395
1396foo_switch()
1397{
1398        /* Enable on position A */
1399        ret = pinctrl_select_state(s1);
1400        if (ret < 0)
1401            ...
1402
1403        ...
1404
1405        /* Enable on position B */
1406        ret = pinctrl_select_state(s2);
1407        if (ret < 0)
1408            ...
1409
1410        ...
1411}
1412
1413The above has to be done from process context. The reservation of the pins
1414will be done when the state is activated, so in effect one specific pin
1415can be used by different functions at different times on a running system.
1416
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