linux/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
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   1SAMSUNG USB-PHY controllers
   2
   3** Samsung's usb 2.0 phy transceiver
   4
   5The Samsung's usb 2.0 phy transceiver is used for controlling
   6usb 2.0 phy for s3c-hsotg as well as ehci-s5p and ohci-exynos
   7usb controllers across Samsung SOCs.
   8TODO: Adding the PHY binding with controller(s) according to the under
   9development generic PHY driver.
  10
  11Required properties:
  12
  13Exynos4210:
  14- compatible : should be "samsung,exynos4210-usb2phy"
  15- reg : base physical address of the phy registers and length of memory mapped
  16        region.
  17- clocks: Clock IDs array as required by the controller.
  18- clock-names: names of clock correseponding IDs clock property as requested
  19               by the controller driver.
  20
  21Exynos5250:
  22- compatible : should be "samsung,exynos5250-usb2phy"
  23- reg : base physical address of the phy registers and length of memory mapped
  24        region.
  25
  26Optional properties:
  27- #address-cells: should be '1' when usbphy node has a child node with 'reg'
  28                  property.
  29- #size-cells: should be '1' when usbphy node has a child node with 'reg'
  30               property.
  31- ranges: allows valid translation between child's address space and parent's
  32          address space.
  33
  34- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller
  35  interface for usb-phy. It should provide the following information required by
  36  usb-phy controller to control phy.
  37  - reg : base physical address of PHY_CONTROL registers.
  38          The size of this register is the total sum of size of all PHY_CONTROL
  39          registers that the SoC has. For example, the size will be
  40          '0x4' in case we have only one PHY_CONTROL register (e.g.
  41          OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)
  42          and, '0x8' in case we have two PHY_CONTROL registers (e.g.
  43          USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
  44          and so on.
  45
  46Example:
  47 - Exynos4210
  48
  49        usbphy@125B0000 {
  50                #address-cells = <1>;
  51                #size-cells = <1>;
  52                compatible = "samsung,exynos4210-usb2phy";
  53                reg = <0x125B0000 0x100>;
  54                ranges;
  55
  56                clocks = <&clock 2>, <&clock 305>;
  57                clock-names = "xusbxti", "otg";
  58
  59                usbphy-sys {
  60                        /* USB device and host PHY_CONTROL registers */
  61                        reg = <0x10020704 0x8>;
  62                };
  63        };
  64
  65
  66** Samsung's usb 3.0 phy transceiver
  67
  68Starting exynso5250, Samsung's SoC have usb 3.0 phy transceiver
  69which is used for controlling usb 3.0 phy for dwc3-exynos usb 3.0
  70controllers across Samsung SOCs.
  71
  72Required properties:
  73
  74Exynos5250:
  75- compatible : should be "samsung,exynos5250-usb3phy"
  76- reg : base physical address of the phy registers and length of memory mapped
  77        region.
  78- clocks: Clock IDs array as required by the controller.
  79- clock-names: names of clocks correseponding to IDs in the clock property
  80               as requested by the controller driver.
  81
  82Optional properties:
  83- #address-cells: should be '1' when usbphy node has a child node with 'reg'
  84                  property.
  85- #size-cells: should be '1' when usbphy node has a child node with 'reg'
  86               property.
  87- ranges: allows valid translation between child's address space and parent's
  88          address space.
  89
  90- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller
  91  interface for usb-phy. It should provide the following information required by
  92  usb-phy controller to control phy.
  93  - reg : base physical address of PHY_CONTROL registers.
  94          The size of this register is the total sum of size of all PHY_CONTROL
  95          registers that the SoC has. For example, the size will be
  96          '0x4' in case we have only one PHY_CONTROL register (e.g.
  97          OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)
  98          and, '0x8' in case we have two PHY_CONTROL registers (e.g.
  99          USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
 100          and so on.
 101
 102Example:
 103        usbphy@12100000 {
 104                compatible = "samsung,exynos5250-usb3phy";
 105                reg = <0x12100000 0x100>;
 106                #address-cells = <1>;
 107                #size-cells = <1>;
 108                ranges;
 109
 110                clocks = <&clock 1>, <&clock 286>;
 111                clock-names = "ext_xtal", "usbdrd30";
 112
 113                usbphy-sys {
 114                        /* USB device and host PHY_CONTROL registers */
 115                        reg = <0x10040704 0x8>;
 116                };
 117        };
 118