linux/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
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   1* Rockchip Pinmux Controller
   2
   3The Rockchip Pinmux Controller, enables the IC
   4to share one PAD to several functional blocks. The sharing is done by
   5multiplexing the PAD input/output signals. For each PAD there are up to
   64 muxing options with option 0 being the use as a GPIO.
   7
   8Please refer to pinctrl-bindings.txt in this directory for details of the
   9common pinctrl bindings used by client devices, including the meaning of the
  10phrase "pin configuration node".
  11
  12The Rockchip pin configuration node is a node of a group of pins which can be
  13used for a specific device or function. This node represents both mux and
  14config of the pins in that group. The 'pins' selects the function mode(also
  15named pin mode) this pin can work on and the 'config' configures various pad
  16settings such as pull-up, etc.
  17
  18The pins are grouped into up to 5 individual pin banks which need to be
  19defined as gpio sub-nodes of the pinmux controller.
  20
  21Required properties for iomux controller:
  22  - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
  23                       "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
  24
  25Required properties for gpio sub nodes:
  26  - compatible: "rockchip,gpio-bank"
  27  - reg: register of the gpio bank (different than the iomux registerset)
  28  - interrupts: base interrupt of the gpio bank in the interrupt controller
  29  - clocks: clock that drives this bank
  30  - gpio-controller: identifies the node as a gpio controller and pin bank.
  31  - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
  32    binding is used, the amount of cells must be specified as 2. See generic
  33    GPIO binding documentation for description of particular cells.
  34  - interrupt-controller: identifies the controller node as interrupt-parent.
  35  - #interrupt-cells: the value of this property should be 2 and the interrupt
  36    cells should use the standard two-cell scheme described in
  37    bindings/interrupt-controller/interrupts.txt
  38
  39Required properties for pin configuration node:
  40  - rockchip,pins: 3 integers array, represents a group of pins mux and config
  41    setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
  42    The MUX 0 means gpio and MUX 1 to 3 mean the specific device function.
  43    The phandle of a node containing the generic pinconfig options
  44    to use, as described in pinctrl-bindings.txt in this directory.
  45
  46Examples:
  47
  48#include <dt-bindings/pinctrl/rockchip.h>
  49
  50...
  51
  52pinctrl@20008000 {
  53        compatible = "rockchip,rk3066a-pinctrl";
  54        reg = <0x20008000 0x150>;
  55        #address-cells = <1>;
  56        #size-cells = <1>;
  57        ranges;
  58
  59        gpio0: gpio0@20034000 {
  60                compatible = "rockchip,gpio-bank";
  61                reg = <0x20034000 0x100>;
  62                interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
  63                clocks = <&clk_gates8 9>;
  64
  65                gpio-controller;
  66                #gpio-cells = <2>;
  67
  68                interrupt-controller;
  69                #interrupt-cells = <2>;
  70        };
  71
  72        ...
  73
  74        pcfg_pull_default: pcfg_pull_default {
  75                bias-pull-pin-default
  76        };
  77
  78        uart2 {
  79                uart2_xfer: uart2-xfer {
  80                        rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
  81                                        <RK_GPIO1 9 1 &pcfg_pull_default>;
  82                };
  83        };
  84};
  85
  86uart2: serial@20064000 {
  87        compatible = "snps,dw-apb-uart";
  88        reg = <0x20064000 0x400>;
  89        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  90        reg-shift = <2>;
  91        reg-io-width = <1>;
  92        clocks = <&mux_uart2>;
  93        status = "okay";
  94
  95        pinctrl-names = "default";
  96        pinctrl-0 = <&uart2_xfer>;
  97};
  98