linux/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
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   1One-register-per-pin type device tree based pinctrl driver
   2
   3Required properties:
   4- compatible : "pinctrl-single" or "pinconf-single".
   5  "pinctrl-single" means that pinconf isn't supported.
   6  "pinconf-single" means that generic pinconf is supported.
   7
   8- reg : offset and length of the register set for the mux registers
   9
  10- pinctrl-single,register-width : pinmux register access width in bits
  11
  12- pinctrl-single,function-mask : mask of allowed pinmux function bits
  13  in the pinmux register
  14
  15Optional properties:
  16- pinctrl-single,function-off : function off mode for disabled state if
  17  available and same for all registers; if not specified, disabling of
  18  pin functions is ignored
  19
  20- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
  21  more than one pin, for which "pinctrl-single,function-mask" property specifies
  22 position mask of pin.
  23
  24- pinctrl-single,drive-strength : array of value that are used to configure
  25  drive strength in the pinmux register. They're value of drive strength
  26  current and drive strength mask.
  27
  28                /* drive strength current, mask */
  29                pinctrl-single,power-source = <0x30 0xf0>;
  30
  31- pinctrl-single,bias-pullup : array of value that are used to configure the
  32  input bias pullup in the pinmux register.
  33
  34                /* input, enabled pullup bits, disabled pullup bits, mask */
  35                pinctrl-single,bias-pullup = <0 1 0 1>;
  36
  37- pinctrl-single,bias-pulldown : array of value that are used to configure the
  38  input bias pulldown in the pinmux register.
  39
  40                /* input, enabled pulldown bits, disabled pulldown bits, mask */
  41                pinctrl-single,bias-pulldown = <2 2 0 2>;
  42
  43  * Two bits to control input bias pullup and pulldown: User should use
  44    pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
  45    pullup, and the other one bit means pulldown.
  46  * Three bits to control input bias enable, pullup and pulldown. User should
  47    use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
  48    enable bit should be included in pullup or pulldown bits.
  49  * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
  50    pinctrl-single,bias-disable. Because pinctrl single driver could implement
  51    it by calling pulldown, pullup disabled.
  52
  53- pinctrl-single,input-schmitt : array of value that are used to configure
  54  input schmitt in the pinmux register. In some silicons, there're two input
  55  schmitt value (rising-edge & falling-edge) in the pinmux register.
  56
  57                /* input schmitt value, mask */
  58                pinctrl-single,input-schmitt = <0x30 0x70>;
  59
  60- pinctrl-single,input-schmitt-enable : array of value that are used to
  61  configure input schmitt enable or disable in the pinmux register.
  62
  63                /* input, enable bits, disable bits, mask */
  64                pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
  65
  66- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
  67  range. They're value of subnode phandle, pin base in pinctrl device, pin
  68  number in this range, GPIO function value of this GPIO range.
  69  The number of parameters is depend on #pinctrl-single,gpio-range-cells
  70  property.
  71
  72                /* pin base, nr pins & gpio function */
  73                pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
  74
  75This driver assumes that there is only one register for each pin (unless the
  76pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
  77specified in the pinctrl-bindings.txt document in this directory.
  78
  79The pin configuration nodes for pinctrl-single are specified as pinctrl
  80register offset and value pairs using pinctrl-single,pins. Only the bits
  81specified in pinctrl-single,function-mask are updated. For example, setting
  82a pin for a device could be done with:
  83
  84        pinctrl-single,pins = <0xdc 0x118>;
  85
  86Where 0xdc is the offset from the pinctrl register base address for the
  87device pinctrl register, and 0x118 contains the desired value of the
  88pinctrl register. See the device example and static board pins example
  89below for more information.
  90
  91In case when one register changes more than one pin's mux the
  92pinctrl-single,bits need to be used which takes three parameters:
  93
  94        pinctrl-single,bits = <0xdc 0x18, 0xff>;
  95
  96Where 0xdc is the offset from the pinctrl register base address for the
  97device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
  98be used when applying this change to the register.
  99
 100
 101Optional sub-node: In case some pins could be configured as GPIO in the pinmux
 102register, those pins could be defined as a GPIO range. This sub-node is required
 103by pinctrl-single,gpio-range property.
 104
 105Required properties in sub-node:
 106- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
 107  pinctrl-single,gpio-range property.
 108
 109        range: gpio-range {
 110                #pinctrl-single,gpio-range-cells = <3>;
 111        };
 112
 113
 114Example:
 115
 116/* SoC common file */
 117
 118/* first controller instance for pins in core domain */
 119pmx_core: pinmux@4a100040 {
 120        compatible = "pinctrl-single";
 121        reg = <0x4a100040 0x0196>;
 122        #address-cells = <1>;
 123        #size-cells = <0>;
 124        pinctrl-single,register-width = <16>;
 125        pinctrl-single,function-mask = <0xffff>;
 126};
 127
 128/* second controller instance for pins in wkup domain */
 129pmx_wkup: pinmux@4a31e040 {
 130        compatible = "pinctrl-single";
 131        reg = <0x4a31e040 0x0038>;
 132        #address-cells = <1>;
 133        #size-cells = <0>;
 134        pinctrl-single,register-width = <16>;
 135        pinctrl-single,function-mask = <0xffff>;
 136};
 137
 138control_devconf0: pinmux@48002274 {
 139        compatible = "pinctrl-single";
 140        reg = <0x48002274 4>;   /* Single register */
 141        #address-cells = <1>;
 142        #size-cells = <0>;
 143        pinctrl-single,bit-per-mux;
 144        pinctrl-single,register-width = <32>;
 145        pinctrl-single,function-mask = <0x5F>;
 146};
 147
 148/* third controller instance for pins in gpio domain */
 149pmx_gpio: pinmux@d401e000 {
 150        compatible = "pinconf-single";
 151        reg = <0xd401e000 0x0330>;
 152        #address-cells = <1>;
 153        #size-cells = <1>;
 154        ranges;
 155
 156        pinctrl-single,register-width = <32>;
 157        pinctrl-single,function-mask = <7>;
 158
 159        /* sparse GPIO range could be supported */
 160        pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
 161                                &range 12 1 0 &range 13 29 1
 162                                &range 43 1 0 &range 44 49 1
 163                                &range 94 1 1 &range 96 2 1>;
 164
 165        range: gpio-range {
 166                #pinctrl-single,gpio-range-cells = <3>;
 167        };
 168};
 169
 170
 171/* board specific .dts file */
 172
 173&pmx_core {
 174
 175        /*
 176         * map all board specific static pins enabled by the pinctrl driver
 177         * itself during the boot (or just set them up in the bootloader)
 178         */
 179        pinctrl-names = "default";
 180        pinctrl-0 = <&board_pins>;
 181
 182        board_pins: pinmux_board_pins {
 183                pinctrl-single,pins = <
 184                        0x6c 0xf
 185                        0x6e 0xf
 186                        0x70 0xf
 187                        0x72 0xf
 188                >;
 189        };
 190
 191        uart0_pins: pinmux_uart0_pins {
 192                pinctrl-single,pins = <
 193                        0x208 0         /* UART0_RXD (IOCFG138) */
 194                        0x20c 0         /* UART0_TXD (IOCFG139) */
 195                >;
 196                pinctrl-single,bias-pulldown = <0 2 2>;
 197                pinctrl-single,bias-pullup = <0 1 1>;
 198        };
 199
 200        /* map uart2 pins */
 201        uart2_pins: pinmux_uart2_pins {
 202                pinctrl-single,pins = <
 203                        0xd8 0x118
 204                        0xda 0
 205                        0xdc 0x118
 206                        0xde 0
 207                >;
 208        };
 209};
 210
 211&control_devconf0 {
 212        mcbsp1_pins: pinmux_mcbsp1_pins {
 213                pinctrl-single,bits = <
 214                        0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
 215                >;
 216        };
 217
 218        mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
 219                pinctrl-single,bits = <
 220                        0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
 221                >;
 222        };
 223
 224};
 225
 226&uart1 {
 227       pinctrl-names = "default";
 228       pinctrl-0 = <&uart0_pins>;
 229};
 230
 231&uart2 {
 232       pinctrl-names = "default";
 233       pinctrl-0 = <&uart2_pins>;
 234};
 235