linux/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
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   1* Marvell Armada XP SoC pinctrl driver for mpp
   2
   3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
   4part and usage.
   5
   6Required properties:
   7- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
   8              "marvell,mv78460-pinctrl"
   9
  10This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
  11
  12Available mpp pins/groups and functions:
  13Note: brackets (x) are not part of the mpp name for marvell,function and given
  14only for more detailed description in this document.
  15
  16* Marvell Armada XP (all variants)
  17
  18name          pins     functions
  19================================================================================
  20mpp0          0        gpio, ge0(txclko), lcd(d0)
  21mpp1          1        gpio, ge0(txd0), lcd(d1)
  22mpp2          2        gpio, ge0(txd1), lcd(d2)
  23mpp3          3        gpio, ge0(txd2), lcd(d3)
  24mpp4          4        gpio, ge0(txd3), lcd(d4)
  25mpp5          5        gpio, ge0(txctl), lcd(d5)
  26mpp6          6        gpio, ge0(rxd0), lcd(d6)
  27mpp7          7        gpio, ge0(rxd1), lcd(d7)
  28mpp8          8        gpio, ge0(rxd2), lcd(d8)
  29mpp9          9        gpio, ge0(rxd3), lcd(d9)
  30mpp10         10       gpio, ge0(rxctl), lcd(d10)
  31mpp11         11       gpio, ge0(rxclk), lcd(d11)
  32mpp12         12       gpio, ge0(txd4), ge1(txd0), lcd(d12)
  33mpp13         13       gpio, ge0(txd5), ge1(txd1), lcd(d13)
  34mpp14         14       gpio, ge0(txd6), ge1(txd2), lcd(d15)
  35mpp15         15       gpio, ge0(txd7), ge1(txd3), lcd(d16)
  36mpp16         16       gpio, ge0(txd7), ge1(txd3), lcd(d16)
  37mpp17         17       gpio, ge0(col), ge1(txctl), lcd(d17)
  38mpp18         18       gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
  39mpp19         19       gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
  40mpp20         20       gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
  41mpp21         21       gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
  42mpp22         22       gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
  43mpp23         23       gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
  44mpp24         24       gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
  45mpp25         25       gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
  46mpp26         26       gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
  47mpp27         27       gpio, lcd(e), tdm(dtx), ptp(trig)
  48mpp28         28       gpio, lcd(pwm), tdm(drx), ptp(evreq)
  49mpp29         29       gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
  50mpp30         30       gpio, tdm(int1), sd0(clk)
  51mpp31         31       gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
  52mpp32         32       gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
  53mpp33         33       gpio, tdm(int4), sd0(d1), mem(bat)
  54mpp34         34       gpio, tdm(int5), sd0(d2), sata0(prsnt)
  55mpp35         35       gpio, tdm(int6), sd0(d3), sata1(prsnt)
  56mpp36         36       gpio, spi(mosi)
  57mpp37         37       gpio, spi(miso)
  58mpp38         38       gpio, spi(sck)
  59mpp39         39       gpio, spi(cs0)
  60mpp40         40       gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
  61                       pcie(clkreq0)
  62mpp41         41       gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
  63                       pcie(clkreq1)
  64mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
  65                       vdd(cpu0-pd)
  66mpp43         43       gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
  67                       vdd(cpu2-3-pd){1}
  68mpp44         44       gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
  69                       mem(bat)
  70mpp45         45       gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
  71mpp46         46       gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
  72mpp47         47       gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
  73                       ref(clkout)
  74mpp48         48       gpio, tclk, dev(burst/last)
  75
  76* Marvell Armada XP (mv78260 and mv78460 only)
  77
  78name          pins     functions
  79================================================================================
  80mpp49         49       gpio, dev(we3)
  81mpp50         50       gpio, dev(we2)
  82mpp51         51       gpio, dev(ad16)
  83mpp52         52       gpio, dev(ad17)
  84mpp53         53       gpio, dev(ad18)
  85mpp54         54       gpio, dev(ad19)
  86mpp55         55       gpio, dev(ad20), vdd(cpu0-pd)
  87mpp56         56       gpio, dev(ad21), vdd(cpu1-pd)
  88mpp57         57       gpio, dev(ad22), vdd(cpu2-3-pd){1}
  89mpp58         58       gpio, dev(ad23)
  90mpp59         59       gpio, dev(ad24)
  91mpp60         60       gpio, dev(ad25)
  92mpp61         61       gpio, dev(ad26)
  93mpp62         62       gpio, dev(ad27)
  94mpp63         63       gpio, dev(ad28)
  95mpp64         64       gpio, dev(ad29)
  96mpp65         65       gpio, dev(ad30)
  97mpp66         66       gpio, dev(ad31)
  98
  99Notes:
 100* {1} vdd(cpu2-3-pd) only available on mv78460.
 101