linux/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
<<
>>
Prefs
   1* Atmel AT91 Pinmux Controller
   2
   3The AT91 Pinmux Controller, enables the IC
   4to share one PAD to several functional blocks. The sharing is done by
   5multiplexing the PAD input/output signals. For each PAD there are up to
   68 muxing options (called periph modes). Since different modules require
   7different PAD settings (like pull up, keeper, etc) the contoller controls
   8also the PAD settings parameters.
   9
  10Please refer to pinctrl-bindings.txt in this directory for details of the
  11common pinctrl bindings used by client devices, including the meaning of the
  12phrase "pin configuration node".
  13
  14Atmel AT91 pin configuration node is a node of a group of pins which can be
  15used for a specific device or function. This node represents both mux and config
  16of the pins in that group. The 'pins' selects the function mode(also named pin
  17mode) this pin can work on and the 'config' configures various pad settings
  18such as pull-up, multi drive, etc.
  19
  20Required properties for iomux controller:
  21- compatible: "atmel,at91rm9200-pinctrl"
  22- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
  23  configured in this periph mode. All the periph and bank need to be describe.
  24
  25How to create such array:
  26
  27Each column will represent the possible peripheral of the pinctrl
  28Each line will represent a pio bank
  29
  30Take an example on the 9260
  31Peripheral: 2 ( A and B)
  32Bank: 3 (A, B and C)
  33=>
  34
  35  /*    A         B     */
  36  0xffffffff 0xffc00c3b  /* pioA */
  37  0xffffffff 0x7fff3ccf  /* pioB */
  38  0xffffffff 0x007fffff  /* pioC */
  39
  40For each peripheral/bank we will descibe in a u32 if a pin can can be
  41configured in it by putting 1 to the pin bit (1 << pin)
  42
  43Let's take the pioA on peripheral B
  44From the datasheet Table 10-2.
  45Peripheral B
  46PA0     MCDB0
  47PA1     MCCDB
  48PA2
  49PA3     MCDB3
  50PA4     MCDB2
  51PA5     MCDB1
  52PA6
  53PA7
  54PA8
  55PA9
  56PA10    ETX2
  57PA11    ETX3
  58PA12
  59PA13
  60PA14
  61PA15
  62PA16
  63PA17
  64PA18
  65PA19
  66PA20
  67PA21
  68PA22    ETXER
  69PA23    ETX2
  70PA24    ETX3
  71PA25    ERX2
  72PA26    ERX3
  73PA27    ERXCK
  74PA28    ECRS
  75PA29    ECOL
  76PA30    RXD4
  77PA31    TXD4
  78
  79=> 0xffc00c3b
  80
  81Required properties for pin configuration node:
  82- atmel,pins: 4 integers array, represents a group of pins mux and config
  83  setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
  84  The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
  85  PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
  86
  87Bits used for CONFIG:
  88PULL_UP         (1 << 0): indicate this pin need a pull up.
  89MULTIDRIVE      (1 << 1): indicate this pin need to be configured as multidrive.
  90DEGLITCH        (1 << 2): indicate this pin need deglitch.
  91PULL_DOWN       (1 << 3): indicate this pin need a pull down.
  92DIS_SCHMIT      (1 << 4): indicate this pin need to disable schmit trigger.
  93DEBOUNCE        (1 << 16): indicate this pin need debounce.
  94DEBOUNCE_VAL    (0x3fff << 17): debounce val.
  95
  96NOTE:
  97Some requirements for using atmel,at91rm9200-pinctrl binding:
  981. We have pin function node defined under at91 controller node to represent
  99   what pinmux functions this SoC supports.
 1002. The driver can use the function node's name and pin configuration node's
 101   name describe the pin function and group hierarchy.
 102   For example, Linux at91 pinctrl driver takes the function node's name
 103   as the function name and pin configuration node's name as group name to
 104   create the map table.
 1053. Each pin configuration node should have a phandle, devices can set pins
 106   configurations by referring to the phandle of that pin configuration node.
 1074. The gpio controller must be describe in the pinctrl simple-bus.
 108
 109Examples:
 110
 111pinctrl@fffff400 {
 112        #address-cells = <1>;
 113        #size-cells = <1>;
 114        ranges;
 115        compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
 116        reg = <0xfffff400 0x600>;
 117
 118        atmel,mux-mask = <
 119              /*    A         B     */
 120               0xffffffff 0xffc00c3b  /* pioA */
 121               0xffffffff 0x7fff3ccf  /* pioB */
 122               0xffffffff 0x007fffff  /* pioC */
 123              >;
 124
 125        /* shared pinctrl settings */
 126        dbgu {
 127                pinctrl_dbgu: dbgu-0 {
 128                        atmel,pins =
 129                                <1 14 0x1 0x0   /* PB14 periph A */
 130                                 1 15 0x1 0x1>; /* PB15 periph A with pullup */
 131                };
 132        };
 133};
 134
 135dbgu: serial@fffff200 {
 136        compatible = "atmel,at91sam9260-usart";
 137        reg = <0xfffff200 0x200>;
 138        interrupts = <1 4 7>;
 139        pinctrl-names = "default";
 140        pinctrl-0 = <&pinctrl_dbgu>;
 141        status = "disabled";
 142};
 143