LXR linux/Documentation/devicetree/bindings/pci/designware-pcie.txt

   1* Synopsis Designware PCIe interface
   2
   3Required properties:
   4- compatible: should contain "snps,dw-pcie" to identify the
   5        core, plus an identifier for the specific instance, such
   6        as "samsung,exynos5440-pcie".
   7- reg: base addresses and lengths of the pcie controller,
   8        the phy controller, additional register for the phy controller.
   9- interrupts: interrupt values for level interrupt,
  10        pulse interrupt, special interrupt.
  11- clocks: from common clock binding: handle to pci clock.
  12- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
  13- #address-cells: set to <3>
  14- #size-cells: set to <2>
  15- device_type: set to "pci"
  16- ranges: ranges for the PCI memory and I/O regions
  17- #interrupt-cells: set to <1>
  18- interrupt-map-mask and interrupt-map: standard PCI properties
  19        to define the mapping of the PCIe interface to interrupt
  20        numbers.
  21- reset-gpio: gpio pin number of power good signal
  22
  23Example:
  24
  25SoC specific DT Entry:
  26
  27        pcie@290000 {
  28                compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
  29                reg = <0x290000 0x1000
  30                        0x270000 0x1000
  31                        0x271000 0x40>;
  32                interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
  33                clocks = <&clock 28>, <&clock 27>;
  34                clock-names = "pcie", "pcie_bus";
  35                #address-cells = <3>;
  36                #size-cells = <2>;
  37                device_type = "pci";
  38                ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */
  39                          0x81000000 0 0          0x40001000 0 0x00010000   /* downstream I/O */
  40                          0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
  41                #interrupt-cells = <1>;
  42                interrupt-map-mask = <0 0 0 0>;
  43                interrupt-map = <0x0 0 &gic 53>;
  44        };
  45
  46        pcie@2a0000 {
  47                compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
  48                reg = <0x2a0000 0x1000
  49                        0x272000 0x1000
  50                        0x271040 0x40>;
  51                interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
  52                clocks = <&clock 29>, <&clock 27>;
  53                clock-names = "pcie", "pcie_bus";
  54                #address-cells = <3>;
  55                #size-cells = <2>;
  56                device_type = "pci";
  57                ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */
  58                          0x81000000 0 0          0x60001000 0 0x00010000   /* downstream I/O */
  59                          0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
  60                #interrupt-cells = <1>;
  61                interrupt-map-mask = <0 0 0 0>;
  62                interrupt-map = <0x0 0 &gic 56>;
  63        };
  64
  65Board specific DT Entry:
  66
  67        pcie@290000 {
  68                reset-gpio = <&pin_ctrl 5 0>;
  69        };
  70
  71        pcie@2a0000 {
  72                reset-gpio = <&pin_ctrl 22 0>;
  73        };
  74