linux/Documentation/devicetree/bindings/open-pic.txt
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   1* Open PIC Binding
   2
   3This binding specifies what properties must be available in the device tree
   4representation of an Open PIC compliant interrupt controller.  This binding is
   5based on the binding defined for Open PIC in [1] and is a superset of that
   6binding.
   7
   8Required properties:
   9
  10  NOTE: Many of these descriptions were paraphrased here from [1] to aid
  11        readability.
  12
  13    - compatible: Specifies the compatibility list for the PIC.  The type
  14      shall be <string> and the value shall include "open-pic".
  15
  16    - reg: Specifies the base physical address(s) and size(s) of this
  17      PIC's addressable register space.  The type shall be <prop-encoded-array>.
  18
  19    - interrupt-controller: The presence of this property identifies the node
  20      as an Open PIC.  No property value shall be defined.
  21
  22    - #interrupt-cells: Specifies the number of cells needed to encode an
  23      interrupt source.  The type shall be a <u32> and the value shall be 2.
  24
  25    - #address-cells: Specifies the number of cells needed to encode an
  26      address.  The type shall be <u32> and the value shall be 0.  As such,
  27      'interrupt-map' nodes do not have to specify a parent unit address.
  28
  29Optional properties:
  30
  31    - pic-no-reset: The presence of this property indicates that the PIC
  32      shall not be reset during runtime initialization.  No property value shall
  33      be defined.  The presence of this property also mandates that any
  34      initialization related to interrupt sources shall be limited to sources
  35      explicitly referenced in the device tree.
  36
  37* Interrupt Specifier Definition
  38
  39  Interrupt specifiers consists of 2 cells encoded as
  40  follows:
  41
  42    - <1st-cell>: The interrupt-number that identifies the interrupt source.
  43
  44    - <2nd-cell>: The level-sense information, encoded as follows:
  45                    0 = low-to-high edge triggered
  46                    1 = active low level-sensitive
  47                    2 = active high level-sensitive
  48                    3 = high-to-low edge triggered
  49
  50* Examples
  51
  52Example 1:
  53
  54        /*
  55         * An Open PIC interrupt controller
  56         */
  57        mpic: pic@40000 {
  58                // This is an interrupt controller node.
  59                interrupt-controller;
  60
  61                // No address cells so that 'interrupt-map' nodes which reference
  62                // this Open PIC node do not need a parent address specifier.
  63                #address-cells = <0>;
  64
  65                // Two cells to encode interrupt sources.
  66                #interrupt-cells = <2>;
  67
  68                // Offset address of 0x40000 and size of 0x40000.
  69                reg = <0x40000 0x40000>;
  70
  71                // Compatible with Open PIC.
  72                compatible = "open-pic";
  73
  74                // The PIC shall not be reset.
  75                pic-no-reset;
  76        };
  77
  78Example 2:
  79
  80        /*
  81         * An interrupt generating device that is wired to an Open PIC.
  82         */
  83        serial0: serial@4500 {
  84                // Interrupt source '42' that is active high level-sensitive.
  85                // Note that there are only two cells as specified in the interrupt
  86                // parent's '#interrupt-cells' property.
  87                interrupts = <42 2>;
  88
  89                // The interrupt controller that this device is wired to.
  90                interrupt-parent = <&mpic>;
  91        };
  92
  93* References
  94
  95[1] Power.org (TM) Standard for Embedded Power Architecture (TM) Platform
  96    Requirements (ePAPR), Version 1.0, July 2008.
  97    (http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf)
  98
  99
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