linux/Documentation/devicetree/bindings/net/mdio-mux.txt
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   1Common MDIO bus multiplexer/switch properties.
   2
   3An MDIO bus multiplexer/switch will have several child busses that are
   4numbered uniquely in a device dependent manner.  The nodes for an MDIO
   5bus multiplexer/switch will have one child node for each child bus.
   6
   7Required properties:
   8- mdio-parent-bus : phandle to the parent MDIO bus.
   9- #address-cells = <1>;
  10- #size-cells = <0>;
  11
  12Optional properties:
  13- Other properties specific to the multiplexer/switch hardware.
  14
  15Required properties for child nodes:
  16- #address-cells = <1>;
  17- #size-cells = <0>;
  18- reg : The sub-bus number.
  19
  20
  21Example :
  22
  23        /* The parent MDIO bus. */
  24        smi1: mdio@1180000001900 {
  25                compatible = "cavium,octeon-3860-mdio";
  26                #address-cells = <1>;
  27                #size-cells = <0>;
  28                reg = <0x11800 0x00001900 0x0 0x40>;
  29        };
  30
  31        /*
  32           An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
  33           pair of GPIO lines.  Child busses 2 and 3 populated with 4
  34           PHYs each.
  35         */
  36        mdio-mux {
  37                compatible = "mdio-mux-gpio";
  38                gpios = <&gpio1 3 0>, <&gpio1 4 0>;
  39                mdio-parent-bus = <&smi1>;
  40                #address-cells = <1>;
  41                #size-cells = <0>;
  42
  43                mdio@2 {
  44                        reg = <2>;
  45                        #address-cells = <1>;
  46                        #size-cells = <0>;
  47
  48                        phy11: ethernet-phy@1 {
  49                                reg = <1>;
  50                                compatible = "marvell,88e1149r";
  51                                marvell,reg-init = <3 0x10 0 0x5777>,
  52                                        <3 0x11 0 0x00aa>,
  53                                        <3 0x12 0 0x4105>,
  54                                        <3 0x13 0 0x0a60>;
  55                                interrupt-parent = <&gpio>;
  56                                interrupts = <10 8>; /* Pin 10, active low */
  57                        };
  58                        phy12: ethernet-phy@2 {
  59                                reg = <2>;
  60                                compatible = "marvell,88e1149r";
  61                                marvell,reg-init = <3 0x10 0 0x5777>,
  62                                        <3 0x11 0 0x00aa>,
  63                                        <3 0x12 0 0x4105>,
  64                                        <3 0x13 0 0x0a60>;
  65                                interrupt-parent = <&gpio>;
  66                                interrupts = <10 8>; /* Pin 10, active low */
  67                        };
  68                        phy13: ethernet-phy@3 {
  69                                reg = <3>;
  70                                compatible = "marvell,88e1149r";
  71                                marvell,reg-init = <3 0x10 0 0x5777>,
  72                                        <3 0x11 0 0x00aa>,
  73                                        <3 0x12 0 0x4105>,
  74                                        <3 0x13 0 0x0a60>;
  75                                interrupt-parent = <&gpio>;
  76                                interrupts = <10 8>; /* Pin 10, active low */
  77                        };
  78                        phy14: ethernet-phy@4 {
  79                                reg = <4>;
  80                                compatible = "marvell,88e1149r";
  81                                marvell,reg-init = <3 0x10 0 0x5777>,
  82                                        <3 0x11 0 0x00aa>,
  83                                        <3 0x12 0 0x4105>,
  84                                        <3 0x13 0 0x0a60>;
  85                                interrupt-parent = <&gpio>;
  86                                interrupts = <10 8>; /* Pin 10, active low */
  87                        };
  88                };
  89
  90                mdio@3 {
  91                        reg = <3>;
  92                        #address-cells = <1>;
  93                        #size-cells = <0>;
  94
  95                        phy21: ethernet-phy@1 {
  96                                reg = <1>;
  97                                compatible = "marvell,88e1149r";
  98                                marvell,reg-init = <3 0x10 0 0x5777>,
  99                                        <3 0x11 0 0x00aa>,
 100                                        <3 0x12 0 0x4105>,
 101                                        <3 0x13 0 0x0a60>;
 102                                interrupt-parent = <&gpio>;
 103                                interrupts = <12 8>; /* Pin 12, active low */
 104                        };
 105                        phy22: ethernet-phy@2 {
 106                                reg = <2>;
 107                                compatible = "marvell,88e1149r";
 108                                marvell,reg-init = <3 0x10 0 0x5777>,
 109                                        <3 0x11 0 0x00aa>,
 110                                        <3 0x12 0 0x4105>,
 111                                        <3 0x13 0 0x0a60>;
 112                                interrupt-parent = <&gpio>;
 113                                interrupts = <12 8>; /* Pin 12, active low */
 114                        };
 115                        phy23: ethernet-phy@3 {
 116                                reg = <3>;
 117                                compatible = "marvell,88e1149r";
 118                                marvell,reg-init = <3 0x10 0 0x5777>,
 119                                        <3 0x11 0 0x00aa>,
 120                                        <3 0x12 0 0x4105>,
 121                                        <3 0x13 0 0x0a60>;
 122                                interrupt-parent = <&gpio>;
 123                                interrupts = <12 8>; /* Pin 12, active low */
 124                        };
 125                        phy24: ethernet-phy@4 {
 126                                reg = <4>;
 127                                compatible = "marvell,88e1149r";
 128                                marvell,reg-init = <3 0x10 0 0x5777>,
 129                                        <3 0x11 0 0x00aa>,
 130                                        <3 0x12 0 0x4105>,
 131                                        <3 0x13 0 0x0a60>;
 132                                interrupt-parent = <&gpio>;
 133                                interrupts = <12 8>; /* Pin 12, active low */
 134                        };
 135                };
 136        };
 137