linux/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
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   1=====================================================================
   2SEC 4 Device Tree Binding
   3Copyright (C) 2008-2011 Freescale Semiconductor Inc.
   4
   5 CONTENTS
   6   -Overview
   7   -SEC 4 Node
   8   -Job Ring Node
   9   -Run Time Integrity Check (RTIC) Node
  10   -Run Time Integrity Check (RTIC) Memory Node
  11   -Secure Non-Volatile Storage (SNVS) Node
  12   -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
  13   -Full Example
  14
  15NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
  16Accelerator and Assurance Module (CAAM).
  17
  18=====================================================================
  19Overview
  20
  21DESCRIPTION
  22
  23SEC 4 h/w can process requests from 2 types of sources.
  241. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
  252. Job Rings (HW interface between cores & SEC 4 registers).
  26
  27High Speed Data Path Configuration:
  28
  29HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
  30such as the P4080.  The number of simultaneous dequeues the QI can make is
  31equal to the number of Descriptor Controller (DECO) engines in a particular
  32SEC version.  E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
  33dequeue from 5 subportals simultaneously.
  34
  35Job Ring Data Path Configuration:
  36
  37Each JR is located on a separate 4k page, they may (or may not) be made visible
  38in the memory partition devoted to a particular core.  The P4080 has 4 JRs, so
  39up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
  40
  41=====================================================================
  42SEC 4 Node
  43
  44Description
  45
  46    Node defines the base address of the SEC 4 block.
  47    This block specifies the address range of all global
  48    configuration registers for the SEC 4 block.  It
  49    also receives interrupts from the Run Time Integrity Check
  50    (RTIC) function within the SEC 4 block.
  51
  52PROPERTIES
  53
  54   - compatible
  55      Usage: required
  56      Value type: <string>
  57      Definition: Must include "fsl,sec-v4.0"
  58
  59   - fsl,sec-era
  60      Usage: optional
  61      Value type: <u32>
  62      Definition: A standard property. Define the 'ERA' of the SEC
  63          device.
  64
  65   - #address-cells
  66       Usage: required
  67       Value type: <u32>
  68       Definition: A standard property.  Defines the number of cells
  69           for representing physical addresses in child nodes.
  70
  71   - #size-cells
  72       Usage: required
  73       Value type: <u32>
  74       Definition: A standard property.  Defines the number of cells
  75           for representing the size of physical addresses in
  76           child nodes.
  77
  78   - reg
  79      Usage: required
  80      Value type: <prop-encoded-array>
  81      Definition: A standard property.  Specifies the physical
  82          address and length of the SEC4 configuration registers.
  83          registers
  84
  85   - ranges
  86       Usage: required
  87       Value type: <prop-encoded-array>
  88       Definition: A standard property.  Specifies the physical address
  89           range of the SEC 4.0 register space (-SNVS not included).  A
  90           triplet that includes the child address, parent address, &
  91           length.
  92
  93   - interrupts
  94      Usage: required
  95      Value type: <prop_encoded-array>
  96      Definition:  Specifies the interrupts generated by this
  97           device.  The value of the interrupts property
  98           consists of one interrupt specifier. The format
  99           of the specifier is defined by the binding document
 100           describing the node's interrupt parent.
 101
 102   - interrupt-parent
 103      Usage: (required if interrupt property is defined)
 104      Value type: <phandle>
 105      Definition: A single <phandle> value that points
 106          to the interrupt parent to which the child domain
 107          is being mapped.
 108
 109   Note: All other standard properties (see the ePAPR) are allowed
 110   but are optional.
 111
 112
 113EXAMPLE
 114        crypto@300000 {
 115                compatible = "fsl,sec-v4.0";
 116                fsl,sec-era = <2>;
 117                #address-cells = <1>;
 118                #size-cells = <1>;
 119                reg = <0x300000 0x10000>;
 120                ranges = <0 0x300000 0x10000>;
 121                interrupt-parent = <&mpic>;
 122                interrupts = <92 2>;
 123        };
 124
 125=====================================================================
 126Job Ring (JR) Node
 127
 128    Child of the crypto node defines data processing interface to SEC 4
 129    across the peripheral bus for purposes of processing
 130    cryptographic descriptors. The specified address
 131    range can be made visible to one (or more) cores.
 132    The interrupt defined for this node is controlled within
 133    the address range of this node.
 134
 135  - compatible
 136      Usage: required
 137      Value type: <string>
 138      Definition: Must include "fsl,sec-v4.0-job-ring"
 139
 140  - reg
 141      Usage: required
 142      Value type: <prop-encoded-array>
 143      Definition: Specifies a two JR parameters:  an offset from
 144          the parent physical address and the length the JR registers.
 145
 146   - fsl,liodn
 147       Usage: optional-but-recommended
 148       Value type: <prop-encoded-array>
 149       Definition:
 150           Specifies the LIODN to be used in conjunction with
 151           the ppid-to-liodn table that specifies the PPID to LIODN mapping.
 152           Needed if the PAMU is used.  Value is a 12 bit value
 153           where value is a LIODN ID for this JR. This property is
 154           normally set by boot firmware.
 155
 156   - interrupts
 157      Usage: required
 158      Value type: <prop_encoded-array>
 159      Definition:  Specifies the interrupts generated by this
 160           device.  The value of the interrupts property
 161           consists of one interrupt specifier. The format
 162           of the specifier is defined by the binding document
 163           describing the node's interrupt parent.
 164
 165   - interrupt-parent
 166      Usage: (required if interrupt property is defined)
 167      Value type: <phandle>
 168      Definition: A single <phandle> value that points
 169          to the interrupt parent to which the child domain
 170          is being mapped.
 171
 172EXAMPLE
 173        jr@1000 {
 174                compatible = "fsl,sec-v4.0-job-ring";
 175                reg = <0x1000 0x1000>;
 176                fsl,liodn = <0x081>;
 177                interrupt-parent = <&mpic>;
 178                interrupts = <88 2>;
 179        };
 180
 181
 182=====================================================================
 183Run Time Integrity Check (RTIC) Node
 184
 185  Child node of the crypto node.  Defines a register space that
 186  contains up to 5 sets of addresses and their lengths (sizes) that
 187  will be checked at run time.  After an initial hash result is
 188  calculated, these addresses are checked by HW to monitor any
 189  change.  If any memory is modified, a Security Violation is
 190  triggered (see SNVS definition).
 191
 192
 193  - compatible
 194      Usage: required
 195      Value type: <string>
 196      Definition: Must include "fsl,sec-v4.0-rtic".
 197
 198   - #address-cells
 199       Usage: required
 200       Value type: <u32>
 201       Definition: A standard property.  Defines the number of cells
 202           for representing physical addresses in child nodes.  Must
 203           have a value of 1.
 204
 205   - #size-cells
 206       Usage: required
 207       Value type: <u32>
 208       Definition: A standard property.  Defines the number of cells
 209           for representing the size of physical addresses in
 210           child nodes.  Must have a value of 1.
 211
 212  - reg
 213      Usage: required
 214      Value type: <prop-encoded-array>
 215      Definition: A standard property.  Specifies a two parameters:
 216          an offset from the parent physical address and the length
 217          the SEC4 registers.
 218
 219   - ranges
 220       Usage: required
 221       Value type: <prop-encoded-array>
 222       Definition: A standard property.  Specifies the physical address
 223           range of the SEC 4 register space (-SNVS not included).  A
 224           triplet that includes the child address, parent address, &
 225           length.
 226
 227EXAMPLE
 228        rtic@6000 {
 229                compatible = "fsl,sec-v4.0-rtic";
 230                #address-cells = <1>;
 231                #size-cells = <1>;
 232                reg = <0x6000 0x100>;
 233                ranges = <0x0 0x6100 0xe00>;
 234        };
 235
 236=====================================================================
 237Run Time Integrity Check (RTIC) Memory Node
 238  A child node that defines individual RTIC memory regions that are used to
 239  perform run-time integrity check of memory areas that should not modified.
 240  The node defines a register that contains the memory address &
 241  length (combined) and a second register that contains the hash result
 242  in big endian format.
 243
 244  - compatible
 245      Usage: required
 246      Value type: <string>
 247      Definition: Must include "fsl,sec-v4.0-rtic-memory".
 248
 249  - reg
 250      Usage: required
 251      Value type: <prop-encoded-array>
 252      Definition: A standard property.  Specifies two parameters:
 253          an offset from the parent physical address and the length:
 254
 255          1. The location of the RTIC memory address & length registers.
 256          2. The location RTIC hash result.
 257
 258  - fsl,rtic-region
 259       Usage: optional-but-recommended
 260       Value type: <prop-encoded-array>
 261       Definition:
 262           Specifies the HW address (36 bit address) for this region
 263           followed by the length of the HW partition to be checked;
 264           the address is represented as a 64 bit quantity followed
 265           by a 32 bit length.
 266
 267   - fsl,liodn
 268       Usage: optional-but-recommended
 269       Value type: <prop-encoded-array>
 270       Definition:
 271           Specifies the LIODN to be used in conjunction with
 272           the ppid-to-liodn table that specifies the PPID to LIODN
 273           mapping.  Needed if the PAMU is used.  Value is a 12 bit value
 274           where value is a LIODN ID for this RTIC memory region. This
 275           property is normally set by boot firmware.
 276
 277EXAMPLE
 278        rtic-a@0 {
 279                compatible = "fsl,sec-v4.0-rtic-memory";
 280                reg = <0x00 0x20 0x100 0x80>;
 281                fsl,liodn   = <0x03c>;
 282                fsl,rtic-region  = <0x12345678 0x12345678 0x12345678>;
 283        };
 284
 285=====================================================================
 286Secure Non-Volatile Storage (SNVS) Node
 287
 288    Node defines address range and the associated
 289    interrupt for the SNVS function.  This function
 290    monitors security state information & reports
 291    security violations.
 292
 293  - compatible
 294      Usage: required
 295      Value type: <string>
 296      Definition: Must include "fsl,sec-v4.0-mon".
 297
 298  - reg
 299      Usage: required
 300      Value type: <prop-encoded-array>
 301      Definition: A standard property.  Specifies the physical
 302          address and length of the SEC4 configuration
 303          registers.
 304
 305   - #address-cells
 306       Usage: required
 307       Value type: <u32>
 308       Definition: A standard property.  Defines the number of cells
 309           for representing physical addresses in child nodes.  Must
 310           have a value of 1.
 311
 312   - #size-cells
 313       Usage: required
 314       Value type: <u32>
 315       Definition: A standard property.  Defines the number of cells
 316           for representing the size of physical addresses in
 317           child nodes.  Must have a value of 1.
 318
 319   - ranges
 320       Usage: required
 321       Value type: <prop-encoded-array>
 322       Definition: A standard property.  Specifies the physical address
 323           range of the SNVS register space.  A triplet that includes
 324           the child address, parent address, & length.
 325
 326   - interrupts
 327      Usage: required
 328      Value type: <prop_encoded-array>
 329      Definition:  Specifies the interrupts generated by this
 330           device.  The value of the interrupts property
 331           consists of one interrupt specifier. The format
 332           of the specifier is defined by the binding document
 333           describing the node's interrupt parent.
 334
 335   - interrupt-parent
 336      Usage: (required if interrupt property is defined)
 337      Value type: <phandle>
 338      Definition: A single <phandle> value that points
 339          to the interrupt parent to which the child domain
 340          is being mapped.
 341
 342EXAMPLE
 343        sec_mon@314000 {
 344                compatible = "fsl,sec-v4.0-mon";
 345                reg = <0x314000 0x1000>;
 346                ranges = <0 0x314000 0x1000>;
 347                interrupt-parent = <&mpic>;
 348                interrupts = <93 2>;
 349        };
 350
 351=====================================================================
 352Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
 353
 354  A SNVS child node that defines SNVS LP RTC.
 355
 356  - compatible
 357      Usage: required
 358      Value type: <string>
 359      Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
 360
 361  - reg
 362      Usage: required
 363      Value type: <prop-encoded-array>
 364      Definition: A standard property.  Specifies the physical
 365          address and length of the SNVS LP configuration registers.
 366
 367EXAMPLE
 368        sec_mon_rtc_lp@314000 {
 369                compatible = "fsl,sec-v4.0-mon-rtc-lp";
 370                reg = <0x34 0x58>;
 371        };
 372
 373=====================================================================
 374FULL EXAMPLE
 375
 376        crypto: crypto@300000 {
 377                compatible = "fsl,sec-v4.0";
 378                #address-cells = <1>;
 379                #size-cells = <1>;
 380                reg = <0x300000 0x10000>;
 381                ranges = <0 0x300000 0x10000>;
 382                interrupt-parent = <&mpic>;
 383                interrupts = <92 2>;
 384
 385                sec_jr0: jr@1000 {
 386                        compatible = "fsl,sec-v4.0-job-ring";
 387                        reg = <0x1000 0x1000>;
 388                        interrupt-parent = <&mpic>;
 389                        interrupts = <88 2>;
 390                };
 391
 392                sec_jr1: jr@2000 {
 393                        compatible = "fsl,sec-v4.0-job-ring";
 394                        reg = <0x2000 0x1000>;
 395                        interrupt-parent = <&mpic>;
 396                        interrupts = <89 2>;
 397                };
 398
 399                sec_jr2: jr@3000 {
 400                        compatible = "fsl,sec-v4.0-job-ring";
 401                        reg = <0x3000 0x1000>;
 402                        interrupt-parent = <&mpic>;
 403                        interrupts = <90 2>;
 404                };
 405
 406                sec_jr3: jr@4000 {
 407                        compatible = "fsl,sec-v4.0-job-ring";
 408                        reg = <0x4000 0x1000>;
 409                        interrupt-parent = <&mpic>;
 410                        interrupts = <91 2>;
 411                };
 412
 413                rtic@6000 {
 414                        compatible = "fsl,sec-v4.0-rtic";
 415                        #address-cells = <1>;
 416                        #size-cells = <1>;
 417                        reg = <0x6000 0x100>;
 418                        ranges = <0x0 0x6100 0xe00>;
 419
 420                        rtic_a: rtic-a@0 {
 421                                compatible = "fsl,sec-v4.0-rtic-memory";
 422                                reg = <0x00 0x20 0x100 0x80>;
 423                        };
 424
 425                        rtic_b: rtic-b@20 {
 426                                compatible = "fsl,sec-v4.0-rtic-memory";
 427                                reg = <0x20 0x20 0x200 0x80>;
 428                        };
 429
 430                        rtic_c: rtic-c@40 {
 431                                compatible = "fsl,sec-v4.0-rtic-memory";
 432                                reg = <0x40 0x20 0x300 0x80>;
 433                        };
 434
 435                        rtic_d: rtic-d@60 {
 436                                compatible = "fsl,sec-v4.0-rtic-memory";
 437                                reg = <0x60 0x20 0x500 0x80>;
 438                        };
 439                };
 440        };
 441
 442        sec_mon: sec_mon@314000 {
 443                compatible = "fsl,sec-v4.0-mon";
 444                reg = <0x314000 0x1000>;
 445                ranges = <0 0x314000 0x1000>;
 446                interrupt-parent = <&mpic>;
 447                interrupts = <93 2>;
 448
 449                sec_mon_rtc_lp@34 {
 450                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
 451                        reg = <0x34 0x58>;
 452                };
 453        };
 454
 455=====================================================================
 456