linux/Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt
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   1Generic ARM big LITTLE cpufreq driver's DT glue
   2-----------------------------------------------
   3
   4This is DT specific glue layer for generic cpufreq driver for big LITTLE
   5systems.
   6
   7Both required and optional properties listed below must be defined
   8under node /cpus/cpu@x. Where x is the first cpu inside a cluster.
   9
  10FIXME: Cpus should boot in the order specified in DT and all cpus for a cluster
  11must be present contiguously. Generic DT driver will check only node 'x' for
  12cpu:x.
  13
  14Required properties:
  15- operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt
  16  for details
  17
  18Optional properties:
  19- clock-latency: Specify the possible maximum transition latency for clock,
  20  in unit of nanoseconds.
  21
  22Examples:
  23
  24cpus {
  25        #address-cells = <1>;
  26        #size-cells = <0>;
  27
  28        cpu@0 {
  29                compatible = "arm,cortex-a15";
  30                reg = <0>;
  31                next-level-cache = <&L2>;
  32                operating-points = <
  33                        /* kHz    uV */
  34                        792000  1100000
  35                        396000  950000
  36                        198000  850000
  37                >;
  38                clock-latency = <61036>; /* two CLK32 periods */
  39        };
  40
  41        cpu@1 {
  42                compatible = "arm,cortex-a15";
  43                reg = <1>;
  44                next-level-cache = <&L2>;
  45        };
  46
  47        cpu@100 {
  48                compatible = "arm,cortex-a7";
  49                reg = <100>;
  50                next-level-cache = <&L2>;
  51                operating-points = <
  52                        /* kHz    uV */
  53                        792000  950000
  54                        396000  750000
  55                        198000  450000
  56                >;
  57                clock-latency = <61036>; /* two CLK32 periods */
  58        };
  59
  60        cpu@101 {
  61                compatible = "arm,cortex-a7";
  62                reg = <101>;
  63                next-level-cache = <&L2>;
  64        };
  65};
  66