linux/Documentation/devicetree/bindings/clock/rockchip.txt
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   1Device Tree Clock bindings for arch-rockchip
   2
   3This binding uses the common clock binding[1].
   4
   5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
   6
   7== Gate clocks ==
   8
   9The gate registers form a continuos block which makes the dt node
  10structure a matter of taste, as either all gates can be put into
  11one gate clock spanning all registers or they can be divided into
  12the 10 individual gates containing 16 clocks each.
  13The code supports both approaches.
  14
  15Required properties:
  16- compatible : "rockchip,rk2928-gate-clk"
  17- reg : shall be the control register address(es) for the clock.
  18- #clock-cells : from common clock binding; shall be set to 1
  19- clock-output-names : the corresponding gate names that the clock controls
  20- clocks : should contain the parent clock for each individual gate,
  21  therefore the number of clocks elements should match the number of
  22  clock-output-names
  23
  24Example using multiple gate clocks:
  25
  26                clk_gates0: gate-clk@200000d0 {
  27                        compatible = "rockchip,rk2928-gate-clk";
  28                        reg = <0x200000d0 0x4>;
  29                        clocks = <&dummy>, <&dummy>,
  30                                 <&dummy>, <&dummy>,
  31                                 <&dummy>, <&dummy>,
  32                                 <&dummy>, <&dummy>,
  33                                 <&dummy>, <&dummy>,
  34                                 <&dummy>, <&dummy>,
  35                                 <&dummy>, <&dummy>,
  36                                 <&dummy>, <&dummy>;
  37
  38                        clock-output-names =
  39                                "gate_core_periph", "gate_cpu_gpll",
  40                                "gate_ddrphy", "gate_aclk_cpu",
  41                                "gate_hclk_cpu", "gate_pclk_cpu",
  42                                "gate_atclk_cpu", "gate_i2s0",
  43                                "gate_i2s0_frac", "gate_i2s1",
  44                                "gate_i2s1_frac", "gate_i2s2",
  45                                "gate_i2s2_frac", "gate_spdif",
  46                                "gate_spdif_frac", "gate_testclk";
  47
  48                        #clock-cells = <1>;
  49                };
  50
  51                clk_gates1: gate-clk@200000d4 {
  52                        compatible = "rockchip,rk2928-gate-clk";
  53                        reg = <0x200000d4 0x4>;
  54                        clocks = <&xin24m>, <&xin24m>,
  55                                 <&xin24m>, <&dummy>,
  56                                 <&dummy>, <&xin24m>,
  57                                 <&xin24m>, <&dummy>,
  58                                 <&xin24m>, <&dummy>,
  59                                 <&xin24m>, <&dummy>,
  60                                 <&xin24m>, <&dummy>,
  61                                 <&xin24m>, <&dummy>;
  62
  63                        clock-output-names =
  64                                "gate_timer0", "gate_timer1",
  65                                "gate_timer2", "gate_jtag",
  66                                "gate_aclk_lcdc1_src", "gate_otgphy0",
  67                                "gate_otgphy1", "gate_ddr_gpll",
  68                                "gate_uart0", "gate_frac_uart0",
  69                                "gate_uart1", "gate_frac_uart1",
  70                                "gate_uart2", "gate_frac_uart2",
  71                                "gate_uart3", "gate_frac_uart3";
  72
  73                        #clock-cells = <1>;
  74                };
  75