1* Samsung Exynos5420 Clock Controller 2 3The Exynos5420 clock controller generates and supplies clock to various 4controllers within the Exynos5420 SoC. 5 6Required Properties: 7 8- comptible: should be one of the following. 9 - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC. 10 11- reg: physical base address of the controller and length of memory mapped 12 region. 13 14- #clock-cells: should be 1. 15 16The following is the list of clocks generated by the controller. Each clock is 17assigned an identifier and client nodes use this identifier to specify the 18clock which they consume. 19 20 21 [Core Clocks] 22 23 Clock ID 24 ---------------------------- 25 26 fin_pll 1 27 28 [Clock Gate for Special Clocks] 29 30 Clock ID 31 ---------------------------- 32 sclk_uart0 128 33 sclk_uart1 129 34 sclk_uart2 130 35 sclk_uart3 131 36 sclk_mmc0 132 37 sclk_mmc1 133 38 sclk_mmc2 134 39 sclk_spi0 135 40 sclk_spi1 136 41 sclk_spi2 137 42 sclk_i2s1 138 43 sclk_i2s2 139 44 sclk_pcm1 140 45 sclk_pcm2 141 46 sclk_spdif 142 47 sclk_hdmi 143 48 sclk_pixel 144 49 sclk_dp1 145 50 sclk_mipi1 146 51 sclk_fimd1 147 52 sclk_maudio0 148 53 sclk_maupcm0 149 54 sclk_usbd300 150 55 sclk_usbd301 151 56 sclk_usbphy300 152 57 sclk_usbphy301 153 58 sclk_unipro 154 59 sclk_pwm 155 60 sclk_gscl_wa 156 61 sclk_gscl_wb 157 62 63 [Peripheral Clock Gates] 64 65 Clock ID 66 ---------------------------- 67 68 aclk66_peric 256 69 uart0 257 70 uart1 258 71 uart2 259 72 uart3 260 73 i2c0 261 74 i2c1 262 75 i2c2 263 76 i2c3 264 77 i2c4 265 78 i2c5 266 79 i2c6 267 80 i2c7 268 81 i2c_hdmi 269 82 tsadc 270 83 spi0 271 84 spi1 272 85 spi2 273 86 keyif 274 87 i2s1 275 88 i2s2 276 89 pcm1 277 90 pcm2 278 91 pwm 279 92 spdif 280 93 i2c8 281 94 i2c9 282 95 i2c10 283 96 aclk66_psgen 300 97 chipid 301 98 sysreg 302 99 tzpc0 303 100 tzpc1 304 101 tzpc2 305 102 tzpc3 306 103 tzpc4 307 104 tzpc5 308 105 tzpc6 309 106 tzpc7 310 107 tzpc8 311 108 tzpc9 312 109 hdmi_cec 313 110 seckey 314 111 mct 315 112 wdt 316 113 rtc 317 114 tmu 318 115 tmu_gpu 319 116 pclk66_gpio 330 117 aclk200_fsys2 350 118 mmc0 351 119 mmc1 352 120 mmc2 353 121 sromc 354 122 ufs 355 123 aclk200_fsys 360 124 tsi 361 125 pdma0 362 126 pdma1 363 127 rtic 364 128 usbh20 365 129 usbd300 366 130 usbd301 377 131 aclk400_mscl 380 132 mscl0 381 133 mscl1 382 134 mscl2 383 135 smmu_mscl0 384 136 smmu_mscl1 385 137 smmu_mscl2 386 138 aclk333 400 139 mfc 401 140 smmu_mfcl 402 141 smmu_mfcr 403 142 aclk200_disp1 410 143 dsim1 411 144 dp1 412 145 hdmi 413 146 aclk300_disp1 420 147 fimd1 421 148 smmu_fimd1 422 149 aclk166 430 150 mixer 431 151 aclk266 440 152 rotator 441 153 mdma1 442 154 smmu_rotator 443 155 smmu_mdma1 444 156 aclk300_jpeg 450 157 jpeg 451 158 jpeg2 452 159 smmu_jpeg 453 160 aclk300_gscl 460 161 smmu_gscl0 461 162 smmu_gscl1 462 163 gscl_wa 463 164 gscl_wb 464 165 gscl0 465 166 gscl1 466 167 clk_3aa 467 168 aclk266_g2d 470 169 sss 471 170 slim_sss 472 171 mdma0 473 172 aclk333_g2d 480 173 g2d 481 174 aclk333_432_gscl 490 175 smmu_3aa 491 176 smmu_fimcl0 492 177 smmu_fimcl1 493 178 smmu_fimcl3 494 179 fimc_lite3 495 180 aclk_g3d 500 181 g3d 501 182 183Example 1: An example of a clock controller node is listed below. 184 185 clock: clock-controller@0x10010000 { 186 compatible = "samsung,exynos5420-clock"; 187 reg = <0x10010000 0x30000>; 188 #clock-cells = <1>; 189 }; 190 191Example 2: UART controller node that consumes the clock generated by the clock 192 controller. Refer to the standard clock bindings for information 193 about 'clocks' and 'clock-names' property. 194 195 serial@13820000 { 196 compatible = "samsung,exynos4210-uart"; 197 reg = <0x13820000 0x100>; 198 interrupts = <0 54 0>; 199 clocks = <&clock 259>, <&clock 130>; 200 clock-names = "uart", "clk_uart_baud0"; 201 }; 202