1* Samsung Exynos4 Clock Controller 2 3The Exynos4 clock controller generates and supplies clock to various controllers 4within the Exynos4 SoC. The clock binding described here is applicable to all 5SoC's in the Exynos4 family. 6 7Required Properties: 8 9- comptible: should be one of the following. 10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC. 11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC. 12 13- reg: physical base address of the controller and length of memory mapped 14 region. 15 16- #clock-cells: should be 1. 17 18The following is the list of clocks generated by the controller. Each clock is 19assigned an identifier and client nodes use this identifier to specify the 20clock which they consume. Some of the clocks are available only on a particular 21Exynos4 SoC and this is specified where applicable. 22 23 24 [Core Clocks] 25 26 Clock ID SoC (if specific) 27 ----------------------------------------------- 28 29 xxti 1 30 xusbxti 2 31 fin_pll 3 32 fout_apll 4 33 fout_mpll 5 34 fout_epll 6 35 fout_vpll 7 36 sclk_apll 8 37 sclk_mpll 9 38 sclk_epll 10 39 sclk_vpll 11 40 arm_clk 12 41 aclk200 13 42 aclk100 14 43 aclk160 15 44 aclk133 16 45 mout_mpll_user_t 17 Exynos4x12 46 mout_mpll_user_c 18 Exynos4x12 47 mout_core 19 48 mout_apll 20 49 50 51 [Clock Gate for Special Clocks] 52 53 Clock ID SoC (if specific) 54 ----------------------------------------------- 55 56 sclk_fimc0 128 57 sclk_fimc1 129 58 sclk_fimc2 130 59 sclk_fimc3 131 60 sclk_cam0 132 61 sclk_cam1 133 62 sclk_csis0 134 63 sclk_csis1 135 64 sclk_hdmi 136 65 sclk_mixer 137 66 sclk_dac 138 67 sclk_pixel 139 68 sclk_fimd0 140 69 sclk_mdnie0 141 Exynos4412 70 sclk_mdnie_pwm0 12 142 Exynos4412 71 sclk_mipi0 143 72 sclk_audio0 144 73 sclk_mmc0 145 74 sclk_mmc1 146 75 sclk_mmc2 147 76 sclk_mmc3 148 77 sclk_mmc4 149 78 sclk_sata 150 Exynos4210 79 sclk_uart0 151 80 sclk_uart1 152 81 sclk_uart2 153 82 sclk_uart3 154 83 sclk_uart4 155 84 sclk_audio1 156 85 sclk_audio2 157 86 sclk_spdif 158 87 sclk_spi0 159 88 sclk_spi1 160 89 sclk_spi2 161 90 sclk_slimbus 162 91 sclk_fimd1 163 Exynos4210 92 sclk_mipi1 164 Exynos4210 93 sclk_pcm1 165 94 sclk_pcm2 166 95 sclk_i2s1 167 96 sclk_i2s2 168 97 sclk_mipihsi 169 Exynos4412 98 sclk_mfc 170 99 sclk_pcm0 171 100 sclk_g3d 172 101 sclk_pwm_isp 173 Exynos4x12 102 sclk_spi0_isp 174 Exynos4x12 103 sclk_spi1_isp 175 Exynos4x12 104 sclk_uart_isp 176 Exynos4x12 105 sclk_fimg2d 177 106 107 [Peripheral Clock Gates] 108 109 Clock ID SoC (if specific) 110 ----------------------------------------------- 111 112 fimc0 256 113 fimc1 257 114 fimc2 258 115 fimc3 259 116 csis0 260 117 csis1 261 118 jpeg 262 119 smmu_fimc0 263 120 smmu_fimc1 264 121 smmu_fimc2 265 122 smmu_fimc3 266 123 smmu_jpeg 267 124 vp 268 125 mixer 269 126 tvenc 270 Exynos4210 127 hdmi 271 128 smmu_tv 272 129 mfc 273 130 smmu_mfcl 274 131 smmu_mfcr 275 132 g3d 276 133 g2d 277 134 rotator 278 Exynos4210 135 mdma 279 Exynos4210 136 smmu_g2d 280 Exynos4210 137 smmu_rotator 281 Exynos4210 138 smmu_mdma 282 Exynos4210 139 fimd0 283 140 mie0 284 141 mdnie0 285 Exynos4412 142 dsim0 286 143 smmu_fimd0 287 144 fimd1 288 Exynos4210 145 mie1 289 Exynos4210 146 dsim1 290 Exynos4210 147 smmu_fimd1 291 Exynos4210 148 pdma0 292 149 pdma1 293 150 pcie_phy 294 151 sata_phy 295 Exynos4210 152 tsi 296 153 sdmmc0 297 154 sdmmc1 298 155 sdmmc2 299 156 sdmmc3 300 157 sdmmc4 301 158 sata 302 Exynos4210 159 sromc 303 160 usb_host 304 161 usb_device 305 162 pcie 306 163 onenand 307 164 nfcon 308 165 smmu_pcie 309 166 gps 310 167 smmu_gps 311 168 uart0 312 169 uart1 313 170 uart2 314 171 uart3 315 172 uart4 316 173 i2c0 317 174 i2c1 318 175 i2c2 319 176 i2c3 320 177 i2c4 321 178 i2c5 322 179 i2c6 323 180 i2c7 324 181 i2c_hdmi 325 182 tsadc 326 183 spi0 327 184 spi1 328 185 spi2 329 186 i2s1 330 187 i2s2 331 188 pcm0 332 189 i2s0 333 190 pcm1 334 191 pcm2 335 192 pwm 336 193 slimbus 337 194 spdif 338 195 ac97 339 196 modemif 340 197 chipid 341 198 sysreg 342 199 hdmi_cec 343 200 mct 344 201 wdt 345 202 rtc 346 203 keyif 347 204 audss 348 205 mipi_hsi 349 Exynos4210 206 mdma2 350 Exynos4210 207 pixelasyncm0 351 208 pixelasyncm1 352 209 fimc_lite0 353 Exynos4x12 210 fimc_lite1 354 Exynos4x12 211 ppmuispx 355 Exynos4x12 212 ppmuispmx 356 Exynos4x12 213 fimc_isp 357 Exynos4x12 214 fimc_drc 358 Exynos4x12 215 fimc_fd 359 Exynos4x12 216 mcuisp 360 Exynos4x12 217 gicisp 361 Exynos4x12 218 smmu_isp 362 Exynos4x12 219 smmu_drc 363 Exynos4x12 220 smmu_fd 364 Exynos4x12 221 smmu_lite0 365 Exynos4x12 222 smmu_lite1 366 Exynos4x12 223 mcuctl_isp 367 Exynos4x12 224 mpwm_isp 368 Exynos4x12 225 i2c0_isp 369 Exynos4x12 226 i2c1_isp 370 Exynos4x12 227 mtcadc_isp 371 Exynos4x12 228 pwm_isp 372 Exynos4x12 229 wdt_isp 373 Exynos4x12 230 uart_isp 374 Exynos4x12 231 asyncaxim 375 Exynos4x12 232 smmu_ispcx 376 Exynos4x12 233 spi0_isp 377 Exynos4x12 234 spi1_isp 378 Exynos4x12 235 pwm_isp_sclk 379 Exynos4x12 236 spi0_isp_sclk 380 Exynos4x12 237 spi1_isp_sclk 381 Exynos4x12 238 uart_isp_sclk 382 Exynos4x12 239 240 [Mux Clocks] 241 242 Clock ID SoC (if specific) 243 ----------------------------------------------- 244 245 mout_fimc0 384 246 mout_fimc1 385 247 mout_fimc2 386 248 mout_fimc3 387 249 mout_cam0 388 250 mout_cam1 389 251 mout_csis0 390 252 mout_csis1 391 253 mout_g3d0 392 254 mout_g3d1 393 255 mout_g3d 394 256 aclk400_mcuisp 395 Exynos4x12 257 258 [Div Clocks] 259 260 Clock ID SoC (if specific) 261 ----------------------------------------------- 262 263 div_isp0 450 Exynos4x12 264 div_isp1 451 Exynos4x12 265 div_mcuisp0 452 Exynos4x12 266 div_mcuisp1 453 Exynos4x12 267 div_aclk200 454 Exynos4x12 268 div_aclk400_mcuisp 455 Exynos4x12 269 270 271Example 1: An example of a clock controller node is listed below. 272 273 clock: clock-controller@0x10030000 { 274 compatible = "samsung,exynos4210-clock"; 275 reg = <0x10030000 0x20000>; 276 #clock-cells = <1>; 277 }; 278 279Example 2: UART controller node that consumes the clock generated by the clock 280 controller. Refer to the standard clock bindings for information 281 about 'clocks' and 'clock-names' property. 282 283 serial@13820000 { 284 compatible = "samsung,exynos4210-uart"; 285 reg = <0x13820000 0x100>; 286 interrupts = <0 54 0>; 287 clocks = <&clock 314>, <&clock 153>; 288 clock-names = "uart", "clk_uart_baud0"; 289 }; 290