LXR linux/Documentation/devicetree/bindings/arm/l2cc.txt

   1* ARM L2 Cache Controller
   2
   3ARM cores often have a separate level 2 cache controller. There are various
   4implementations of the L2 cache controller with compatible programming models.
   5The ARM L2 cache representation in the device tree should be done as follows:
   6
   7Required properties:
   8
   9- compatible : should be one of:
  10        "arm,pl310-cache"
  11        "arm,l220-cache"
  12        "arm,l210-cache"
  13        "marvell,aurora-system-cache": Marvell Controller designed to be
  14     compatible with the ARM one, with system cache mode (meaning
  15     maintenance operations on L1 are broadcasted to the L2 and L2
  16     performs the same operation).
  17        "marvell,"aurora-outer-cache: Marvell Controller designed to be
  18         compatible with the ARM one with outer cache mode.
  19        "bcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
  20        offset needs to be added to the address before passing down to the L2
  21        cache controller
  22- cache-unified : Specifies the cache is a unified cache.
  23- cache-level : Should be set to 2 for a level 2 cache.
  24- reg : Physical base address and size of cache controller's memory mapped
  25  registers.
  26
  27Optional properties:
  28
  29- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
  30  read, write and setup latencies. Minimum valid values are 1. Controllers
  31  without setup latency control should use a value of 0.
  32- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
  33  read, write and setup latencies. Controllers without setup latency control
  34  should use 0. Controllers without separate read and write Tag RAM latency
  35  values should only use the first cell.
  36- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
  37- arm,filter-ranges : <start length> Starting address and length of window to
  38  filter. Addresses in the filter window are directed to the M1 port. Other
  39  addresses will go to the M0 port.
  40- interrupts : 1 combined interrupt.
  41- cache-id-part: cache id part number to be used if it is not present
  42  on hardware
  43- wt-override: If present then L2 is forced to Write through mode
  44
  45Example:
  46
  47L2: cache-controller {
  48        compatible = "arm,pl310-cache";
  49        reg = <0xfff12000 0x1000>;
  50        arm,data-latency = <1 1 1>;
  51        arm,tag-latency = <2 2 2>;
  52        arm,filter-ranges = <0x80000000 0x8000000>;
  53        cache-unified;
  54        cache-level = <2>;
  55        interrupts = <45>;
  56};
  57