LXR linux/Documentation/devicetree/bindings/arm/gic.txt

   1* ARM Generic Interrupt Controller
   2
   3ARM SMP cores are often associated with a GIC, providing per processor
   4interrupts (PPI), shared processor interrupts (SPI) and software
   5generated interrupts (SGI).
   6
   7Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
   8Secondary GICs are cascaded into the upward interrupt controller and do not
   9have PPIs or SGIs.
  10
  11Main node required properties:
  12
  13- compatible : should be one of:
  14        "arm,cortex-a15-gic"
  15        "arm,cortex-a9-gic"
  16        "arm,cortex-a7-gic"
  17        "arm,arm11mp-gic"
  18- interrupt-controller : Identifies the node as an interrupt controller
  19- #interrupt-cells : Specifies the number of cells needed to encode an
  20  interrupt source.  The type shall be a <u32> and the value shall be 3.
  21
  22  The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
  23  interrupts.
  24
  25  The 2nd cell contains the interrupt number for the interrupt type.
  26  SPI interrupts are in the range [0-987].  PPI interrupts are in the
  27  range [0-15].
  28
  29  The 3rd cell is the flags, encoded as follows:
  30        bits[3:0] trigger type and level flags.
  31                1 = low-to-high edge triggered
  32                2 = high-to-low edge triggered
  33                4 = active high level-sensitive
  34                8 = active low level-sensitive
  35        bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
  36        the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
  37        the interrupt is wired to that CPU.  Only valid for PPI interrupts.
  38
  39- reg : Specifies base physical address(s) and size of the GIC registers. The
  40  first region is the GIC distributor register base and size. The 2nd region is
  41  the GIC cpu interface register base and size.
  42
  43Optional
  44- interrupts    : Interrupt source of the parent interrupt controller on
  45  secondary GICs, or VGIC maintenance interrupt on primary GIC (see
  46  below).
  47
  48- cpu-offset    : per-cpu offset within the distributor and cpu interface
  49  regions, used when the GIC doesn't have banked registers. The offset is
  50  cpu-offset * cpu-nr.
  51
  52Example:
  53
  54        intc: interrupt-controller@fff11000 {
  55                compatible = "arm,cortex-a9-gic";
  56                #interrupt-cells = <3>;
  57                #address-cells = <1>;
  58                interrupt-controller;
  59                reg = <0xfff11000 0x1000>,
  60                      <0xfff10100 0x100>;
  61        };
  62
  63
  64* GIC virtualization extensions (VGIC)
  65
  66For ARM cores that support the virtualization extensions, additional
  67properties must be described (they only exist if the GIC is the
  68primary interrupt controller).
  69
  70Required properties:
  71
  72- reg : Additional regions specifying the base physical address and
  73  size of the VGIC registers. The first additional region is the GIC
  74  virtual interface control register base and size. The 2nd additional
  75  region is the GIC virtual cpu interface register base and size.
  76
  77- interrupts : VGIC maintenance interrupt.
  78
  79Example:
  80
  81        interrupt-controller@2c001000 {
  82                compatible = "arm,cortex-a15-gic";
  83                #interrupt-cells = <3>;
  84                interrupt-controller;
  85                reg = <0x2c001000 0x1000>,
  86                      <0x2c002000 0x1000>,
  87                      <0x2c004000 0x2000>,
  88                      <0x2c006000 0x2000>;
  89                interrupts = <1 9 0xf04>;
  90        };
  91