linux/Documentation/devicetree/bindings/arm/cci.txt
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   2ARM CCI cache coherent interconnect binding description
   3=======================================================
   4
   5ARM multi-cluster systems maintain intra-cluster coherency through a
   6cache coherent interconnect (CCI) that is capable of monitoring bus
   7transactions and manage coherency, TLB invalidations and memory barriers.
   8
   9It allows snooping and distributed virtual memory message broadcast across
  10clusters, through memory mapped interface, with a global control register
  11space and multiple sets of interface control registers, one per slave
  12interface.
  13
  14Bindings for the CCI node follow the ePAPR standard, available from:
  15
  16www.power.org/documentation/epapr-version-1-1/
  17
  18with the addition of the bindings described in this document which are
  19specific to ARM.
  20
  21* CCI interconnect node
  22
  23        Description: Describes a CCI cache coherent Interconnect component
  24
  25        Node name must be "cci".
  26        Node's parent must be the root node /, and the address space visible
  27        through the CCI interconnect is the same as the one seen from the
  28        root node (ie from CPUs perspective as per DT standard).
  29        Every CCI node has to define the following properties:
  30
  31        - compatible
  32                Usage: required
  33                Value type: <string>
  34                Definition: must be set to
  35                            "arm,cci-400"
  36
  37        - reg
  38                Usage: required
  39                Value type: <prop-encoded-array>
  40                Definition: A standard property. Specifies base physical
  41                            address of CCI control registers common to all
  42                            interfaces.
  43
  44        - ranges:
  45                Usage: required
  46                Value type: <prop-encoded-array>
  47                Definition: A standard property. Follow rules in the ePAPR for
  48                            hierarchical bus addressing. CCI interfaces
  49                            addresses refer to the parent node addressing
  50                            scheme to declare their register bases.
  51
  52        CCI interconnect node can define the following child nodes:
  53
  54        - CCI control interface nodes
  55
  56                Node name must be "slave-if".
  57                Parent node must be CCI interconnect node.
  58
  59                A CCI control interface node must contain the following
  60                properties:
  61
  62                - compatible
  63                        Usage: required
  64                        Value type: <string>
  65                        Definition: must be set to
  66                                    "arm,cci-400-ctrl-if"
  67
  68                - interface-type:
  69                        Usage: required
  70                        Value type: <string>
  71                        Definition: must be set to one of {"ace", "ace-lite"}
  72                                    depending on the interface type the node
  73                                    represents.
  74
  75                - reg:
  76                        Usage: required
  77                        Value type: <prop-encoded-array>
  78                        Definition: the base address and size of the
  79                                    corresponding interface programming
  80                                    registers.
  81
  82* CCI interconnect bus masters
  83
  84        Description: masters in the device tree connected to a CCI port
  85                     (inclusive of CPUs and their cpu nodes).
  86
  87        A CCI interconnect bus master node must contain the following
  88        properties:
  89
  90        - cci-control-port:
  91                Usage: required
  92                Value type: <phandle>
  93                Definition: a phandle containing the CCI control interface node
  94                            the master is connected to.
  95
  96Example:
  97
  98        cpus {
  99                #size-cells = <0>;
 100                #address-cells = <1>;
 101
 102                CPU0: cpu@0 {
 103                        device_type = "cpu";
 104                        compatible = "arm,cortex-a15";
 105                        cci-control-port = <&cci_control1>;
 106                        reg = <0x0>;
 107                };
 108
 109                CPU1: cpu@1 {
 110                        device_type = "cpu";
 111                        compatible = "arm,cortex-a15";
 112                        cci-control-port = <&cci_control1>;
 113                        reg = <0x1>;
 114                };
 115
 116                CPU2: cpu@100 {
 117                        device_type = "cpu";
 118                        compatible = "arm,cortex-a7";
 119                        cci-control-port = <&cci_control2>;
 120                        reg = <0x100>;
 121                };
 122
 123                CPU3: cpu@101 {
 124                        device_type = "cpu";
 125                        compatible = "arm,cortex-a7";
 126                        cci-control-port = <&cci_control2>;
 127                        reg = <0x101>;
 128                };
 129
 130        };
 131
 132        dma0: dma@3000000 {
 133                compatible = "arm,pl330", "arm,primecell";
 134                cci-control-port = <&cci_control0>;
 135                reg = <0x0 0x3000000 0x0 0x1000>;
 136                interrupts = <10>;
 137                #dma-cells = <1>;
 138                #dma-channels = <8>;
 139                #dma-requests = <32>;
 140        };
 141
 142        cci@2c090000 {
 143                compatible = "arm,cci-400";
 144                #address-cells = <1>;
 145                #size-cells = <1>;
 146                reg = <0x0 0x2c090000 0 0x1000>;
 147                ranges = <0x0 0x0 0x2c090000 0x6000>;
 148
 149                cci_control0: slave-if@1000 {
 150                        compatible = "arm,cci-400-ctrl-if";
 151                        interface-type = "ace-lite";
 152                        reg = <0x1000 0x1000>;
 153                };
 154
 155                cci_control1: slave-if@4000 {
 156                        compatible = "arm,cci-400-ctrl-if";
 157                        interface-type = "ace";
 158                        reg = <0x4000 0x1000>;
 159                };
 160
 161                cci_control2: slave-if@5000 {
 162                        compatible = "arm,cci-400-ctrl-if";
 163                        interface-type = "ace";
 164                        reg = <0x5000 0x1000>;
 165                };
 166        };
 167
 168This CCI node corresponds to a CCI component whose control registers sits
 169at address 0x000000002c090000.
 170CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
 171CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
 172CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
 173