linux/drivers/watchdog/coh901327_wdt.c
<<
aluealuealo/spa4.1alospa4 class="lxr_search">aluealuealuealue typ Search.1 aluealo/spa4.1uealoinput typ aue1 odiv id/ /1o/a>ospa4 class="comment">/*o/spa4.1/ /2o/a>ospa4 class="comment"> * coh901327_wdt.co/spa4.1/ /3o/a>ospa4 class="comment"> *o/spa4.1/ /4o/a>ospa4 class="comment"> * Copyright (C) 2008-2009 ST-Ericssn> ABo/spa4.1/ /5o/a>ospa4 class="comment"> * License terms: GNU General Public License (GPL) verson> 2o/spa4.1/ /6o/a>ospa4 class="comment"> * Watchdog driver for the ST-Ericssn> AB COH 901 327 IP coreo/spa4.1/ /7o/a>ospa4 class="comment"> * Author: Linus Walleij <linus.walleij@stericssn>.com>o/spa4.1/ /8o/a>ospa4 class="comment"> */o/spa4.1/ /9o/a>#include <linux/module.ho/a>>1/ a>#include <linux/typ s.ho/a>>1/ 11 a>#include <linux/watchdog.ho/a>>1/ 12 a>#include <linux/interrupt.ho/a>>1/ 13 a>#include <linux/pm.ho/a>>1/ 14 a>#include <linux/platform_device.ho/a>>1/ 15 a>#include <linux/io.ho/a>>1/ 16 a>#include <linux/bitops.ho/a>>1/ 17 a>#include <linux/clk.ho/a>>1/ 18 a>#include <linux/delay.ho/a>>1/ 19o/a>#include <linux/err.ho/a>>1/ 2 a>1/ 21 a>#define/oa href="+code=DRV_NAME" class="sref">DRV_NAME a> ospa4 class="string">"WDOG COH 901 327"o/spa4.1/ 22 a>1/ 23o/a>ospa4 class="comment">/*o/spa4.1/ 24o/a>ospa4 class="comment"> * COH 901 327 register defini v4so/spa4.1/ 25o/a>ospa4 class="comment"> */o/spa4.1/ 26 a>1/ 27o/a>ospa4 class="comment">/* WDOG_FEED Register 32bit (-/W) */o/spa4.1/ 28 a>#define/oa href="+code=U300_WDOG_FR" class="sref">U300_WDOG_FR a> 0x001/ 29 a>#define/oa href="+code=U300_WDOG_FR_FEED_RESTART_TIMER" class="sref">U300_WDOG_FR_FEED_RESTART_TIMER a> 0xFEEDU1/ 30o/a>ospa4 class="comment">/* WDOG_TIMEOUT Register 32bit (R/W) */o/spa4.1/ 31 a>#define/oa href="+code=U300_WDOG_TR" class="sref">U300_WDOG_TR a> 0x041/ 32 a>#define/oa href="+code=U300_WDOG_TR_TIMEOUT_MASK" class="sref">U300_WDOG_TR_TIMEOUT_MASK a> 0x7FFFU1/ 33o/a>ospa4 class="comment">/* WDOG_DISABLE1 Register 32bit (-/W) */o/spa4.1/ 34 a>#define/oa href="+code=U300_WDOG_D1R" class="sref">U300_WDOG_D1R a> 0x081/ 35 a>#define/oa href="+code=U300_WDOG_D1R_DISABLE1_DISABLE_TIMER" class="sref">U300_WDOG_D1R_DISABLE1_DISABLE_TIMER a> 0x2BADU1/ 36o/a>ospa4 class="comment">/* WDOG_DISABLE2 Register 32bit (R/W) */o/spa4.1/ 37 a>#define/oa href="+code=U300_WDOG_D2R" class="sref">U300_WDOG_D2R a> 0x0C1/ 38 a>#define/oa href="+code=U300_WDOG_D2R_DISABLE2_DISABLE_TIMER" class="sref">U300_WDOG_D2R_DISABLE2_DISABLE_TIMER a> 0xCAFEU1/ 39 a>#define/oa href="+code=U300_WDOG_D2R_DISABLE_STATUS_DISABLED" class="sref">U300_WDOG_D2R_DISABLE_STATUS_DISABLED a> 0xDABEU1/ 40 a>#define/oa href="+code=U300_WDOG_D2R_DISABLE_STATUS_ENABLED" class="sref">U300_WDOG_D2R_DISABLE_STATUS_ENABLED a> 0x0000U1/ 41o/a>ospa4 class="comment">/* WDOG_STATUS Register 32bit (R/W) */o/spa4.1/ 42 a>#define/oa href="+code=U300_WDOG_SR" class="sref">U300_WDOG_SR a> 0x101/ 43 a>#define/oa href="+code=U300_WDOG_SR_STATUS_TIMED_OUT" class="sref">U300_WDOG_SR_STATUS_TIMED_OUT a> 0xCFE8U1/ 44 a>#define/oa href="+code=U300_WDOG_SR_STATUS_NORMAL" class="sref">U300_WDOG_SR_STATUS_NORMAL a> 0x0000U1/ 45 a>#define/oa href="+code=U300_WDOG_SR_RESET_STATUS_RESET" class="sref">U300_WDOG_SR_RESET_STATUS_RESET a> 0xE8B4U1/ 46o/a>ospa4 class="comment">/* WDOG_COUNT Register 32bit (R/-) */o/spa4.1/ 47 a>#define/oa href="+code=U300_WDOG_CR" class="sref">U300_WDOG_CR a> 0x141/ 48 a>#define/oa href="+code=U300_WDOG_CR_VALID_IND" class="sref">U300_WDOG_CR_VALID_IND a> 0x8000U1/ 49 a>#define/oa href="+code=U300_WDOG_CR_VALID_STABLE" class="sref">U300_WDOG_CR_VALID_STABLE a> 0x0000U1/ 50 a>#define/oa href="+code=U300_WDOG_CR_COUNT_VALUE_MASK" class="sref">U300_WDOG_CR_COUNT_VALUE_MASK a> 0x7FFFU1/ 51o/a>ospa4 class="comment">/* WDOG_JTAGOVR Register 32bit (R/W) */o/spa4.1/ 52 a>#define/oa href="+code=U300_WDOG_JOR" class="sref">U300_WDOG_JOR a> 0x181/ 53 a>#define/oa href="+code=U300_WDOG_JOR_JTAG_MODE_IND" class="sref">U300_WDOG_JOR_JTAG_MODE_IND a> 0x0002U1/ 54 a>#define/oa href="+code=U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE" class="sref">U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE a> 0x0001U1/ 55o/a>ospa4 class="comment">/* WDOG_RESTART Register 32bit (-/W) */o/spa4.1/ 56 a>#define/oa href="+code=U300_WDOG_RR" class="sref">U300_WDOG_RR a> 0x1C1/ 57 a>#define/oa href="+code=U300_WDOG_RR_RESTART_VALUE_RESUME" class="sref">U300_WDOG_RR_RESTART_VALUE_RESUME a> 0xACEDU1/ 58o/a>ospa4 class="comment">/* WDOG_IRQ_EVENT Register 32bit (R/W) */o/spa4.1/ 59 a>#define/oa href="+code=U300_WDOG_IER" class="sref">U300_WDOG_IER a> 0x201/ 60 a>#define/oa href="+code=U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND" class="sref">U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND a> 0x0001U1/ 61 a>#define/oa href="+code=U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE" class="sref">U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE a> 0x0001U1/ 62o/a>ospa4 class="comment">/* WDOG_IRQ_MASK Register 32bit (R/W) */o/spa4.1/ 63 a>#define/oa href="+code=U300_WDOG_IMR" class="sref">U300_WDOG_IMR a> 0x241/ 64 a>#define/oa href="+code=U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE" class="sref">U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE a> 0x0001U1/ 65o/a>ospa4 class="comment">/* WDOG_IRQ_FORCE Register 32bit (R/W) */o/spa4.1/ 66 a>#define/oa href="+code=U300_WDOG_IFR" class="sref">U300_WDOG_IFR a> 0x281/ 67 a>#define/oa href="+code=U300_WDOG_IFR_WILL_BARK_IRQ_FORCE_ENABLE" class="sref">U300_WDOG_IFR_WILL_BARK_IRQ_FORCE_ENABLE a> 0x0001U1/ 68 a>1/ 69o/a>ospa4 class="comment">/* Default timeout in seconds = 1 minute */o/spa4.1/ 70 a>static unsigned int/oa href="+code=margin" class="sref">margin a> = 60;1/ 71 a>static oa href="+code=resource_size_t" class="sref">resource_size_t a> oa href="+code=phybase" class="sref">phybase a>;1/ 72 a>static oa href="+code=resource_size_t" class="sref">resource_size_t a> oa href="+code=physize" class="sref">physize a>;1/ 73 a>static int/oa href="+code=irq" class="sref">irq a>;1/ 74 a>static void/oa href="+code=__iomem" class="sref">__iomem a> *oa href="+code=virtbase" class="sref">virtbase a>;1/ 75 a>static struct/oa href="+code=device" class="sref">device a> *oa href="+code=parent" class="sref">parent a>;1/ 76 a>1/ 77o/a>ospa4 class="comment">/*o/spa4.1/ 78o/a>ospa4 class="comment"> * The watchdog block is of course always clocked, theo/spa4.1/ 79o/a>ospa4 class="comment"> * clk_enable()/clk_disable() calls are mainly for performing referenceo/spa4.1/ 80o/a>ospa4 class="comment"> * counting higher up in the clock hierarchy.o/spa4.1/ 81o/a>ospa4 class="comment"> */o/spa4.1/ 82 a>static struct/oa href="+code=clk" class="sref">clk a> *oa href="+code=clk" class="sref">clk a>;1/ 83 a>1/ 84o/a>ospa4 class="comment">/*o/spa4.1/ 85o/a>ospa4 class="comment"> * Enabling and disabling func v4s.o/spa4.1/ 86o/a>ospa4 class="comment"> */o/spa4.1/ 87 a>static void/oa href="+code=coh901327_enable" class="sref">coh901327_enable a>(oa href="+code=u16" class="sref">u16 a>/oa href="+code=timeout" class="sref">timeout a>)1/ 88o/a>{1/ 89 a> oa href="+code=u16" class="sref">u16 a>/oa href="+code=val" class="sref">val a>;1/ 90 a> unsigned long oa href="+code=freq" class="sref">freq a>;1/ 91 a> unsigned long oa href="+code=delay_ns" class="sref">delay_ns a>;1/ 92 a>1/ 93 a> oa href="+code=clk_enable" class="sref">clk_enable a>(oa href="+code=clk" class="sref">clk a>);1/ 94 a> ospa4 class="comment">/* Restart timer if it is disabled */o/spa4.1/ 95 a> oa href="+code=val" class="sref">val a> = oa href="+code=readw" class="sref">readw a>(oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_D2R" class="sref">U300_WDOG_D2R a>);1/ 96 a> if (oa href="+code=val" class="sref">val a> == oa href="+code=U300_WDOG_D2R_DISABLE_STATUS_DISABLED" class="sref">U300_WDOG_D2R_DISABLE_STATUS_DISABLED a>)1/ 97 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=U300_WDOG_RR_RESTART_VALUE_RESUME" class="sref">U300_WDOG_RR_RESTART_VALUE_RESUME a>,1/ 98 a> oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_RR" class="sref">U300_WDOG_RR a>);1/ 99 a> ospa4 class="comment">/* Acknowledge any pending interrupt so it doesn't just fire off */o/spa4.1/100 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE" class="sref">U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE a>,1/101 a> oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_IER" class="sref">U300_WDOG_IER a>);1/102 a> ospa4 class="comment">/*o/spa4.1/103o/a>ospa4 class="comment"> * The interrupt is cleared in the 32 kHz clock domain.o/spa4.1/104o/a>ospa4 class="comment"> * Wait 3 32 kHz cycles for it to take effecto/spa4.1/105o/a>ospa4 class="comment"> */o/spa4.1/106 a> oa href="+code=freq" class="sref">freq a> = oa href="+code=clk_get_rate" class="sref">clk_get_rate a>(oa href="+code=clk" class="sref">clk a>);1/107 a> oa href="+code=delay_ns" class="sref">delay_ns a> = oa href="+code=DIV_ROUND_UP" class="sref">DIV_ROUND_UP a>(1000000000, oa href="+code=freq" class="sref">freq a>); ospa4 class="comment">/* Freq to ns and round up */o/spa4.1/108 a> oa href="+code=delay_ns" class="sref">delay_ns a> = 3 * oa href="+code=delay_ns" class="sref">delay_ns a>; ospa4 class="comment">/* Wait 3 cycles */o/spa4.1/109 a> oa href="+code=ndelay" class="sref">ndelay a>(oa href="+code=delay_ns" class="sref">delay_ns a>);1/110 a> ospa4 class="comment">/* Enable the watchdog interrupt */o/spa4.1/111 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE" class="sref">U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE a>, oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_IMR" class="sref">U300_WDOG_IMR a>);1/112 a> ospa4 class="comment">/* Activate the watchdog timer */o/spa4.1/113 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=timeout" class="sref">timeout a>, oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_TR" class="sref">U300_WDOG_TR a>);1/114 a> ospa4 class="comment">/* Start the watchdog timer */o/spa4.1/115 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=U300_WDOG_FR_FEED_RESTART_TIMER" class="sref">U300_WDOG_FR_FEED_RESTART_TIMER a>, oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_FR" class="sref">U300_WDOG_FR a>);1/116 a> ospa4 class="comment">/*o/spa4.1/117o/a>ospa4 class="comment"> * Extra read so that this change propagate in the watchdog.o/spa4.1/118o/a>ospa4 class="comment"> */o/spa4.1/119 a> (void) oa href="+code=readw" class="sref">readw a>(oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_CR" class="sref">U300_WDOG_CR a>);1/120 a> oa href="+code=val" class="sref">val a> = oa href="+code=readw" class="sref">readw a>(oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_D2R" class="sref">U300_WDOG_D2R a>);1/121 a> oa href="+code=clk_disable" class="sref">clk_disable a>(oa href="+code=clk" class="sref">clk a>);1/122 a> if (oa href="+code=val" class="sref">val a> != oa href="+code=U300_WDOG_D2R_DISABLE_STATUS_ENABLED" class="sref">U300_WDOG_D2R_DISABLE_STATUS_ENABLED a>)1/123 a> oa href="+code=dev_err" class="sref">dev_err a>(oa href="+code=parent" class="sref">parent a>,1/124 a> ospa4 class="string">"%s(): watchdog not enabled! D2R %04x\n"o/spa4.,1/125 a> oa href="+code=__func__" class="sref">__func__ a>, oa href="+code=val" class="sref">val a>);1/126 a>}1/127o/a>1/128 a>static void/oa href="+code=coh901327_disable" class="sref">coh901327_disable a>(void)1/129 a>{1/130 a> oa href="+code=u16" class="sref">u16 a>/oa href="+code=val" class="sref">val a>;1/131 a>1/132 a> oa href="+code=clk_enable" class="sref">clk_enable a>(oa href="+code=clk" class="sref">clk a>);1/133 a> ospa4 class="comment">/* Disable the watchdog interrupt if it is ac ve */o/spa4.1/134 a> oa href="+code=writew" class="sref">writew a>(0x0000U, oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_IMR" class="sref">U300_WDOG_IMR a>);1/135 a> ospa4 class="comment">/* If the watchdog is currently enabled, attempt to disable it */o/spa4.1/136 a> oa href="+code=val" class="sref">val a> = oa href="+code=readw" class="sref">readw a>(oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_D2R" class="sref">U300_WDOG_D2R a>);1/137 a> if (oa href="+code=val" class="sref">val a> != oa href="+code=U300_WDOG_D2R_DISABLE_STATUS_DISABLED" class="sref">U300_WDOG_D2R_DISABLE_STATUS_DISABLED a>) {1/138 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=U300_WDOG_D1R_DISABLE1_DISABLE_TIMER" class="sref">U300_WDOG_D1R_DISABLE1_DISABLE_TIMER a>,1/139 a> oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_D1R" class="sref">U300_WDOG_D1R a>);1/140 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=U300_WDOG_D2R_DISABLE2_DISABLE_TIMER" class="sref">U300_WDOG_D2R_DISABLE2_DISABLE_TIMER a>,1/141 a> oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_D2R" class="sref">U300_WDOG_D2R a>);1/142 a> ospa4 class="comment">/* Write this twice (else problems occur) */o/spa4.1/143 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=U300_WDOG_D2R_DISABLE2_DISABLE_TIMER" class="sref">U300_WDOG_D2R_DISABLE2_DISABLE_TIMER a>,1/144 a> oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_D2R" class="sref">U300_WDOG_D2R a>);1/145 a> }1/146 a> oa href="+code=val" class="sref">val a> = oa href="+code=readw" class="sref">readw a>(oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_D2R" class="sref">U300_WDOG_D2R a>);1/147 a> oa href="+code=clk_disable" class="sref">clk_disable a>(oa href="+code=clk" class="sref">clk a>);1/148 a> if (oa href="+code=val" class="sref">val a> != oa href="+code=U300_WDOG_D2R_DISABLE_STATUS_DISABLED" class="sref">U300_WDOG_D2R_DISABLE_STATUS_DISABLED a>)1/149 a> oa href="+code=dev_err" class="sref">dev_err a>(oa href="+code=parent" class="sref">parent a>,1/150 a> ospa4 class="string">"%s(): watchdog not disabled! D2R %04x\n"o/spa4.,1/151 a> oa href="+code=__func__" class="sref">__func__ a>, oa href="+code=val" class="sref">val a>);1/152 a>}1/153 a>1/154 a>static int/oa href="+code=coh901327_start" class="sref">coh901327_start a>(struct/oa href="+code=watchdog_device" class="sref">watchdog_device a> *oa href="+code=wdt_dev" class="sref">wdt_dev a>)1/155o/a>{1/156 a> oa href="+code=coh901327_enable" class="sref">coh901327_enable a>(oa href="+code=wdt_dev" class="sref">wdt_dev a>->oa href="+code=timeout" class="sref">timeout a> */100);1/157 a> return 0;1/158o/a>}1/159 a>1/160 a>static int/oa href="+code=coh901327_stop" class="sref">coh901327_stop a>(struct/oa href="+code=watchdog_device" class="sref">watchdog_device a> *oa href="+code=wdt_dev" class="sref">wdt_dev a>)1/161 a>{1/162 a> oa href="+code=coh901327_disable" class="sref">coh901327_disable a>();1/163 a> return 0;1/164 a>}1/165o/a>1/166 a>static int/oa href="+code=coh901327_ping" class="sref">coh901327_ping a>(struct/oa href="+code=watchdog_device" class="sref">watchdog_device a> *oa href="+code=wdd" class="sref">wdd a>)1/167 a>{1/168 a> oa href="+code=clk_enable" class="sref">clk_enable a>(oa href="+code=clk" class="sref">clk a>);1/169 a> ospa4 class="comment">/* Feed the watchdog */o/spa4.1/170 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=U300_WDOG_FR_FEED_RESTART_TIMER" class="sref">U300_WDOG_FR_FEED_RESTART_TIMER a>,1/171 a> oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_FR" class="sref">U300_WDOG_FR a>);1/172 a> oa href="+code=clk_disable" class="sref">clk_disable a>(oa href="+code=clk" class="sref">clk a>);1/173 a> return 0;1/174 a>}1/175o/a>1/176 a>static int/oa href="+code=coh901327_settimeout" class="sref">coh901327_settimeout a>(struct/oa href="+code=watchdog_device" class="sref">watchdog_device a> *oa href="+code=wdt_dev" class="sref">wdt_dev a>,1/177 a> unsigned int/oa href="+code=time" class="sref">time a>)1/178o/a>{1/179 a> oa href="+code=wdt_dev" class="sref">wdt_dev a>->oa href="+code=timeout" class="sref">timeout a> = oa href="+code=time" class="sref">time a>;1/180 a> oa href="+code=clk_enable" class="sref">clk_enable a>(oa href="+code=clk" class="sref">clk a>);1/181 a> ospa4 class="comment">/* Set new timeout */o/spa4.1/182 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=time" class="sref">time a> */100, oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_TR" class="sref">U300_WDOG_TR a>);1/183 a> ospa4 class="comment">/* Feed the dog */o/spa4.1/184 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=U300_WDOG_FR_FEED_RESTART_TIMER" class="sref">U300_WDOG_FR_FEED_RESTART_TIMER a>,1/185 a> oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_FR" class="sref">U300_WDOG_FR a>);1/186 a> oa href="+code=clk_disable" class="sref">clk_disable a>(oa href="+code=clk" class="sref">clk a>);1/187 a> return 0;1/188o/a>}1/189 a>1/190 a>static unsigned int/oa href="+code=coh901327_gettimeleft" class="sref">coh901327_gettimeleft a>(struct/oa href="+code=watchdog_device" class="sref">watchdog_device a> *oa href="+code=wdt_dev" class="sref">wdt_dev a>)1/191 a>{1/192 a> oa href="+code=u16" class="sref">u16 a>/oa href="+code=val" class="sref">val a>;1/193 a>1/194 a> oa href="+code=clk_enable" class="sref">clk_enable a>(oa href="+code=clk" class="sref">clk a>);1/195 a> ospa4 class="comment">/* Read repeatedly until the is stable! */o/spa4.1/196 a> oa href="+code=val" class="sref">val a> = oa href="+code=readw" class="sref">readw a>(oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_CR" class="sref">U300_WDOG_CR a>);1/197 a> while (oa href="+code=val" class="sref">val a> &/oa href="+code=U300_WDOG_CR_VALID_IND" class="sref">U300_WDOG_CR_VALID_IND a>)1/198 a> oa href="+code=val" class="sref">val a> = oa href="+code=readw" class="sref">readw a>(oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_CR" class="sref">U300_WDOG_CR a>);1/199 a> oa href="+code=val" class="sref">val a> &= oa href="+code=U300_WDOG_CR_COUNT_VALUE_MASK" class="sref">U300_WDOG_CR_COUNT_VALUE_MASK a>;1/200 a> oa href="+code=clk_disable" class="sref">clk_disable a>(oa href="+code=clk" class="sref">clk a>);1/201 a> if (oa href="+code=val" class="sref">val a> != 0)1/202 a> oa href="+code=val" class="sref">val a> /=/100;1/203 a>1/204 a> return oa href="+code=val" class="sref">val a>;1/205o/a>}1/206 a>1/207o/a>ospa4 class="comment">/*o/spa4.1/208o/a>ospa4 class="comment"> * This interrupt occurs/10 ms before the watchdog WILL bark.o/spa4.1/209o/a>ospa4 class="comment"> */o/spa4.1/210 a>static oa href="+code=irqreturn_t" class="sref">irqreturn_t a>/oa href="+code=coh901327_interrupt" class="sref">coh901327_interrupt a>(int/oa href="+code=irq" class="sref">irq a>, void/*oa href="+code=data" class="sref">data a>)1/211 a>{1/212 a> oa href="+code=u16" class="sref">u16 a>/oa href="+code=val" class="sref">val a>;1/213 a>1/214 a> ospa4 class="comment">/*o/spa4.1/215o/a>ospa4 class="comment"> * Ack IRQ? If this occurs/we're FUBAR anyway, soo/spa4.1/216o/a>ospa4 class="comment"> * just acknowledge, disable the interrupt and await the imminent end.o/spa4.1/217o/a>ospa4 class="comment"> * If you at some point/need a host of callbacks to be calledo/spa4.1/218o/a>ospa4 class="comment"> * when the system is about to watchdog-reset, add them here!o/spa4.1/219o/a>ospa4 class="comment"> *o/spa4.1/220o/a>ospa4 class="comment"> * NOTE: on future vers v4s of this IP-block, it will be possible spa4.1/221o/a>ospa4 class="comment"> * to prevent a watchdog reset by feeding the watchdog at this spa4.1/222o/a>ospa4 class="comment"> * point.o/spa4.1/223o/a>ospa4 class="comment"> */o/spa4.1/224 a> oa href="+code=clk_enable" class="sref">clk_enable a>(oa href="+code=clk" class="sref">clk a>);1/225 a> oa href="+code=val" class="sref">val a> = oa href="+code=readw" class="sref">readw a>(oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_IER" class="sref">U300_WDOG_IER a>);1/226 a> if (oa href="+code=val" class="sref">val a> == oa href="+code=U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND" class="sref">U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND a>)1/227 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE" class="sref">U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE a>,1/228 a> oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_IER" class="sref">U300_WDOG_IER a>);1/229 a> oa href="+code=writew" class="sref">writew a>(0x0000U, oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_IMR" class="sref">U300_WDOG_IMR a>);1/230 a> oa href="+code=clk_disable" class="sref">clk_disable a>(oa href="+code=clk" class="sref">clk a>);1/231 a> oa href="+code=dev_crit" class="sref">dev_crit a>(oa href="+code=parent" class="sref">parent a>, ospa4 class="string">"watchdog is barking!\n"o/spa4.);1/232 a> return oa href="+code=IRQ_HANDLED" class="sref">IRQ_HANDLED a>;1/233 a>}1/234 a>1/235 a>static cv4st struct/oa href="+code=watchdog_info" class="sref">watchdog_info a>/oa href="+code=coh901327_ident" class="sref">coh901327_ident a> = {1/236 a> .oa href="+code=op v4s" class="sref">op v4s a> = oa href="+code=WDIOF_CARDRESET" class="sref">WDIOF_CARDRESET a> | oa href="+code=WDIOF_SETTIMEOUT" class="sref">WDIOF_SETTIMEOUT a> | oa href="+code=WDIOF_KEEPALIVEPING" class="sref">WDIOF_KEEPALIVEPING a>,1/237 a> .oa href="+code=identity" class="sref">identity a> = oa href="+code=DRV_NAME" class="sref">DRV_NAME a>,1/238 a>};1/239 a>1/240 a>static struct/oa href="+code=watchdog_ops" class="sref">watchdog_ops a>/oa href="+code=coh901327_ops" class="sref">coh901327_ops a> = {1/241 a> .oa href="+code=owner" class="sref">owner a> = oa href="+code=THIS_MODULE" class="sref">THIS_MODULE a>,1/242 a> .oa href="+code=start" class="sref">start a> = oa href="+code=coh901327_start" class="sref">coh901327_start a>,1/243 a> .oa href="+code=stop" class="sref">stop a> = oa href="+code=coh901327_stop" class="sref">coh901327_stop a>,1/244 a> .oa href="+code=ping" class="sref">ping a> = oa href="+code=coh901327_ping" class="sref">coh901327_ping a>,1/245 a> .oa href="+code=set_timeout" class="sref">set_timeout a> = oa href="+code=coh901327_settimeout" class="sref">coh901327_settimeout a>,1/246 a> .oa href="+code=get_timeleft" class="sref">get_timeleft a> = oa href="+code=coh901327_gettimeleft" class="sref">coh901327_gettimeleft a>,1/247 a>};1/248 a>1/249 a>static struct/oa href="+code=watchdog_device" class="sref">watchdog_device a> oa href="+code=coh901327_wdt" class="sref">coh901327_wdt a> = {1/250 a> .oa href="+code=info" class="sref">info a>/= &oa href="+code=coh901327_ident" class="sref">coh901327_ident a>,1/251 a> .oa href="+code=ops" class="sref">ops a> = &oa href="+code=coh901327_ops" class="sref">coh901327_ops a>,1/252 a> ospa4 class="comment">/*o/spa4.1/253o/a>ospa4 class="comment"> * Max timeout is 327 since the 10ms spa4.1/254o/a>ospa4 class="comment"> * timeout register is max spa4.1/255o/a>ospa4 class="comment"> * 0x7FFF = 327670ms ~= 327s.o/spa4.1/256o/a>ospa4 class="comment"> */o/spa4.1/257 a> .oa href="+code=min_timeout" class="sref">min_timeout a> = 0,1/258 a> .oa href="+code=max_timeout" class="sref">max_timeout a> = 327,1/259 a>};1/260 a>1/261 a>static int/oa href="+code=__exit" class="sref">__exit a> oa href="+code=coh901327_remove" class="sref">coh901327_remove a>(struct/oa href="+code=platform_device" class="sref">platform_device a> *oa href="+code=pdev" class="sref">pdev a>)1/262 a>{1/263 a> oa href="+code=watchdog_unregister_device" class="sref">watchdog_unregister_device a>(&oa href="+code=coh901327_wdt" class="sref">coh901327_wdt a>);1/264 a> oa href="+code=coh901327_disable" class="sref">coh901327_disable a>();1/265 a> oa href="+code=free_irq" class="sref">free_irq a>(oa href="+code=irq" class="sref">irq a>, oa href="+code=pdev" class="sref">pdev a>);1/266 a> oa href="+code=clk_unprepare" class="sref">clk_unprepare a>(oa href="+code=clk" class="sref">clk a>);1/267 a> oa href="+code=clk_put" class="sref">clk_put a>(oa href="+code=clk" class="sref">clk a>);1/268 a> oa href="+code=iounmap" class="sref">iounmap a>(oa href="+code=virtbase" class="sref">virtbase a>);1/269 a> oa href="+code=release_mem_region" class="sref">release_mem_region a>(oa href="+code=phybase" class="sref">phybase a>, oa href="+code=physize" class="sref">physize a>);1/270 a> return 0;1/271 a>}1/272 a>1/273 a>static int/oa href="+code=__init" class="sref">__init a> oa href="+code=coh901327_probe" class="sref">coh901327_probe a>(struct/oa href="+code=platform_device" class="sref">platform_device a> *oa href="+code=pdev" class="sref">pdev a>)1/274 a>{1/275 a> int/oa href="+code=ret" class="sref">ret a>;1/276 a> oa href="+code=u16" class="sref">u16 a>/oa href="+code=val" class="sref">val a>;1/277 a> struct/oa href="+code=resource" class="sref">resource a> *oa href="+code=res" class="sref">res a>;1/278 a>1/279 a> oa href="+code=res" class="sref">res a> = oa href="+code=platform_get_resource" class="sref">platform_get_resource a>(oa href="+code=pdev" class="sref">pdev a>, oa href="+code=IORESOURCE_MEM" class="sref">IORESOURCE_MEM a>, 0);1/280 a> if (!oa href="+code=res" class="sref">res a>)1/281 a> return -oa href="+code=ENOENT" class="sref">ENOENT a>;1/282 a>1/283 a> oa href="+code=parent" class="sref">parent a> = &oa href="+code=pdev" class="sref">pdev a>->oa href="+code=dev" class="sref">dev a>;1/284 a> oa href="+code=physize" class="sref">physize a> = oa href="+code=resource_size" class="sref">resource_size a>(oa href="+code=res" class="sref">res a>);1/285 a> oa href="+code=phybase" class="sref">phybase a> = oa href="+code=res" class="sref">res a>->oa href="+code=start" class="sref">start a>;1/286 a>1/287 a> if (oa href="+code=request_mem_region" class="sref">request_mem_region a>(oa href="+code=phybase" class="sref">phybase a>, oa href="+code=physize" class="sref">physize a>, oa href="+code=DRV_NAME" class="sref">DRV_NAME a>) == oa href="+code=NULL" class="sref">NULL a>) {1/288 a> oa href="+code=ret" class="sref">ret a> = -oa href="+code=EBUSY" class="sref">EBUSY a>;1/289 a> goto oa href="+code=out" class="sref">out a>;1/290 a> }1/291 a>1/292 a> oa href="+code=virtbase" class="sref">virtbase a> = oa href="+code=ioremap" class="sref">ioremap a>(oa href="+code=phybase" class="sref">phybase a>, oa href="+code=physize" class="sref">physize a>);1/293 a> if (!oa href="+code=virtbase" class="sref">virtbase a>) {1/294 a> oa href="+code=ret" class="sref">ret a> = -oa href="+code=ENOMEM" class="sref">ENOMEM a>;1/295 a> goto oa href="+code=out_no_remap" class="sref">out_no_remap a>;1/296 a> }1/297o/a>1/298 a> oa href="+code=clk" class="sref">clk a> = oa href="+code=clk_get" class="sref">clk_get a>(&oa href="+code=pdev" class="sref">pdev a>->oa href="+code=dev" class="sref">dev a>, oa href="+code=NULL" class="sref">NULL a>);1/299 a> if (oa href="+code=IS_ERR" class="sref">IS_ERR a>(oa href="+code=clk" class="sref">clk a>)) {1/300 a> oa href="+code=ret" class="sref">ret a> = oa href="+code=PTR_ERR" class="sref">PTR_ERR a>(oa href="+code=clk" class="sref">clk a>);1/301 a> oa href="+code=dev_err" class="sref">dev_err a>(&oa href="+code=pdev" class="sref">pdev a>->oa href="+code=dev" class="sref">dev a>, ospa4 class="string">"could not get clock\n"o/spa4.);1/302 a> goto oa href="+code=out_no_clk" class="sref">out_no_clk a>;1/303 a> }1/304 a> oa href="+code=ret" class="sref">ret a> = oa href="+code=clk_prepare_enable" class="sref">clk_prepare_enable a>(oa href="+code=clk" class="sref">clk a>);1/305 a> if (oa href="+code=ret" class="sref">ret a>) {1/306 a> oa href="+code=dev_err" class="sref">dev_err a>(&oa href="+code=pdev" class="sref">pdev a>->oa href="+code=dev" class="sref">dev a>, ospa4 class="string">"could not prepare and enable clock\n"o/spa4.);1/307 a> goto oa href="+code=out_no_clk_enable" class="sref">out_no_clk_enable a>;1/308 a> }1/309 a>1/310 a> oa href="+code=val" class="sref">val a> = oa href="+code=readw" class="sref">readw a>(oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_SR" class="sref">U300_WDOG_SR a>);1/311 a> switch (oa href="+code=val" class="sref">val a>) {1/312 a> case/oa href="+code=U300_WDOG_SR_STATUS_TIMED_OUT" class="sref">U300_WDOG_SR_STATUS_TIMED_OUT a>:1/313 a> oa href="+code=dev_info" class="sref">dev_info a>(&oa href="+code=pdev" class="sref">pdev a>->oa href="+code=dev" class="sref">dev a>,1/314 a> ospa4 class="string">"watchdog timed out since last chip reset!\n"o/spa4.);1/315 a> oa href="+code=coh901327_wdt" class="sref">coh901327_wdt a>.oa href="+code=bootstatus" class="sref">bootstatus a> |= oa href="+code=WDIOF_CARDRESET" class="sref">WDIOF_CARDRESET a>;1/316 a> ospa4 class="comment">/* Status will be cleared below */o/spa4.1/317 a> break;1/318 a> case/oa href="+code=U300_WDOG_SR_STATUS_NORMAL" class="sref">U300_WDOG_SR_STATUS_NORMAL a>:1/319 a> oa href="+code=dev_info" class="sref">dev_info a>(&oa href="+code=pdev" class="sref">pdev a>->oa href="+code=dev" class="sref">dev a>,1/320 a> ospa4 class="string">"in normal status, no timeouts have occurred.\n"o/spa4.);1/321 a> break;1/322 a> default:1/323 a> oa href="+code=dev_info" class="sref">dev_info a>(&oa href="+code=pdev" class="sref">pdev a>->oa href="+code=dev" class="sref">dev a>,1/324 a> ospa4 class="string">"contains an illegal status code (%08x)\n"o/spa4., oa href="+code=val" class="sref">val a>);1/325 a> break;1/326 a> }1/327o/a>1/328 a> oa href="+code=val" class="sref">val a> = oa href="+code=readw" class="sref">readw a>(oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_D2R" class="sref">U300_WDOG_D2R a>);1/329 a> switch (oa href="+code=val" class="sref">val a>) {1/330 a> case/oa href="+code=U300_WDOG_D2R_DISABLE_STATUS_DISABLED" class="sref">U300_WDOG_D2R_DISABLE_STATUS_DISABLED a>:1/331 a> oa href="+code=dev_info" class="sref">dev_info a>(&oa href="+code=pdev" class="sref">pdev a>->oa href="+code=dev" class="sref">dev a>, ospa4 class="string">"currently disabled.\n"o/spa4.);1/332 a> break;1/333 a> case/oa href="+code=U300_WDOG_D2R_DISABLE_STATUS_ENABLED" class="sref">U300_WDOG_D2R_DISABLE_STATUS_ENABLED a>:1/334 a> oa href="+code=dev_info" class="sref">dev_info a>(&oa href="+code=pdev" class="sref">pdev a>->oa href="+code=dev" class="sref">dev a>,1/335 a> ospa4 class="string">"currently enabled! (disabling it now)\n"o/spa4.);1/336 a> oa href="+code=coh901327_disable" class="sref">coh901327_disable a>();1/337 a> break;1/338 a> default:1/339 a> oa href="+code=dev_err" class="sref">dev_err a>(&oa href="+code=pdev" class="sref">pdev a>->oa href="+code=dev" class="sref">dev a>,1/340 a> ospa4 class="string">"contains an illegal enable/disable code (%08x)\n"o/spa4.,1/341 a> oa href="+code=val" class="sref">val a>);1/342 a> break;1/343 a> }1/344 a>1/345 a> ospa4 class="comment">/* Reset the watchdog */o/spa4.1/346 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=U300_WDOG_SR_RESET_STATUS_RESET" class="sref">U300_WDOG_SR_RESET_STATUS_RESET a>, oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_SR" class="sref">U300_WDOG_SR a>);1/347o/a>1/348 a> oa href="+code=irq" class="sref">irq a> = oa href="+code=platform_get_irq" class="sref">platform_get_irq a>(oa href="+code=pdev" class="sref">pdev a>, 0);1/349 a> if (oa href="+code=request_irq" class="sref">request_irq a>(oa href="+code=irq" class="sref">irq a>, oa href="+code=coh901327_interrupt" class="sref">coh901327_interrupt a>, 0,1/350 a> oa href="+code=DRV_NAME" class="sref">DRV_NAME a> ospa4 class="string">" Bark"o/spa4., oa href="+code=pdev" class="sref">pdev a>)) {1/351 a> oa href="+code=ret" class="sref">ret a> = -oa href="+code=EIO" class="sref">EIO a>;1/352 a> goto oa href="+code=out_no_irq" class="sref">out_no_irq a>;1/353 a> }1/354 a>1/355 a> oa href="+code=clk_disable" class="sref">clk_disable a>(oa href="+code=clk" class="sref">clk a>);1/356 a>1/357 a> oa href="+code=ret" class="sref">ret a> = oa href="+code=watchdog_init_timeout" class="sref">watchdog_init_timeout a>(&oa href="+code=coh901327_wdt" class="sref">coh901327_wdt a>, oa href="+code=margin" class="sref">margin a>, &oa href="+code=pdev" class="sref">pdev a>->oa href="+code=dev" class="sref">dev a>);1/358 a> if (oa href="+code=ret" class="sref">ret a> < 0)1/359 a> oa href="+code=coh901327_wdt" class="sref">coh901327_wdt a>.oa href="+code=timeout" class="sref">timeout a> = 60;1/360 a>1/361 a> oa href="+code=ret" class="sref">ret a> = oa href="+code=watchdog_register_device" class="sref">watchdog_register_device a>(&oa href="+code=coh901327_wdt" class="sref">coh901327_wdt a>);1/362 a> if (oa href="+code=ret" class="sref">ret a> == 0)1/363 a> oa href="+code=dev_info" class="sref">dev_info a>(&oa href="+code=pdev" class="sref">pdev a>->oa href="+code=dev" class="sref">dev a>,1/364 a> ospa4 class="string">"initialized. timer margin=%d sec\n"o/spa4., oa href="+code=margin" class="sref">margin a>);1/365 a> else1/366 a> goto oa href="+code=out_no_wdog" class="sref">out_no_wdog a>;1/367o/a>1/368 a> return 0;1/369 a>1/370 a>oa href="+code=out_no_wdog" class="sref">out_no_wdog a>:1/371 a> oa href="+code=free_irq" class="sref">free_irq a>(oa href="+code=irq" class="sref">irq a>, oa href="+code=pdev" class="sref">pdev a>);1/372 a>oa href="+code=out_no_irq" class="sref">out_no_irq a>:1/373 a> oa href="+code=clk_disable_unprepare" class="sref">clk_disable_unprepare a>(oa href="+code=clk" class="sref">clk a>);1/374 a>oa href="+code=out_no_clk_enable" class="sref">out_no_clk_enable a>:1/375 a> oa href="+code=clk_put" class="sref">clk_put a>(oa href="+code=clk" class="sref">clk a>);1/376 a>oa href="+code=out_no_clk" class="sref">out_no_clk a>:1/377 a> oa href="+code=iounmap" class="sref">iounmap a>(oa href="+code=virtbase" class="sref">virtbase a>);1/378 a>oa href="+code=out_no_remap" class="sref">out_no_remap a>:1/379 a> oa href="+code=release_mem_region" class="sref">release_mem_region a>(oa href="+code=phybase" class="sref">phybase a>, oa href="+code=SZ_4K" class="sref">SZ_4K a>);1/380 a>oa href="+code=out" class="sref">out a>:1/381 a> return oa href="+code=ret" class="sref">ret a>;1/382 a>}1/383 a>1/384 a>#ifdef oa href="+code=CONFIG_PM" class="sref">CONFIG_PM a>1/385 a>1/386 a>static oa href="+code=u16" class="sref">u16 a>/oa href="+code=wdogenablestore" class="sref">wdogenablestore a>;1/387 a>static oa href="+code=u16" class="sref">u16 a>/oa href="+code=irqmaskstore" class="sref">irqmaskstore a>;1/388 a>1/389 a>static int/oa href="+code=coh901327_suspend" class="sref">coh901327_suspend a>(struct/oa href="+code=platform_device" class="sref">platform_device a> *oa href="+code=pdev" class="sref">pdev a>, oa href="+code=pm_message_t" class="sref">pm_message_t a>/oa href="+code=state" class="sref">state a>)1/390 a>{1/391 a> oa href="+code=irqmaskstore" class="sref">irqmaskstore a> = oa href="+code=readw" class="sref">readw a>(oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_IMR" class="sref">U300_WDOG_IMR a>) & 0x0001U;1/392 a> oa href="+code=wdogenablestore" class="sref">wdogenablestore a> = oa href="+code=readw" class="sref">readw a>(oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_D2R" class="sref">U300_WDOG_D2R a>);1/393 a> ospa4 class="comment">/* If watchdog is on, disable it here and now */o/spa4.1/394 a> if (oa href="+code=wdogenablestore" class="sref">wdogenablestore a> == oa href="+code=U300_WDOG_D2R_DISABLE_STATUS_ENABLED" class="sref">U300_WDOG_D2R_DISABLE_STATUS_ENABLED a>)1/395 a> oa href="+code=coh901327_disable" class="sref">coh901327_disable a>();1/396 a> return 0;1/397o/a>}1/398 a>1/399 a>static int/oa href="+code=coh901327_resume" class="sref">coh901327_resume a>(struct/oa href="+code=platform_device" class="sref">platform_device a> *oa href="+code=pdev" class="sref">pdev a>)1/400 a>{1/401 a> ospa4 class="comment">/* Restore the watchdog interrupt */o/spa4.1/402 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=irqmaskstore" class="sref">irqmaskstore a>, oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_IMR" class="sref">U300_WDOG_IMR a>);1/403 a> if (oa href="+code=wdogenablestore" class="sref">wdogenablestore a> == oa href="+code=U300_WDOG_D2R_DISABLE_STATUS_ENABLED" class="sref">U300_WDOG_D2R_DISABLE_STATUS_ENABLED a>) {1/404 a> ospa4 class="comment">/* Restart the watchdog timer */o/spa4.1/405 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=U300_WDOG_RR_RESTART_VALUE_RESUME" class="sref">U300_WDOG_RR_RESTART_VALUE_RESUME a>,1/406 a> oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_RR" class="sref">U300_WDOG_RR a>);1/407 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=U300_WDOG_FR_FEED_RESTART_TIMER" class="sref">U300_WDOG_FR_FEED_RESTART_TIMER a>,1/408 a> oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_FR" class="sref">U300_WDOG_FR a>);1/409 a> }1/410 a> return 0;1/411 a>}1/412 a>#else1/413 a>#define/oa href="+code=coh901327_suspend" class="sref">coh901327_suspend a> oa href="+code=NULL" class="sref">NULL a>1/414 a>#define/oa href="+code=coh901327_resume" class="sref">coh901327_resume a> oa href="+code=NULL" class="sref">NULL a>1/415 a>#endif1/416 a>1/417 a>ospa4 class="comment">/*o/spa4.1/418 a>ospa4 class="comment"> * Mistreating the watchdog is the only way to perform a software reset of theo/spa4.1/419 a>ospa4 class="comment"> * system on EMP platforms. So we implement this and export a symbol for it.o/spa4.1/420 a>ospa4 class="comment"> */o/spa4.1/421 a>void oa href="+code=coh901327_watchdog_reset" class="sref">coh901327_watchdog_reset a>(void)1/422 a>{1/423 a> ospa4 class="comment">/* Enable even if on JTAG too */o/spa4.1/424 a> oa href="+code=writew" class="sref">writew a>(oa href="+code=U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE" class="sref">U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE a>,1/425 a> oa href="+code=virtbase" class="sref">virtbase a> +/oa href="+code=U300_WDOG_JOR" class="sref">U300_WDOG_JOR a>);1/426 a> ospa4 class="comment">/*o/spa4.1/427 a>ospa4 class="comment"> * Timeout = 5s, we have to wait for the watchdog reset too/spa4.1/428 a>ospa4 class="comment"> * actually take place: the watchdog will be reloaded with theo/spa4.1/429 a>ospa4 class="comment"> * default value immediately, so we HAVE to reboot and get backo/spa4.1/430 a>ospa4 class="comment"> * into the kernel in 30s, or the device will reboot again!o/spa4.1/431 a>ospa4 class="comment"> * The boot loader will typically deactivate the watchdog, so weo/spa4.1/432 a>ospa4 class="comment"> * need time enough for the boot loader to get to the point/ofo/spa4.1/433 a>ospa4 class="comment"> * deactivating the watchdog before it is shut down by it.o/spa4.1/434 a>ospa4 class="comment"> *o/spa4.1/435 a>ospa4 class="comment"> * NOTE: on future versions of the watchdog, this restriction iso/spa4.1/436 a>ospa4 class="comment"> * gone: the watchdog will be reloaded with a default value (1 min)o/spa4.1/437 a>ospa4 class="comment"> * instead of last value, and you ca4 conveniently set the watchdogo/spa4.1/438 a>ospa4 class="comment"> * timeout to 10ms (value = 1) without any problems.o/spa4.1/439 a>ospa4 class="comment"> */o/spa4.1/440 a> oa href="+code=coh901327_enable" class="sref">coh901327_enable a>(500);1/441 a> ospa4 class="comment">/* Return and await doom */o/spa4.1/442 a>}1/443 a>1/444 a>static const struct/oa href="+code=of_device_id" class="sref">of_device_id a> oa href="+code=coh901327_dt_match" class="sref">coh901327_dt_match a>[] = {1/445 a> { .oa href="+code=compatible" class="sref">compatible a> = ospa4 class="string">"stericsson,coh901327"o/spa4. },1/446 a> {},1/447o/a>};1/448 a>1/449 a>static struct/oa href="+code=platform_driver" class="sref">platform_driver a> oa href="+code=coh901327_driver" class="sref">coh901327_driver a> = {1/450 a> .oa href="+code=driver" class="sref">driver a> = {1/451 a> .oa href="+code=owner" class="sref">owner a> = oa href="+code=THIS_MODULE" class="sref">THIS_MODULE a>,1/452 a> .oa href="+code=nam " class="sref">nam a> = ospa4 class="string">"coh901327_wdog"o/spa4.,1/453 a> .oa href="+code=of_match_table" class="sref">of_match_table a> = oa href="+code=coh901327_dt_match" class="sref">coh901327_dt_match a>,1/454 a> },1/455 a> .oa href="+code=remove" class="sref">remove a> = oa href="+code=__exit_p" class="sref">__exit_p a>(oa href="+code=coh901327_remove" class="sref">coh901327_remove a>),1/456 a> .oa href="+code=suspend" class="sref">suspend a> = oa href="+code=coh901327_suspend" class="sref">coh901327_suspend a>,1/457 a> .oa href="+code=resume" class="sref">resume a> = oa href="+code=coh901327_resume" class="sref">coh901327_resume a>,1/458 a>};1/459 a>1/460 a>oa href="+code=module_platform_driver_probe" class="sref">module_platform_driver_probe a>(oa href="+code=coh901327_driver" class="sref">coh901327_driver a>, oa href="+code=coh901327_probe" class="sref">coh901327_probe a>);1/461 a>1/462 a>oa href="+code=MODULE_AUTHOR" class="sref">MODULE_AUTHOR a>(ospa4 class="string">"Linus Walleij <linus.walleij@stericsson.com>"o/spa4.);1/463 a>oa href="+code=MODULE_DESCRIPTION" class="sref">MODULE_DESCRIPTION a>(ospa4 class="string">"COH 901/327 Watchdog"o/spa4.);1/464 a>1/465 a>oa href="+code=module_param" class="sref">module_param a>(oa href="+code=margin" class="sref">margin a>, oa href="+code=uint" class="sref">uint a>, 0);1/466 a>oa href="+code=MODULE_PARM_DESC" class="sref">MODULE_PARM_DESC a>(oa href="+code=margin" class="sref">margin a>, ospa4 class="string">"Watchdog margin in seconds (default 60s)"o/spa4.);1/467o/a>1/468 a>oa href="+code=MODULE_LICE hree"line" na9rDULE_DESCRIPTION a>GPLgin in seconds (default 60s)"o/spa4.);1/46LIASoa href="+code=MODULE_ALIASe"line" na9rDULE_DESCRIPTION a>_probe" :;1"COH 901/327 Watchdog"o/spa4.);1 =/div> claori="sal LXRis the onlbyand y327 Watchhttp://sourc deage.net/projects/lxa">LXRi441 unity=margie verexpWal a>al > lbya327 Watchmailto:lxa@ng">x.no">lxa@ng">x.no=mar. =/div> lxa.ng">x.no kindly hos Wdlbya327 Watchhttp://www.redpill-ng"pro.no">Redpill Lg"pro ASe"li,10msvitimeof Lg"ux" namhdoomme4 clopWaat serevicsng">&qu1995. =/div>