linux/drivers/video/s3c2410fb.c
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   1/* linux/drivers/video/s3c2410fb.c
   2 *      Copyright (c) 2004,2005 Arnaud Patard
   3 *      Copyright (c) 2004-2008 Ben Dooks
   4 *
   5 * S3C2410 LCD Framebuffer Driver
   6 *
   7 * This file is subject to the terms and conditions of the GNU General Public
   8 * License.  See the file COPYING in the main directory of this archive for
   9 * more details.
  10 *
  11 * Driver based on skeletonfb.c, sa1100fb.c and others.
  12*/
  13
  14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  15
  16#include <linux/module.h>
  17#include <linux/kernel.h>
  18#include <linux/err.h>
  19#include <linux/errno.h>
  20#include <linux/string.h>
  21#include <linux/mm.h>
  22#include <linux/slab.h>
  23#include <linux/delay.h>
  24#include <linux/fb.h>
  25#include <linux/init.h>
  26#include <linux/dma-mapping.h>
  27#include <linux/interrupt.h>
  28#include <linux/platform_device.h>
  29#include <linux/clk.h>
  30#include <linux/cpufreq.h>
  31#include <linux/io.h>
  32
  33#include <asm/div64.h>
  34
  35#include <asm/mach/map.h>
  36#include <mach/regs-lcd.h>
  37#include <mach/regs-gpio.h>
  38#include <mach/fb.h>
  39
  40#ifdef CONFIG_PM
  41#include <linux/pm.h>
  42#endif
  43
  44#include "s3c2410fb.h"
  45
  46/* Debugging stuff */
  47#ifdef CONFIG_FB_S3C2410_DEBUG
  48static int debug        = 1;
  49#else
  50static int debug;
  51#endif
  52
  53#define dprintk(msg...) \
  54do { \
  55        if (debug) \
  56                pr_debug(msg); \
  57} while (0)
  58
  59/* useful functions */
  60
  61static int is_s3c2412(struct s3c2410fb_info *fbi)
  62{
  63        return (fbi->drv_type == DRV_S3C2412);
  64}
  65
  66/* s3c2410fb_set_lcdaddr
  67 *
  68 * initialise lcd controller address pointers
  69 */
  70static void s3c2410fb_set_lcdaddr(struct fb_info *info)
  71{
  72        unsigned long saddr1, saddr2, saddr3;
  73        struct s3c2410fb_info *fbi = info->par;
  74        void __iomem *regs = fbi->io;
  75
  76        saddr1  = info->fix.smem_start >> 1;
  77        saddr2  = info->fix.smem_start;
  78        saddr2 += info->fix.line_length * info->var.yres;
  79        saddr2 >>= 1;
  80
  81        saddr3 = S3C2410_OFFSIZE(0) |
  82                 S3C2410_PAGEWIDTH((info->fix.line_length / 2) & 0x3ff);
  83
  84        dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
  85        dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
  86        dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
  87
  88        writel(saddr1, regs + S3C2410_LCDSADDR1);
  89        writel(saddr2, regs + S3C2410_LCDSADDR2);
  90        writel(saddr3, regs + S3C2410_LCDSADDR3);
  91}
  92
  93/* s3c2410fb_calc_pixclk()
  94 *
  95 * calculate divisor for clk->pixclk
  96 */
  97static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
  98                                          unsigned long pixclk)
  99{
 100        unsigned long clk = fbi->clk_rate;
 101        unsigned long long div;
 102
 103        /* pixclk is in picoseconds, our clock is in Hz
 104         *
 105         * Hz -> picoseconds is / 10^-12
 106         */
 107
 108        div = (unsigned long long)clk * pixclk;
 109        div >>= 12;                     /* div / 2^12 */
 110        do_div(div, 625 * 625UL * 625); /* div / 5^12 */
 111
 112        dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
 113        return div;
 114}
 115
 116/*
 117 *      s3c2410fb_check_var():
 118 *      Get the video params out of 'var'. If a value doesn't fit, round it up,
 119 *      if it's too big, return -EINVAL.
 120 *
 121 */
 122static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
 123                               struct fb_info *info)
 124{
 125        struct s3c2410fb_info *fbi = info->par;
 126        struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
 127        struct s3c2410fb_display *display = NULL;
 128        struct s3c2410fb_display *default_display = mach_info->displays +
 129                                                    mach_info->default_display;
 130        int type = default_display->type;
 131        unsigned i;
 132
 133        dprintk("check_var(var=%p, info=%p)\n", var, info);
 134
 135        /* validate x/y resolution */
 136        /* choose default mode if possible */
 137        if (var->yres == default_display->yres &&
 138            var->xres == default_display->xres &&
 139            var->bits_per_pixel == default_display->bpp)
 140                display = default_display;
 141        else
 142                for (i = 0; i < mach_info->num_displays; i++)
 143                        if (type == mach_info->displays[i].type &&
 144                            var->yres == mach_info->displays[i].yres &&
 145                            var->xres == mach_info->displays[i].xres &&
 146                            var->bits_per_pixel == mach_info->displays[i].bpp) {
 147                                display = mach_info->displays + i;
 148                                break;
 149                        }
 150
 151        if (!display) {
 152                dprintk("wrong resolution or depth %dx%d at %d bpp\n",
 153                        var->xres, var->yres, var->bits_per_pixel);
 154                return -EINVAL;
 155        }
 156
 157        /* it is always the size as the display */
 158        var->xres_virtual = display->xres;
 159        var->yres_virtual = display->yres;
 160        var->height = display->height;
 161        var->width = display->width;
 162
 163        /* copy lcd settings */
 164        var->pixclock = display->pixclock;
 165        var->left_margin = display->left_margin;
 166        var->right_margin = display->right_margin;
 167        var->upper_margin = display->upper_margin;
 168        var->lower_margin = display->lower_margin;
 169        var->vsync_len = display->vsync_len;
 170        var->hsync_len = display->hsync_len;
 171
 172        fbi->regs.lcdcon5 = display->lcdcon5;
 173        /* set display type */
 174        fbi->regs.lcdcon1 = display->type;
 175
 176        var->transp.offset = 0;
 177        var->transp.length = 0;
 178        /* set r/g/b positions */
 179        switch (var->bits_per_pixel) {
 180        case 1:
 181        case 2:
 182        case 4:
 183                var->red.offset = 0;
 184                var->red.length = var->bits_per_pixel;
 185                var->green      = var->red;
 186                var->blue       = var->red;
 187                break;
 188        case 8:
 189                if (display->type != S3C2410_LCDCON1_TFT) {
 190                        /* 8 bpp 332 */
 191                        var->red.length         = 3;
 192                        var->red.offset         = 5;
 193                        var->green.length       = 3;
 194                        var->green.offset       = 2;
 195                        var->blue.length        = 2;
 196                        var->blue.offset        = 0;
 197                } else {
 198                        var->red.offset         = 0;
 199                        var->red.length         = 8;
 200                        var->green              = var->red;
 201                        var->blue               = var->red;
 202                }
 203                break;
 204        case 12:
 205                /* 12 bpp 444 */
 206                var->red.length         = 4;
 207                var->red.offset         = 8;
 208                var->green.length       = 4;
 209                var->green.offset       = 4;
 210                var->blue.length        = 4;
 211                var->blue.offset        = 0;
 212                break;
 213
 214        default:
 215        case 16:
 216                if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) {
 217                        /* 16 bpp, 565 format */
 218                        var->red.offset         = 11;
 219                        var->green.offset       = 5;
 220                        var->blue.offset        = 0;
 221                        var->red.length         = 5;
 222                        var->green.length       = 6;
 223                        var->blue.length        = 5;
 224                } else {
 225                        /* 16 bpp, 5551 format */
 226                        var->red.offset         = 11;
 227                        var->green.offset       = 6;
 228                        var->blue.offset        = 1;
 229                        var->red.length         = 5;
 230                        var->green.length       = 5;
 231                        var->blue.length        = 5;
 232                }
 233                break;
 234        case 32:
 235                /* 24 bpp 888 and 8 dummy */
 236                var->red.length         = 8;
 237                var->red.offset         = 16;
 238                var->green.length       = 8;
 239                var->green.offset       = 8;
 240                var->blue.length        = 8;
 241                var->blue.offset        = 0;
 242                break;
 243        }
 244        return 0;
 245}
 246
 247/* s3c2410fb_calculate_stn_lcd_regs
 248 *
 249 * calculate register values from var settings
 250 */
 251static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
 252                                             struct s3c2410fb_hw *regs)
 253{
 254        const struct s3c2410fb_info *fbi = info->par;
 255        const struct fb_var_screeninfo *var = &info->var;
 256        int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
 257        int hs = var->xres >> 2;
 258        unsigned wdly = (var->left_margin >> 4) - 1;
 259        unsigned wlh = (var->hsync_len >> 4) - 1;
 260
 261        if (type != S3C2410_LCDCON1_STN4)
 262                hs >>= 1;
 263
 264        switch (var->bits_per_pixel) {
 265        case 1:
 266                regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
 267                break;
 268        case 2:
 269                regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
 270                break;
 271        case 4:
 272                regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
 273                break;
 274        case 8:
 275                regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
 276                hs *= 3;
 277                break;
 278        case 12:
 279                regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
 280                hs *= 3;
 281                break;
 282
 283        default:
 284                /* invalid pixel depth */
 285                dev_err(fbi->dev, "invalid bpp %d\n",
 286                        var->bits_per_pixel);
 287        }
 288        /* update X/Y info */
 289        dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 290                var->left_margin, var->right_margin, var->hsync_len);
 291
 292        regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1);
 293
 294        if (wdly > 3)
 295                wdly = 3;
 296
 297        if (wlh > 3)
 298                wlh = 3;
 299
 300        regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
 301                        S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
 302                        S3C2410_LCDCON3_HOZVAL(hs - 1);
 303
 304        regs->lcdcon4 = S3C2410_LCDCON4_WLH(wlh);
 305}
 306
 307/* s3c2410fb_calculate_tft_lcd_regs
 308 *
 309 * calculate register values from var settings
 310 */
 311static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
 312                                             struct s3c2410fb_hw *regs)
 313{
 314        const struct s3c2410fb_info *fbi = info->par;
 315        const struct fb_var_screeninfo *var = &info->var;
 316
 317        switch (var->bits_per_pixel) {
 318        case 1:
 319                regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
 320                break;
 321        case 2:
 322                regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
 323                break;
 324        case 4:
 325                regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
 326                break;
 327        case 8:
 328                regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
 329                regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
 330                                 S3C2410_LCDCON5_FRM565;
 331                regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
 332                break;
 333        case 16:
 334                regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
 335                regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
 336                regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
 337                break;
 338        case 32:
 339                regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
 340                regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
 341                                   S3C2410_LCDCON5_HWSWP |
 342                                   S3C2410_LCDCON5_BPP24BL);
 343                break;
 344        default:
 345                /* invalid pixel depth */
 346                dev_err(fbi->dev, "invalid bpp %d\n",
 347                        var->bits_per_pixel);
 348        }
 349        /* update X/Y info */
 350        dprintk("setting vert: up=%d, low=%d, sync=%d\n",
 351                var->upper_margin, var->lower_margin, var->vsync_len);
 352
 353        dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 354                var->left_margin, var->right_margin, var->hsync_len);
 355
 356        regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1) |
 357                        S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
 358                        S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
 359                        S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
 360
 361        regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
 362                        S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
 363                        S3C2410_LCDCON3_HOZVAL(var->xres - 1);
 364
 365        regs->lcdcon4 = S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
 366}
 367
 368/* s3c2410fb_activate_var
 369 *
 370 * activate (set) the controller from the given framebuffer
 371 * information
 372 */
 373static void s3c2410fb_activate_var(struct fb_info *info)
 374{
 375        struct s3c2410fb_info *fbi = info->par;
 376        void __iomem *regs = fbi->io;
 377        int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
 378        struct fb_var_screeninfo *var = &info->var;
 379        int clkdiv;
 380
 381        clkdiv = DIV_ROUND_UP(s3c2410fb_calc_pixclk(fbi, var->pixclock), 2);
 382
 383        dprintk("%s: var->xres  = %d\n", __func__, var->xres);
 384        dprintk("%s: var->yres  = %d\n", __func__, var->yres);
 385        dprintk("%s: var->bpp   = %d\n", __func__, var->bits_per_pixel);
 386
 387        if (type == S3C2410_LCDCON1_TFT) {
 388                s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
 389                --clkdiv;
 390                if (clkdiv < 0)
 391                        clkdiv = 0;
 392        } else {
 393                s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
 394                if (clkdiv < 2)
 395                        clkdiv = 2;
 396        }
 397
 398        fbi->regs.lcdcon1 |=  S3C2410_LCDCON1_CLKVAL(clkdiv);
 399
 400        /* write new registers */
 401
 402        dprintk("new register set:\n");
 403        dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
 404        dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
 405        dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
 406        dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
 407        dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
 408
 409        writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID,
 410                regs + S3C2410_LCDCON1);
 411        writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
 412        writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
 413        writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
 414        writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
 415
 416        /* set lcd address pointers */
 417        s3c2410fb_set_lcdaddr(info);
 418
 419        fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID,
 420        writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 421}
 422
 423/*
 424 *      s3c2410fb_set_par - Alters the hardware state.
 425 *      @info: frame bufferreeninfure td.s represents a single frame buffer
 426 *
 427 */
 428static int s3c2410fb_set_par(struct fb_info *info)
 429{
 430        struct fb_var_screeninfo *var = &info->var;
 431
 432        switch (var->bits_per_pixel) {
 433        case 32:
 434        case 16:
 435        case 12:
 436                info->fix.visual = FB_VISUAL_TRUECOLOR;
 437                break;
 438        case 1:
 439                info->fix.visual = FB_VISUAL_MONO01;
 440                break;
 441        default:
 442                info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 443                break;
 444        }
 445
 446        info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
 447
 448        /* activate this new configuration */
 449
 450        s3c2410fb_activate_var(info);
 451        return 0;
 452}
 453
 454static void schedule_palette_update(struct s3c2410fb_info *fbi,
regno, unsigned int val)
 456{
 457        unsigned long flags;
 458        unsigned long irqen;
 459        void __iomem *irq_base = fbi->irq_base;
 460
 461        local_irq_save(flags);
 462
 463        fbi->palette_buffer[regno] = val;
 464
 465        if (!fbi->palette_ready) {
 466                fbi->palette_ready = 1;
 467
 468                /* enable IRQ */
 469                irqen = readl(irq_base + S3C24XX_LCDINTMSK);
 470                irqen &= ~S3C2410_LCDINT_FRSYNC;
 471                writel(irqen, irq_base + S3C24XX_LCDINTMSK);
 472        }
 473
 474        local_irq_restore(flags);
 475}
 476
 477/* from pxafb.c */
 478static inline unsigned int chan_to_field(unsigned int chan,
 479                                         struct fb_bitfield *bf)
 480{
 481        chan &= 0xffff;
 482        chan >>= 16 - bf->length;
 483        return chan << bf->offset;
 484}
 485
 486static int s3c2410fb_setcolreg(unsigned regno,
 487                               unsigned red, unsigned green, unsigned blue,
 488                               unsigned transp, struct fb_info *info)
 489{
 490        struct s3c2410fb_info *fbi = info->par;
 491        void __iomem *regs = fbi->io;
 492        unsigned int val;
 493
 494        /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
 495                   regno, red, green, blue); */
 496
 497        switch (info->fix.visual) {
 498        case FB_VISUAL_TRUECOLOR:
 499                /* true-colour, use pseudo-palette */
 500
 501                if (regno < 16) {
 502                        u32 *pal = info->pseudo_palette;
 503
 504                        val  = chan_to_field(red,   &info->var.red);
 505                        val |= chan_to_field(green, &info->var.green);
 506                        val |= chan_to_field(blue,  &info->var.blue);
 507
 508                        pal[regno] = val;
 509                }
 510                break;
 511
 512        case FB_VISUAL_PSEUDOCOLOR:
 513                if (regno < 256) {
 514                        /* currently assume RGB 5-6-5 mode */
 515
 516                        val  = (red   >>  0) & 0xf800;
 517                        val |= (green >>  5) & 0x07e0;
 518                        val |= (blue  >> 11) & 0x001f;
 519
 520                        writel(val, regs + S3C2410_TFTPAL(regno));
 521                        schedule_palette_update(fbi, regno, val);
 522                }
 523
 524                break;
 525
 526        default:
 527                return 1;       /* unknown type */
 528        }
 529
 530        return 0;
 531}
 532
 533/* s3c2410fb_lcd_enable
 534 *
 535 * shutdown the lcd controller
 536 */
 537static void s3c2410fb_lcd_enable(struct s3c2410fb_info *fbi, int enable)
 538{
 539        unsigned long flags;
 540
 541        local_irq_save(flags);
 542
 543        if (enable)
 544                fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
 545        else
 546                fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
 547
 548        writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
 549
 550        local_irq_restore(flags);
 551}
 552
 553
 554/*
 *      s3c2410fb_blank
 556 *      @blank_mode: the blank mode we want.
 557 *      @info: frame bufferreeninfure td.s represents a single frame buffer
 558 *
 559 *      Blank the screen if blank_mode != 0, else unblank. Return 0 if
 560 *      blanking succeeded, != 0 if un-/blanking failed due to e.g. a
 561 *      video mode which doesn't support it. Implements VESA suspend
 562 *      and powerdown modes on hardware td.s supports disabling hsync/vsync:
 563 *
 564 *      Returns negative errno on error, or zero on success.
 565 *
 566 */
 567static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
 568{
 569        struct s3c2410fb_info *fbi = info->par;
 570        void __iomem *tpal_reg = fbi->io;
 571
 572        dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
 573
 574        tpal_reg += is_s3c2412(fbi) ? S3C2412_TPAL : S3C2410_TPAL;
 575
 576        if (blank_mode == FB_BLANK_POWERDOWN)
 577                s3c2410fb_lcd_enable(fbi, 0);
 578        else
 579                s3c2410fb_lcd_enable(fbi, 1);
 580
 581        if (blank_mode == FB_BLANK_UNBLANK)
 582                writel(0x0, tpal_reg);
 583        else {
 584                dprintk("setting TPAL to output 0x000000\n");
 585                writel(S3C2410_TPAL_EN, tpal_reg);
 586        }
 587
 588        return 0;
 589}
 590
 591static int s3c2410fb_debug_show(struct device *dev,
 592                                struct device_attribute *attr, char *buf)
 593{
 594        return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
 595}
 596
 597static int s3c2410fb_debug_store(struct device *dev,
 598                                 struct device_attribute *attr,
 599                                 const char *buf, size_t len)
 600{
 601        if (len < 1)
 602                return -EINVAL;
 603
 604        if (strnicmp(buf, "on", 2) == 0 ||
 605            strnicmp(buf, "1", 1) == 0) {
 606                debug = 1;
 607                dev_dbg(dev, "s3c2410fb: Debug On");
 608        } else if (strnicmp(buf, "off", 3) == 0 ||
 609                   strnicmp(buf, "0", 1) == 0) {
 610                debug = 0;
 611                dev_dbg(dev, "s3c2410fb: Debug Off");
 612        } else {
 613                return -EINVAL;
 614        }
 615
 616        return len;
 617}
 618
 619static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
 620
 621static struct fb_ops s3c2410fb_ops = {
 622        .owner          = THIS_MODULE,
 623        .fb_check_var   = s3c2410fb_check_var,
 624        .fb_set_par     = s3c2410fb_set_par,
 625        .fb_blank       = s3c2410fb_blank,
 626        .fb_setcolreg   = s3c2410fb_setcolreg,
 627        .fb_fillrect    = cfb_fillrect,
 628        .fb_copyarea    = cfb_copyarea,
 629        .fb_imageblit   = cfb_imageblit,
 630};
 631
 632/*
 633 * s3c2410fb_map_video_memory():
 634 *      Allocates the DRAM memory for the frame buffer.  This bufferris
 635 *      remapped into a non-cached, non-buffered, memory region to
 636 *      allow palette and pixel writes to occur without flushing the
 637 *      cache.  Once tdis arearis remapped, all virtual memory
 638 *      access to the video memory should occur at the new region.
 639 */
 640static int s3c2410fb_map_video_memory(struct fb_info *info)
 641{
 642        struct s3c2410fb_info *fbi = info->par;
 643        dma_addr_t map_dma;
 644        unsigned map_size = PAGE_ALIGN(info->fix.smem_len);
 645
 646        dprintk("map_video_memory(fbi=%p) map_size %u\n", fbi, map_size);
 647
 648        info->screen_base = dma_alloc_writecombine(fbi->dev, map_size,
 649                                                   &map_dma, GFP_KERNEL);
 650
 651        if (info->screen_base) {
 652                /* prevent initial garbage on screen */
 653                dprintk("map_video_memory: clear %p:%08x\n",
 654                        info->screen_base, map_size);
memset(info->screen_base, 0x00, map_size);
 656
 657                info->fix.smem_start = map_dma;
 658
 659                dprintk("map_video_memory: dma=%08lx cpu=%p size=%08x\n",
 660                        info->fix.smem_start, info->screen_base, map_size);
 661        }
 662
 663        return info->screen_base ? 0 : -ENOMEM;
 664}
 665
 666static inline void s3c2410fb_unmap_video_memory(struct fb_info *info)
 667{
 668        struct s3c2410fb_info *fbi = info->par;
 669
 670        dma_free_writecombine(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
 671                              info->screen_base, info->fix.smem_start);
 672}
 673
 674static inline void modify_gpio(void __iomem *reg,
 675                               unsigned long set, unsigned long mask)
 676{
 677        unsigned long tmp;
 678
 679        tmp = readl(reg) & ~mask;
 680        writel(tmp | set, reg);
 681}
 682
 683/*
 684 * s3c2410fb_init_registers - Initialise all LCD-related registers
 685 */
 686static int s3c2410fb_init_registers(struct fb_info *info)
 687{
 688        struct s3c2410fb_info *fbi = info->par;
 689        struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
 690        unsigned long flags;
 691        void __iomem *regs = fbi->io;
 692        void __iomem *tpal;
 693        void __iomem *lpcsel;
 694
 695        if (is_s3c2412(fbi)) {
 696                tpal = regs + S3C2412_TPAL;
 697                lpcsel = regs + S3C2412_TCONSEL;
 698        } else {
 699                tpal = regs + S3C2410_TPAL;
 700                lpcsel = regs + S3C2410_LPCSEL;
 701        }
 702
 703        /* Initialise LCD with values from haret */
 704
 705        local_irq_save(flags);
 706
 707        /* modify the gpio(s) with interrupts set (bjd) */
 708
 709        modify_gpio(S3C2410_GPCUP,  mach_info->gpcup,  mach_info->gpcup_mask);
 710        modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
 711        modify_gpio(S3C2410_GPDUP,  mach_info->gpdup,  mach_info->gpdup_mask);
 712        modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
 713
 714        local_irq_restore(flags);
 715
 716        dprintk("LPCSEL    = 0x%08lx\n", mach_info->lpcsel);
 717        writel(mach_info->lpcsel, lpcsel);
 718
 719        dprintk("replacing TPAL %08x\n", readl(tpal));
 720
 721        /* ensure temporary palette disabled */
 722        writel(0x00, tpal);
 723
 724        return 0;
 725}
 726
 727static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
 728{
 729        unsigned int i;
 730        void __iomem *regs = fbi->io;
 731
 732        fbi->palette_ready = 0;
 733
 734        for (i = 0; i < 256; i++) {
 735                unsigned long ent = fbi->palette_buffer[i];
 736                if (ent == PALETTE_BUFF_CLEAR)
 737                        continue;
 738
 739                writel(ent, regs + S3C2410_TFTPAL(i));
 740
 741                /* it seems the only way to know exactly
 742                 * if the palette wrote ok,ris to check
 743                 * to see if the value verifies ok
 744                 */
 745
 746                if (readw(regs + S3C2410_TFTPAL(i)) == ent)
 747                        fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 748                else
 749                        fbi->palette_ready = 1;   /* retry */
 750        }
 751}
 752
 753static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
 754{
s3c2410fb_info *fbi = dev_id;
 756        void __iomem *irq_base = fbi->irq_base;
 757        unsigned long lcdirq = readl(irq_base + S3C24XX_LCDINTPND);
 758
 759        if (lcdirq & S3C2410_LCDINT_FRSYNC) {
 760                if (fbi->palette_ready)
 761                        s3c2410fb_write_palette(fbi);
 762
 763                writel(S3C2410_LCDINT_FRSYNC, irq_base + S3C24XX_LCDINTPND);
 764                writel(S3C2410_LCDINT_FRSYNC, irq_base + S3C24XX_LCDSRCPND);
 765        }
 766
 767        return IRQ_HANDLED;
 768}
 769
 770#ifdef CONFIG_CPU_FREQ
 771
 772static int s3c2410fb_cpufreq_transition(struct notifier_block *nb,
 773                                        unsigned long val, void *data)
 774{
 775        struct s3c2410fb_info *info;
 776        struct fb_info *fbinfo;
 777        long delta_f;
 778
 779        info = container_of(nb, struct s3c2410fb_info, freq_transition);
 780        fbinfo = platform_get_drvdata(to_platform_device(info->dev));
 781
 782        /* work out change, <0 for speed-up */
 783        delta_f = info->clk_rate - clk_get_rate(info->clk);
 784
 785        if ((val == CPUFREQ_POSTCHANGE && delta_f > 0) ||
 786            (val == CPUFREQ_PRECHANGE && delta_f < 0)) {
 787                info->clk_rate = clk_get_rate(info->clk);
 788                s3c2410fb_activate_var(fbinfo);
 789        }
 790
 791        return 0;
 792}
 793
 794static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info *info)
 795{
 796        info->freq_transition.notifier_call = s3c2410fb_cpufreq_transition;
 797
 798        return cpufreq_register_notifier(&info->freq_transition,
 799                                         CPUFREQ_TRANSITION_NOTIFIER);
 800}
 801
 802static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info *info)
 803{
 804        cpufreq_unregister_notifier(&info->freq_transition,
 805                                    CPUFREQ_TRANSITION_NOTIFIER);
 806}
 807
 808#else
 809static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info *info)
 810{
 811        return 0;
 812}
 813
 814static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info *info)
 815{
 816}
 817#endif
 818
 819
 820static const char driver_name[] = "s3c2410fb";
 821
 822static int s3c24xxfb_probe(struct platform_device *pdev,
 823                           e0> 82iver_name" class="sref">dr" class="sref">dr" class="sref">dr" class="sre;
platfoideo/sUpcf">drtring">"s3c2o/sUpclass="sref">pladeo/sUpcf">d5"> 815{
 775        struct  *info;
 776        struct fbinivers/videdisrivnfo" class="sref">fb_info 776        struct s3c827f="+code=fbinfo" class="sref">fbinfo;
 777        long  *fbiclass="sref">mach_info = fbi-> 777        long i;
,
fbres/a>,
 777        long __iomem 8 777        long  777        long fbi-> 730        void  730        void i = 0; (&uf">fbi-ss="liualette__notifier(&lcine"1>fbi-ss="lilcine"1="L60"> 730        void  746                if (ent =8 dev->823" class="line" name="L822410fb.c#L781" id="L781" class="line" name="Lode=s3c2410fb_cp10fb.c#L690" id="L690" class="line" name="L690"> 690        unsigned long pai->dev->NUL= d587"> 787                ( 823                           ede=writel8 class="sref">writel8 806}
 690        unsigned long  702
 763                pai->dev->i->d587"> 787                 787                CPUFREclass="sref">pai->lpcsel);
,
d50"> 690        unsigned long readw( 690        unsigned long fbi->8 702
 819
fbi->84ntainer_of" class="sref">condisrivnfo" class="srefdisrivnc241sref">dev->i->da href="drivers/vii-> 690        unsigned long  791        return 0;
)
)
 690        unsigned long pa)
 787                irqreturn_t 806}
 690        unsigned long s3c8410fb85ne" name="L766"> 766
__iomem 8 767        return lcdi8q85mach_info" class="sref">machs="sref">platform_get_drvdata(lUFF_CL_alloc" id="L805" class">lUFF_CL_alloc> *info)
 806}
machs="sref">platform_get_drvdata 815{
lcdirq &am8;  690        unsigned long fbi-&8t; 791        return 0;
to_platformsdevice(machs="sref">platform_get_drvdata 690        unsigned long  763                writel8info(platform_get_drvdata 689        struct writel8(&
 689        struct pladeo/sUpcf">d3c2410fb.c#L7a6" id2o/sUpclass="sref">pladeo/sUpcf">d9"> 689        struct  767        return IRQ_HA8DLED<86mach_info" class="sref">machres/a>,
(machIORESOURCE_MEM  690        unsigned long machres/a>,
ref">dev->NUL= d587"> 787                ent, < namer410fb_info" clas namer4q_transition" class="sref823" class="line" name="L822410fb.c#L781" id="L781" class="line" name="L3 se=tpal" class="50"> 690        unsigned long CONFIG_CPU8FREQ<87ef="+code=regs" class="sref">regs(-b.c#L781" id="LENXIO d9"> 689        struct s3c2410fb_writgoto b.c#L781" id="L78alloc_fs3c2410fb_infod9"> 689        struct  766
 814static (&id="L661" class="liname="L6ass="sref">irq_base 690        unsigned long s3c8410fb87ne" name="L76_notifier(&
irq_basemachid="L661" class="liname="L63 ass="sref">mach823" class="line" name="L822410fb.c#L781" id="L";
 690        unsigned long fb_infopa<dev->NUL= d587"> 787                delta_f;8clk_r namer410fb_info" clas namer4q_transition" class="sref823" class="line" name="L822410fb.c#L781" id="L781" class="line" name="L3 690        unsigned long ((-b.c#L781" id="LENOENT  690        unsigned long info = d9"> 689        struct fbinfo =  751}
 782        /* work8out change, <0 for sp8ed-up8*/
pa<clk_raoremao->machid="L661" class="liname="L650"> 690        unsigned long delta_f = pa<dev->NUL= d587"> 787                 s faie" e=tpal" class="50"> 690        unsigned long val == regs(-b.c#L781" id="LENXIO d9"> 689        struct val == d9"> 689        struct info->8 702
88"L819"> 819
pladeo/sUpcf">d3cref">dev->DRV_a> + <">fbi-ss="liDRV_a> + <"ta 815{
regsirq_bas<i<2 href="BASElass="line" namef">i<2 href="BASEf">d9"> 689        struct  809static regsirq_bas<i<0 href="BASElass="line" namef">i<0 href="BASEf">d9"> 689        struct  794static inline int deo/nite=tpal" class="50"> 690        unsigned long  746                if (info->platform_get_drvdataplatform_get_ixtamachc2410fb";
 690        unsigned long  798        return cpufreq_regisref="drivers/video/s3c241StopL744" eturname="L783"> 783        conlcine"1>fbi-ss="lilcine"1="L6ass="sref">irq_base + i<0 hreCON1>fbi-ss="lief">i<0 hreCON1s/vi50"> 690        unsigned long S3C2410_LCDINT_FRSYNC, fbi-ss="lilcine"1="L6adriver~de=i" class="sref">i<0 hreCON1_ENVIL76ss="sref765" class<0 hreCON1_ENVIL"L753 ass="sref">machsi<0 hreCON1>fbi-ss="lief">i<0 hreCON1s/vi50"> 690        unsigned long  802static inline void paletsref">platform_get_drvdataplatform_get_ixtaplasUpcf">d333333333333ss="sref">irq_basFB_TYPE_PACKED_PIXELSlass="sref">plaFB_TYPE_PACKED_PIXELSf">d9"> 689        struct infoplatform_get_drvdataplatform_get_ixtaplatform_getsUpc_auxde=info" claL733"> 733
cpu9req_unregister_notifier(&letsref">platform_get_drvdataplatform_get_ixta-> 733
platform_get_drvdataplatform_get_ixta-> 733
info->platform_get_drvdataplatform_get_ixta-> 733
machs="sref">platform_get_drvdataplatform_get_ixtaS3C2410_LCDINacceff">d33333333333ss="sref">irq_basFB_ACCEL_NONElass="line" namFB_ACCEL_NONEf">d9"> 689        struct  819
inline int cons="sref">platform_get_drvdatafbinfo);ideo/s3ode=s3c2410fb_cpuf8st56" class="line"uf8st5f">d3333333333L733"> 733
platform_get_drvdatafbinfo);ideo/s3ode=s3c2410fb_cpdrivers/">S3C2410_LCDINacivers/de=info" claL7="sref">irq_basFB_ACTIVATE_NOWlass="line" namFB_ACTIVATE_NOWf">d9"> 689        struct platform_get_drvdatafbinfo);ideo/s3ode=s3c2410fb_cpdrcef_fla2410_TFTPAL( 733
paletsref">platform_get_drvdatafbinfo);ideo/s3ode=s3c2410fb_cpvmb_cf">fbinfo);imb_cf">d33333333333ss="sref">irq_basFB_VMODE_NONINTERLACid="L768" class="FB_VMODE_NONINTERLACidf">d9"> 689        struct  814static inline void platform_get_drvdata(<" claegi9ter_notifier" class="sre9">cpu9req_uC9" class=1MODE_NONINTERLACplatform_get_drvdatclass91li9SITIO90ne" name="L76_notifier(&letsref">platform_get_drvdata(d33333333333ss="sref"INFO_FLAG_DEFAULid="LENOENT platform_get_drvdatafbisref">machsfbi 798        return cpu1" node=S3C24XX_LCDIN">machsmachsmachs + <"ta 815{
sref">machsfbimachs 791        return 0;9video/s3c9410fb.c#L822" id="L822" 9lass=92d=9L812"91ef="+code=S3C2410_f">regspa)
pa)
pa)
mach823" class="line" name="L822410fb.c#L781" id="L";
machs 690        unsigned l="+code=s9c24xxfb_probe" class="sr9f">s392in8" nam85238" id="L738dy" classf">regsd587"> 787                <9         90> 82iver_name" class="s9ef">d9" class="sref">dr" clae"e="L753 ass="sNC" class namer410fb_info" clas namer4q_transition" class="sref823" class="line" name="L822410fb.c#L781" id="L781" class="line" name="L3)
regs 690        unsigned l=de=inlin9rivers/vi8eo/s3c2410fb.c9L725"92in8" nam88="+code=S3C2410_LCDINT_FRSf">regs(-b.c#L7BUSYregs 702
 798        return sref">machs->NUL= deo/nite=tpal" class="50"> 690        unsigned 9ef="+code9210fb.c#L8 class="sref">9;92 c8ass="88ef="+code=S3C2410_LCDIIS_ERs/video/s3c2410fIS_ERs="+code=S3C24XX_LCDINTPND" clasd587"> 787                <9ef="+code9__iomem" 8lass="sref">__9omem<93in8" nam89ef="+code=regs" class="sresNC" class namer410fb_info" clas namer4q_transition" class="sref823" class="line" name="L822410fb.c#L781" id="L781" class="line" name="L3deo/nite=tpal" class="50"> 690        unsigned 9ef="+code9_10fb.c#L832" id="L732" 9lass=93in8" nam87"sref">s3c2"+code=S3C2410_f">regs 690        unsigned 9e"+code=s9_24xxfb_prf">fbi->9pa)
 702
i = 9;  785        if (( 690        unsigned 9eideo/s3c9"+code=en8" class="sref"9ent =8 (& %08x\n", deo/nite=tpal" class="50"> 690        unsigned 9eref="+co9inue;
 798        return usleep_rfb.c>(& %08x\n&usleep_rfb.cspan>1000li1100l" class="50"> 690        unsigned 9ef="+code9de=writel8 class="sref">9ritel93ine" name="L820"> 820static const char9/video/s39410fb.c#L841" id="L741" 9lass=94li9e" na91e=platform_get_drvNTPND" clasclk_get_rate(info->clk);
 788                <9ong  802static  783        machsmachslpcsel);
,
machseNUL=f">d587"> 787                <9 href="+c9         8 */
->i->machs,
x 777        long  746                i9ong rea9w(->i->machs,
y 777        long f94>;8->i->machs-bpchref="dresss="7"> 777        long s3c2410fb_activate_var( 777        long f94in8" nam86="+code=ent"+code=S3C2410_LCDIsref">machs="sref">platform_get_drvdataplatform_get_ixta 815{
machs="sref">platform_get_drvdataplatform_get_ixta 777        long  702
 763                <9 href="+c9urn_t" cl8ss="sref">irqr9turn_9 783        regspa)
sref">machs="sref">platform_get_drvdata 690        unsigned 9ong regsd587"> 787                <9video/s3c9__iomem" 8lass="sref">__9omem<95(regs 690        unsigned lhref="+co9f="+code=8cdirq" class="9ref">95>;8 690        unsigned 9/video/s39210fb.c#L859" id="L759" 9lass=95="sref">s3c2410fb_actRECHANs="sgoto b.c#L781" id="Lockref">pa)
 690        unsigned 9/f="+code9cdirq" cl8ss="sref">lcdi9q9&am8;  702
-&8t; 791        return 0;9deo/nite=tpal" class="50"> 690        unsigned 9ong  763                <9 href="+c9de=writel8 class="sref">9ritel9/a>8paletsref">platform_get_drvdatafbinfo);ideo/s3ode=s3c+code=infores/a>,
xd3c2410fb.sref">condisrivnfo" class="srefd_drvdata,
x 777        long 9ritel9/a>8paletsref">platform_get_drvdatafbinfo);ideo/s3ode=s3y+code=infores/a>,
yd3c2410fb.sref">condisrivnfo" class="srefd_drvdata,
y 777        long paletsref">platform_get_drvdatafbinfo);ideo/s3ode=s3bits_per_pix10fb_cpaccef">S3Cbits_per_pix10hrefo/sUpcf">d3c2410fb.sref">condisrivnfo" class="srefd_drvdata-bpchref="dresss="7"> 777        long  767        return IR9_HA8DLED<86mach_info" class="a href="drivits3c2410fb class=1MODE_NONINTERLACsref">machs="sref">platform_get_drvdata 690        unsigned 9ong  819
fbINTERLACpaletsref">platform_get_drvdatafbinfomachs="sref">platform_get_drvdata 690        unsigned 9ong 9ONFIG97-&8t; 791        return 0;9href="+co9410fb.c#L872" id="L772" 9lass=97d=9L812"91ef="+code=S3C2410_f">regss3c2410fbid="L68sref">fbINTERLACs3c2410fbe=clk" class="sref">clk);
 690        unsigned 9ong regs 787                <9video/s3c9         8  unsigned lon9 dr" clae"e="L753 ass="sNC" class namer410fb_info" clas namer4q_transition" class="sref823" class="line" name="L822410fb.c#L781" id="L781" class="line" name="L3f">deo/nite=tpal" class="50"> 690        unsigned 9ode=inlin92410fb.c#8775" id="L775"9class97iv8rs/vi84="+code=S3CRECHANs="sgoto b.c#Lef"e_a>   _" nto ref">pa)
   _" nto href="dresss="7"> 777        long  702
9b_inf97in8" nam8="L767"> 767        return de9ta_f<97HA8DLED<86mach_info" class="sr>regssref">machs="sref">platform_get_drvdata 690        unsigned 9ong  787                <9vhref="+c9 class="s8ef">info =9 787                <9href="+co9o" class=8sref">fbinfo = <98in8" nam89ef="+code=r10fb_activate_var(regs 690        unsigned l/video/s39410fb.c#L882" id="L782" 9lass=98in8" nam87"sref">s3c2410fb_writgoto b.c#Lef"e_csref">ref">pa)
href="dresss="7"> 777        long /* work8out change, &l9;0 fo9 sp8ed-up8*/ 702
delta_f9/a> =98in9" nam9="L814"> 814static  783        val 690        unsigned l/ng valregs 690        unsigned l/href="+c9velta_f" 8lass="sref">in9o98>;8clk_r namer410fb_info" clas namer4q_transition" class="sref823" class="line" name="L822410fb.c#L781" id="L781" class="line" name="L3deo/nite=tpal" class="50"> 690        unsigned 9video/s3c9de=s3c2418fb_activate_va9" cla9s="8ref">88"L819"> 819
machs="sref">plinfoef">las namer4q_transition" class="sref823" class="line" name="L822410fb.c#L781" id="L781" class="line" name="L3 787                <9/video/s39410fb.c#L891" id="L791" 9lass=9lin8" nam89ef="+code=regs" class="sre="sref">paletsref">platform_get_drvdatafbno10omachs="sref">platform_get_drvdataplatform_get_ixta 690        unsigned 9href="+co9rivers/vi8eo/s3c2410fb.c9L792"99d=9" nam9="L802"> 802static  733
 794static inlineref">pa)
href:nam8="L794"> 794static sde3c2410fbid="L68sref">fbINTERLACsde3c2410fbe=clk" class="sref">clk);
 690        unsigned 9 (info-&9t;   _" nto ref">pa)
   _" nto href:nam8="L794"> 794static    _" nto ref">pa)
sref">machs="sref">platform_get_drvdata 690        unsigned 9href="+co9e=cpufreq8register_notif9er" c9ass8"sNs="sgoto b.c#L781" id="Lockref">pa)
 794static clk);
 788                <1000deo/s3c1000de     8   clk);
ame="L788"> 788                <1001deo/s3c100ivers/vi8eo/s3c2410fb.c100iv>1001s8"sNs="sgoto b.c#L781" id=="sref">pa)
 794static 100li9e" na91lette_ready" class=f"e_="sref">pa)
cPDUP" cla)
);
 690        unsigned 1003deo/s3c100f" class894" id="L794" 100f">1003s8"sNs="sgoto b.c#L781" id=repdrcef_fla2410_TF781" id=repd"8co:nam8="L794"> 794static inline100a>8);
clk);
 690        unsigned 1005deo/s3c100410fb.c#8796" id="L796"10041>1005s8"sNs="sgoto b.c#L781" id="Lrelease_se =  794static info-&100cl>100 =8 +code=infores/a>,
machid="L661" class="liname="L650"> 690        unsigned 1007deo/s3c100elta_f" 898" id="L798" 100el>1007s8"sNs="sgoto b.c#L781" id="L78alloc_fs3c2410fb_info 794static "L805" class"La hreref">pa)
sref">machs="sref">platform_get_drvdata 690        unsigned 1009deo/s3c100        8   regs 690        unsigned 1010deo/s3c102410fb.c#9811" id="L811"10241>1024/vid name="L702"> 702
 802static 102li9e"erstic inzeofhref="+code=info" classprobf">machid="L661" fo" classprobfe=clk* 690        unsigned 1023deo/s3c10r410fb.c#914" id="L814" 10r41>1023s8"sianame="L87"> 787                <1024deo/s3c10" class="9ref">inline1024E8_TRAN89nta" classde=fbidy" class     xxassprobf">machid="L661" fo" xxassprobfe=clk" class="sref">+code=info823" class="line" name="L823 ass="/a>-ss="li0e=info823" clas/a>-ss="li0_get_drvdata 690        unsigned 1015deo/s3c10sref">platform_get_drvda10sre>1025/vid name="L702"> 702
102in8" nam8="L767"> 767        return machid="L661" fo" c2assprobfe=clk* 690        unsigned 1028deo/s3c10410fb.c#L819" id="L819" 10410>1028s8"sianame="L87"> 787                <1029deo/s3c10410fb.c#L820" id="L820" 10410>102RE8_TRAN89nta" classde=fbidy" class     xxassprobf">machid="L661" fo" xxassprobfe=clk" class="sref">+code=info823" class="line" name="L823 ass="/a>-ss="liDRV_a> + <">fbi-ss="liDRV_a>drvdata 690        unsigned 1020deo/s3c10code=driver_name" class=10cod>10co/vid name="L702"> 702
10cd=9" nam9="L802"> 802static  763                <10c3deo/s3c100> 82iver_name" class="s100> >10c3s8"sNpan>
 783        
 783        10c5s8"sNpan>
 783        10c6i9e"erstic inzeofhref="+code=info" classremovf">machid="L661" fo" classremovfe=clk* 690        unsigned 1027deo/s3c104/s3c2410frite_palette" 104/s>10c7s8"sianame="L87"> 787                <1028deo/s3c102410fb.c#8729" id="L729"10241>10cli8e" na82nfo*machs="sref">platoef">las R*q_transition" csref">machs="sref">platform_get="dresss="a>(+code=info823" class="line">drvdata 690        unsigned 1029deo/s3c10210fb.c#L8 class="sref">10210>10c9i8e" na82nfo*machs="sref">plINTERLAClas R*q_transition" cclk);
platform_get_drvdatafbpnfo 690        unsigned 1030deo/s3c10__iomem" 8lass="sref">__10__i>10__a8 *)
 690        unsigned 1031deo/s3c10_10fb.c#L832" id="L732" 10_10>10_d=9" nam9="L802"> 802static fbi->10_24>10_li9e" na91lette_ready" classunf"2410fb_"L805" clasregssref">machs="sref">platform_get_drvdata 690        unsigned 1033deo/s3c10410fb.c#L834" id="L734" 10410>10_a>8sde3c2410fbid="L68sref">fbINTERLACsde3c2410fbe=clk" class="sref">clk);
 690        unsigned 10_4deo/s3c104ivers/vi8sref">i = 104iv>10_ine" name="L785"> 785        if ((10_ c8ass="8ine" name="L76_notiINTERLACclk);
 690        unsigned 10_6deo/s3c10"+code=en8" class="sref"10"+c>10_ =8 (& %08x\n&usleep_rfb.cspan>1000li1100l" class="50"> 690        unsigned 10_7deo/s3c10inue;
 798        return 10_li8e" na82nfo" class="sref">a href="drunmap_a>   _" nto ref">pa)
sref">machs="sref">platform_get_drvdata 690        unsigned 10_9deo/s3c10de=writel8 class="sref">10de=>10_ine" name="L820"> 820static const char1040deo/s3c10410fb.c#L841" id="L741" 10410>1041a8 *pa< 787                <1041deo/s3c10"comment"8/* it seems th10"co>104in8" nam87"sref">s3c2"+code=S3C2410_a hrdisabl" id="L"clk);
 788                <1042deo/s3c10         8 * if the pale10   >104li8e" na892f="+code=regs" class="srea hrpu" id="L788" class="spu"e=clk" class="sref">clk);
 788                <1043deo/s3c10         8 * to see if t10   >104 class="sref">dr" clae"e="L753 ass="sref">machs->NUL=  788                <1044deo/s3c10         8 */
1044E8_TRAN89nta name="L702"> 702
104li8e" na89"L746"> 746                i1046deo/s3c10"+code=en8dw" class="sre10"+c>104 =8 )
)
+code=info823" class="line" n0l" class="50"> 690        unsigned 1047deo/s3c10"nue;
104in9" nam90mach_info" class="sf"e_="sref">pa)
cPDUP" cla)
);
 690        unsigned 1048deo/s3c10 10fb.c#L8video/s3c2410f10 10>104="8ref">88"L819"> 819
);
clk);
 690        unsigned 1050deo/s3c10ideo/s3c2810fb.c#L751" i10ide>10id"8ref">88"L819"> 819
10id=9L812"91ef="+code=S3C2410_f"a href="rclk);
 =="relea="dresss="2410fb.c#L781" id="Lstar="drivers/video/star="L823 ass="relass="_sref">machid="L661"relass="_srefe=clk" class="sref">clk);
 =="relea)_drvdata 690        unsigned 1052deo/s3c10410fb.c#L853" id="L753" 10410>10iin8" nam8="L763"> 763                <1053deo/s3c10urn_t" cl8ss="sref">irqr10urn>10ia>8pa)
sref">machs="sref">platform_get_drvdata 690        unsigned 1054deo/s3c102410fb.c#87ass="sref755"10241>10iine" name="L785"> 785        if ((10i c8ass="8ine"" class="+code=L733"> 733
__10__i>10i6/vid name="L702"> 702
10iin8" nam8="L798"> 798        return 10i="8re#ifdefe=info" class="sCONFIG_Pid="LENOMEM  798        return lcdi10cdi>10iine" name="L820"> 820static const char1060deo/s3c10"+code=fb8" class="sref"10"+c>10"+s8"sNpan>
 783        10"1i9e"erstic inzeofhref="+code=info" classsuspendref">pa)
info-><781f"ine"dCON1s/vi50"> 690        unsigned 1062deo/s3c10"10fb.c#L863" id="L763" 10"10>10"2s8"sianame="L87"> 787                <1063deo/s3c10de=writel8 class="sref">10de=>10"a>8machs="sref">platoef">las RRRRR*q_transition" csref">machs="sref">platform_get="dresss="a>(781" id="L781" class="linvi8sref">i = 104iv>10_ine" name="L785fhref="+code=iCpa)
platform_get_drvdata10i6/vid name="L702"> 702<9_drvdata 9a>)
i = 104iv>10_ine" name="L785"> 785        if ((10_ c8ass="8ine" name="L76_no6ass="8ine"eo-bpchref="dresss="e"eo__10__ic2410fb class=1MODE_NONI_ic24vdat     unsigned eturn static const char1060deo/s3c10"+code=fb8" cl58deo/s3c1>platform_get_drvdataplvdat93c2410fb.c10riv>10c4s8"sNpaaaaaaaaa*ine" LCD DMA4engt_d is  nameoinginr410fbback onine" bus/a>static const char1060deo/s3c10"+code=fb8" c7EM ONm_3c2410fb.c10riv>10c4s8"sNpaaaaaaaaa*ibecode ne" atformeoes off again (bjd)20static const char1060deo/s3c10"+code=fb8" c7ass="sref">platform_get_drvdatapl>ONm__i>10__a8 *s3c2410fbid="L68sref">fef>s3>ONm     unsigned 1031deo/s3c10_1ef">clk);
 690        unsigned 10_6deo/s3c10"+code=e7/a>-><79410fb.c#L8ufreq_transit<7941>ONm     unsigned 1052deo/s3c104L88" id="L788" class="line"vianame="L87"> 787                <1041deo/s3c10"comment"8/* it seems th10"co>104in8" nam87"sref">s3c2"+code=S3C2410_a hrdisabl" id="L"7(ONmclass"La hree=clk" class="sref">sref">machs=7drvdataONm     unsigned 1054deo/s3c102410fb.c#87ass="sref755"10241>10ii7 E8_TR_i>1 href="dresss="7"> 7771 hr>ONm5deo/s3c10i410fb.c#8b_info" class=10i41>10i c7ass="8ine"s3c8410fb87ne" name="L70e"s3c>ONmhref="drivers10i6deo/s3c10__iomem" 8lass="sr7f">__10__i_"L805" clasregsONm8.c#8726" id="L726"10241>10c5s8"sNpan>
l"drivers *44" eturname="L78f">l3        10"1i9e"erstic inzeofhref="+code=info" classsuspendreTR*q_transition" c781" id="L781" class="758deo/s3c19_410fb.c#879" id="L779"c19_4>ONm9ivinfo8EM 10"2s8"sianame="L87"> 787                <1063deo/s3c10de=writel8 class="sref">10de=>10"a>8machs="sref">platoef">las RRRRR*q_transition" csref">machs="sref">pla2410fb.c#L781f">info8ass="sref"class=8sref">fbinfo f"cla>ONc1   unsigned 1062deo/s3c10"10fb.c#Lf">781" id="L781" class="linvi8sref">i = 104iv>10_ine" name="L785fhref="+code=iCpa)
platform_get8ine" fhref"L782" 9lass=98in8" nam8ef"L7>ONc-><7>href="dresss="7"> 777hr>ONc     unsigned 1052deo/s3c104L88"ivers/vi8sref">i = 9;  785        if ((ONc03s8"sNs="sgoto b.c#L781" id1ef">clk);
 690        unsigned 10_6deo/s3c10"+code=e8drvdataONc3C2410_a hrdisabl" id="L"2riv1.c#L781" id="L781" class>1.c#>ONca 9a>)
 767        return IR9_HA8DLED<86mach_info" class="a hreONcass="8ine"/ng ONchref="drivers10i6deo/s3c10__iomem" 8lass="sr8f">__10__i781" id="L781" class="li_i781>ONc     unsigned eturn  802afinforef">lc0static const char1060deo/s3c10"+code=fb8" c858deo/s3c1>deo/nite=tpal" class="5c1>de>ONc/a>        unsigned 9ong IR9_HA8DLED<86mach_info" class="a hreON9EM pa)
IR9_HA8DLED<86mach_info" class="a hreON9ass="sref"">platform_get_drvdatap>ONd__i>10__a8 *-><7m9="L802"> 802static<7m9=>ONd3deo/s3c10i410fb.c#8b_info" class=10i41>10i c9(ONdclass"La hree=clk" class="sref">sref">machs=9drvdatainline/1in9>ONd3C241#else"La hree=clk" class="sref">sref">machs=9 E8_TR_i>13c2410fbid="L68sref">fbI>13c2>ONda 783104 clas"La hree=clk" class="sref">sref">machs=9ass="8ine"="s8ef">info-&9t;l"drivers *44" eturname="L78f">l3104 clas"La hree=clk" class="sref">sref">machs=9f">__10__into ref">pa)
ONd href= 78if"La hree=clk" class="sref">sref">machs=958deo/s3c1o9e=cpufreq8register_notc1o9e>ONdi="8re#ifdefe=info" class="sCONFIG_Pid="LEN1;c1k1;
10fo" ciinf1#L788" id=1L788" class="line" na/pre11028s8"si"> 7879ONFIG97-&8t; 3c2410fb.c10riv>102d=9" nam9="L802"> 80="sref823" class="line" name="L822410fi102788" id=1L56" class="ll" class="5e1c100i1>1001s8"sNs="sform_get_drvdata href="drivers *44" e783"> 7839ONFIG97-&8t;  href="drivers *44" eturname="L783"> 783<="sref823" class="line" name="L822410fi103788" id=1L9="L802"> 802static<1>cPDU103001s8"sNs="sform_get_drvdatalcd="ontroller *44" etu3"> 7839ONFIG97-&8t; lcd="ontroller *44" eturname="L783"> 7831003s8"sNs="sgoform_get_drvdata hf">l"drivers *44" e78f">l39ONFIG97-&8t;  hf">l"drivers *44" eturname="L78f">l3inline/1clk9f="ssage_ E8_TRsss="2410fb.c#L781f">inf1#6788" id=1Lc2410fbid="L68sref">fbI>1"10041>1005s8"sNs="ssNs="sgoform_get_drvdataef">od8=s3c2410fb_wef">005s8"s=0ntainer_of" class=infoef">mb.c#L78-88" id="L788" cl="sref823" class="line" name="L822410fi107788" id=1L"s8ef">info-&9t;9ONFIG97-&8t;pa)
1007s8"sNs=}="sref823" class="line" name="L822410fi109788" id=1L9e=cpufreq8register_notc1=f8051 class}href="+co9rivers/vi8eo/s3c2410fb.c9L79O1d 1009deo/13c100        8    6901/a>  11110fo" ciinf1"L811"10241>1024/vid name="L702"> 701
111001s8"sNs="sform_get_drvdata819" 10410>1028s8"si"> 7879ONFIG97-&8t;102in8" nam8="L767"> 76="sref823" class="line" name="L822410fi1ofhref="+c1de=i 7839ONFIG97-&8t;  href="drivers *44" eturname="L783"> 783<="sref823" class="line" name="L822410fi1ef823" cla1s="line"dCON1s/vi50"> 6901/a>  1103s8"sNs="sgoform_get_drvdatalcd="ontroller *44" etu3"> 7839ONFIG97-&8t; lcd="ontroller *44" eturname="L783"> 783+code=info823"1class1153s8"sNs="sgoform_get_drvdata hf">l"drivers *44" e78f">l39ONFIG97-&8t;  hf">l"drivers *44" eturname="L78f">l3 6901/a>  1163s8"sNs="sgoform_get_drvdataefo" cod8=s3c2410fb_wefo" c5" idnaaaaaa">9f="ssage_ E8_TRsss="2410fb.c#L781f">inf1_drvda10sr1>1025/vid name="L702"> 701
11/a9 == <98/a8 *od8=s3c2410fb_wef">005s8"s=0ntainer_of" class=infoef">mb.c#L72-88" id="L788" cl="sref823" class="line" name="L822410fi1ofhref="+c1de=i 6901/a>  1     unsigned }="sref823" class="line" name="L822410fi1bfe=clk" c1ass="sref">+code=info823"1class1"line" href="+co9rivers/vi8eo/s3c2410fb.c9L79O1bi-ss=1liDRV_a>drvdata 6901/a>  1     unsigned 1020deo/s3c10code=driver_name"1class=10co1>10co/vid name="L702"> 701
1a href="L726"10241>10c5s8_67"> od8=s3c2410fb_w_67"> i od8=s3c2410fb_weurname="L7">      voidTR*q_transition" c781" id="L781" class=1"L822" 10410>10cd=9" nam9="L802"> 801s12ssa href="o vercE8_TR*q_transition" class="s1"> 7631               <10c3deo/s1c100>1203s8"sNs="sgo="L726"10241>10c5s8"drivers/vicrecod2o verc f="Lsr744" eturnamri10ref>10fo" c        return 0;9href="ri10ref>10fo" c        r     "8ref">88"L819"> 819eurname="Lefo" cod8=s3c2410fb_weurname="Lefo" c5" i">IR9_HA8DLED<86mach_info" class="a hreO1>        <1 href="10c4deo/s3c10river1/vi8e123C2410_a hrdisabl" id="L"2riv 783 1      regs10fo" c        return 0;9href="ri10ref>10fo" c        r     "8ref">88"L819"> 819eurnam2="Lefo" cod8=s3c2410fb_weurnam2="Lefo" c5" i">IR9_HA8DLED<86mach_info" class="a hreO1>fhref="+c1s="line"dCON1s/vi50"> 6901/a>  12 cla)
1sref">machs="sref">platform_get_drvdata 690        unsign1href="driv1rs/="dresss="a>(-ss="liDRV_a> + <">1gned 1030d1o/s3c10__iomem" 8lass="sr1f">__10__i>10__a8 *)1 691 13 href="drivevoid726"10241>10c5s8_6ex> od8=s3c2410fb_w_6ex> i
   voidTR*q_transition" c781" id="L781" class=1"2410fb_"L105" clasregssde312410fbid="L68sref">fbINTE1LAC10fo" c nam9="L802eturn 0;9href="ri10ref>10fo" c nam9="L802     "8ref">88"L819"> 819eurname="Lefo" cod8=s3c2410fb_weurname="Lefo" c5" i">IR9_HA8DLED<86mach_info" class="a hreO1;
 691 1      unsigned 10_4deo/s3c104ri10ref>10fo" c nam9="L802eturn 0;9href="ri10ref>10fo" c nam9="L802     "8ref">88"L819"> 819eurnam2="Lefo" cod8=s3c2410fb_weurnam2="Lefo" c5" i">IR9_HA8DLED<86mach_info" class="a hreO1tiINTERLAC1rlcdsenabl" id="L"10i 1n8" class=1sref"10"+c>10_ =8 (& %08x\n&usleep_1fb.cspan>1100li1100l" class="50"> 691 13ap_a>   _" nto e=clkmoduleL7"> od8=s3c2410fb_wmoduleL7">      return  od8=s3c2410fb_weurname="L7">     ">IR9_HA8DLED<86mach_info" class="a hreO1ta href="+1o ref">pa)
 od8=s3c2410fb_wmoduleLex>      return 
  ">IR9_HA8DLED<86mach_info" class="a hreO1"sref">pla1form_get_drvdata 691 14);
14"L788domArnaud Patardtformarnaud.patard@rtp-net.orgcode4q_transition" class="sref823" class="line" name="L8>14 cla)1abl"e=clk" class="sref">c1k1;
mBen Dookstformben-claux@fluff.orgcode4q_transition" class="sref823" class="line" name="L8>142410fb_"L1spu"e=clk" class="sref">c1k14 cla)
mF clas namer4823" >10iine" ine" na4q_transition" class="sref823" class="line" name="L8>14ref">sde31drivers/video/s3c2410fb.c1L88" 1d="L78/a>)
mGPL4q_transition" class="sref823" class="line" name="L8>14
 788    1     14);
mri10ref>:b.c#L78-88" id="L788" cl" class="sref823" class="line" name="L8>14iINTERLAC1TRAN89nta name="L702"> 701
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