linux/drivers/tty/synclink.c
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   1/*
   2 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
   3 *
   4 * Device driver for Microgate SyncLink ISA and PCI
   5 * high speed multiprotocol serial adapters.
   6 *
   7 * written by Paul Fulghum for Microgate Corporation
   8 * paulkf@microgate.com
   9 *
  10 * Microgate and SyncLink are trademarks of Microgate Corporation
  11 *
  12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13 *
  14 * Original release 01/11/99
  15 *
  16 * This code is released under the GNU General Public License (GPL)
  17 *
  18 * This driver is primarily intended for use in synchronous
  19 * HDLC mode. Asynchronous mode is also provided.
  20 *
  21 * When operating in synchronous mode, each call to mgsl_write()
  22 * contains exactly one complete HDLC frame. Calling mgsl_put_char
  23 * will start assembling an HDLC frame that will not be sent until
  24 * mgsl_flush_chars or mgsl_write is called.
  25 * 
  26 * Synchronous receive data is reported as complete frames. To accomplish
  27 * this, the TTY flip buffer is bypassed (too small to hold largest
  28 * frame and may fragment frames) and the line discipline
  29 * receive entry point is called directly.
  30 *
  31 * This driver has been tested with a slightly modified ppp.c driver
  32 * for synchronous PPP.
  33 *
  34 * 2000/02/16
  35 * Added interface for syncppp.c driver (an alternate synchronous PPP
  36 * implementation that also supports Cisco HDLC). Each device instance
  37 * registers as a tty device AND a network device (if dosyncppp option
  38 * is set for the device). The functionality is determined by which
  39 * device interface is opened.
  40 *
  41 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  42 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  44 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  45 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  49 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  50 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  51 * OF THE POSSIBILITY OF SUCH DAMAGE.
  52 */
  53
  54#if defined(__i386__)
  55#  define BREAKPOINT() asm("   int $3");
  56#else
  57#  define BREAKPOINT() { }
  58#endif
  59
  60#define MAX_ISA_DEVICES 10
  61#define MAX_PCI_DEVICES 10
  62#define MAX_TOTAL_DEVICES 20
  63
  64#include <linux/module.h>
  65#include <linux/errno.h>
  66#include <linux/signal.h>
  67#include <linux/sched.h>
  68#include <linux/timer.h>
  69#include <linux/interrupt.h>
  70#include <linux/pci.h>
  71#include <linux/tty.h>
  72#include <linux/tty_flip.h>
  73#include <linux/serial.h>
  74#include <linux/major.h>
  75#include <linux/string.h>
  76#include <linux/fcntl.h>
  77#include <linux/ptrace.h>
  78#include <linux/ioport.h>
  79#include <linux/mm.h>
  80#include <linux/seq_file.h>
  81#include <linux/slab.h>
  82#include <linux/delay.h>
  83#include <linux/netdevice.h>
  84#include <linux/vmalloc.h>
  85#include <linux/init.h>
  86#include <linux/ioctl.h>
  87#include <linux/synclink.h>
  88
  89#include <asm/io.h>
  90#include <asm/irq.h>
  91#include <asm/dma.h>
  92#include <linux/bitops.h>
  93#include <asm/types.h>
  94#include <linux/termios.h>
  95#include <linux/workqueue.h>
  96#include <linux/hdlc.h>
  97#include <linux/dma-mapping.h>
  98
  99#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
 100#define SYNCLINK_GENERIC_HDLC 1
 101#else
 102#define SYNCLINK_GENERIC_HDLC 0
 103#endif
 104
 105#define GET_USER(error,value,addr) error = get_user(value,addr)
 106#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
 107#define PUT_USER(error,value,addr) error = put_user(value,addr)
 108#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
 109
 110#include <asm/uaccess.h>
 111
 112#define RCLRVALUE 0xffff
 113
 114static MGSL_PARAMS default_params = {
 115        MGSL_MODE_HDLC,                 /* unsigned long mode */
 116        0,                              /* unsigned char loopback; */
 117        HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
 118        HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
 119        0,                              /* unsigned long clock_speed; */
 120        0xff,                           /* unsigned char addr_filter; */
 121        HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
 122        HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
 123        HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
 124        9600,                           /* unsigned long data_rate; */
 125        8,                              /* unsigned char data_bits; */
 126        1,                              /* unsigned char stop_bits; */
 127        ASYNC_PARITY_NONE               /* unsigned char parity; */
 128};
 129
 130#define SHARED_MEM_ADDRESS_SIZE 0x40000
 131#define BUFFERLISTSIZE 4096
 132#define DMABUFFERSIZE 4096
 133#define MAXRXFRAMES 7
 134
 135typedef struct _DMABUFFERENTRY
 136{
 137        u32 phys_addr;  /* 32-bit flat physical address of data buffer */
 138        volatile u16 count;     /* buffer size/data count */
 139        volatile u16 status;    /* Control/status field */
 140        volatile u16 rcc;       /* character count field */
 141        u16 reserved;   /* padding required by 16C32 */
 142        u32 link;       /* 32-bit flat link to next buffer entry */
 143        char *virt_addr;        /* virtual address of data buffer */
 144        u32 phys_entry; /* physical address of this buffer entry */
 145        dma_addr_t dma_addr;
 146} DMABUFFERENTRY, *DMAPBUFFERENTRY;
 147
 148/* The queue of BH actions to be performed */
 149
 150#define BH_RECEIVE  1
 151#define BH_TRANSMIT 2
 152#define BH_STATUS   4
 153
 154#define IO_PIN_SHUTDOWN_LIMIT 100
 155
 156struct  _input_signal_events {
 157        int     ri_up;  
 158        int     ri_down;
 159        int     dsr_up;
 160        int     dsr_down;
 161        int     dcd_up;
 162        int     dcd_down;
 163        int     cts_up;
 164        int     cts_down;
 165};
 166
 167/* transmit holding buffer definitions*/
 168#define MAX_TX_HOLDING_BUFFERS 5
 169struct tx_holding_buffer {
 170        int     buffer_size;
 171        unsigned char * buffer;
 172};
 173
 174
 175/*
 176 * Device instance data structure
 177 */
 178 
 179struct mgsl_struct {
 180        int                     magic;
 181        struct tty_port         port;
 182        int                     line;
 183        int                     hw_version;
 184        
 185        struct mgsl_icount      icount;
 186        
 187        int                     timeout;
 188        int                     x_char;         /* xon/xoff character */
 189        u16                     read_status_mask;
 190        u16                     ignore_status_mask;     
 191        unsigned char           *xmit_buf;
 192        int                     xmit_head;
 193        int                     xmit_tail;
 194        int                     xmit_cnt;
 195        
 196        wait_queue_head_t       status_event_wait_q;
 197        wait_queue_head_t       event_wait_q;
 198        struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 199        struct mgsl_struct      *next_device;   /* device list link */
 200        
 201        spinlock_t irq_spinlock;                /* spinlock for synchronizing with ISR */
 202        struct work_struct task;                /* task structure for scheduling bh */
 203
 204        u32 EventMask;                  /* event trigger mask */
 205        u32 RecordedEvents;             /* pending events */
 206
 207        u32 max_frame_size;             /* as set by device config */
 208
 209        u32 pending_bh;
 210
 211        bool bh_running;                /* Protection from multiple */
 212        int isr_overflow;
 213        bool bh_requested;
 214        
 215        int dcd_chkcount;               /* check counts to prevent */
 216        int cts_chkcount;               /* too many IRQs if a signal */
 217        int dsr_chkcount;               /* is floating */
 218        int ri_chkcount;
 219
 220        char *buffer_list;              /* virtual address of Rx & Tx buffer lists */
 221        u32 buffer_list_phys;
 222        dma_addr_t buffer_list_dma_addr;
 223
 224        unsigned int rx_buffer_count;   /* count of total allocated Rx buffers */
 225        DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
 226        unsigned int current_rx_buffer;
 227
 228        int num_tx_dma_buffers;         /* number of tx dma frames required */
 229        int tx_dma_buffers_used;
 230        unsigned int tx_buffer_count;   /* count of total allocated Tx buffers */
 231        DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
 232        int start_tx_dma_buffer;        /* tx dma buffer to start tx dma operation */
 233        int current_tx_buffer;          /* next tx dma buffer to be loaded */
 234        
 235        unsigned char *intermediate_rxbuffer;
 236
 237        int num_tx_holding_buffers;     /* number of tx holding buffer allocated */
 238        int get_tx_holding_index;       /* next tx holding buffer for adapter to load */
 239        int put_tx_holding_index;       /* next tx holding buffer to store user request */
 240        int tx_holding_count;           /* number of tx holding buffers waiting */
 241        struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
 242
 243        bool rx_enabled;
 244        bool rx_overflow;
 245        bool rx_rcc_underrun;
 246
 247        bool tx_enabled;
 248        bool tx_active;
 249        u32 idle_mode;
 250
 251        u16 cmr_value;
 252        u16 tcsr_value;
 253
 254        char device_name[25];           /* device instance name */
 255
 256        unsigned int bus_type;  /* expansion bus type (ISA,EISA,PCI) */
 257        unsigned char bus;              /* expansion bus number (zero based) */
 258        unsigned char function;         /* PCI device number */
 259
 260        unsigned int io_base;           /* base I/O address of adapter */
 261        unsigned int io_addr_size;      /* size of the I/O address range */
 262        bool io_addr_requested;         /* true if I/O address requested */
 263        
 264        unsigned int irq_level;         /* interrupt level */
 265        unsigned long irq_flags;
 266        bool irq_requested;             /* true if IRQ requested */
 267        
 268        unsigned int dma_level;         /* DMA channel */
 269        bool dma_requested;             /* true if dma channel requested */
 270
 271        u16 mbre_bit;
 272        u16 loopback_bits;
 273        u16 usc_idle_mode;
 274
 275        MGSL_PARAMS params;             /* communications parameters */
 276
 277        unsigned char serial_signals;   /* current serial signal states */
 278
 279        bool irq_occurred;              /* for diagnostics use */
 280        unsigned int init_error;        /* Initialization startup error                 (DIAGS) */
 281        int     fDiagnosticsmode;       /* Driver in Diagnostic mode?                   (DIAGS) */
 282
 283        u32 last_mem_alloc;
 284        unsigned char* memory_base;     /* shared memory address (PCI only) */
 285        u32 phys_memory_base;
 286        bool shared_mem_requested;
 287
 288        unsigned char* lcr_base;        /* local config registers (PCI only) */
 289        u32 phys_lcr_base;
 290        u32 lcr_offset;
 291        bool lcr_mem_requested;
 292
 293        u32 misc_ctrl_value;
 294        char *flag_buf;
 295        bool drop_rts_on_tx_done;
 296
 297        bool loopmode_insert_requested;
 298        bool loopmode_send_done_requested;
 299        
 300        struct  _input_signal_events    input_signal_events;
 301
 302        /* generic HDLC device parts */
 303        int netcount;
 304        spinlock_t netlock;
 305
 306#if SYNCLINK_GENERIC_HDLC
 307        struct net_device *netdev;
 308#endif
 309};
 310
 311#define MGSL_MAGIC 0x5401
 312
 313/*
 314 * The size of the serial xmit buffer is 1 page, or 4096 bytes
 315 */
 316#ifndef SERIAL_XMIT_SIZE
 317#define SERIAL_XMIT_SIZE 4096
 318#endif
 319
 320/*
 321 * These macros define the offsets used in calculating the
 322 * I/O address of the specified USC registers.
 323 */
 324
 325
 326#define DCPIN 2         /* Bit 1 of I/O address */
 327#define SDPIN 4         /* Bit 2 of I/O address */
 328
 329#define DCAR 0          /* DMA command/address register */
 330#define CCAR SDPIN              /* channel command/address register */
 331#define DATAREG DCPIN + SDPIN   /* serial data register */
 332#define MSBONLY 0x41
 333#define LSBONLY 0x40
 334
 335/*
 336 * These macros define the register address (ordinal number)
 337 * used for writing address/value pairs to the USC.
 338 */
 339
 340#define CMR     0x02    /* Channel mode Register */
 341#define CCSR    0x04    /* Channel Command/status Register */
 342#define CCR     0x06    /* Channel Control Register */
 343#define PSR     0x08    /* Port status Register */
 344#define PCR     0x0a    /* Port Control Register */
 345#define TMDR    0x0c    /* Test mode Data Register */
 346#define TMCR    0x0e    /* Test mode Control Register */
 347#define CMCR    0x10    /* Clock mode Control Register */
 348#define HCR     0x12    /* Hardware Configuration Register */
 349#define IVR     0x14    /* Interrupt Vector Register */
 350#define IOCR    0x16    /* Input/Output Control Register */
 351#define ICR     0x18    /* Interrupt Control Register */
 352#define DCCR    0x1a    /* Daisy Chain Control Register */
 353#define MISR    0x1c    /* Misc Interrupt status Register */
 354#define SICR    0x1e    /* status Interrupt Control Register */
 355#define RDR     0x20    /* Receive Data Register */
 356#define RMR     0x22    /* Receive mode Register */
 357#define RCSR    0x24    /* Receive Command/status Register */
 358#define RICR    0x26    /* Receive Interrupt Control Register */
 359#define RSR     0x28    /* Receive Sync Register */
 360#define RCLR    0x2a    /* Receive count Limit Register */
 361#define RCCR    0x2c    /* Receive Character count Register */
 362#define TC0R    0x2e    /* Time Constant 0 Register */
 363#define TDR     0x30    /* Transmit Data Register */
 364#define TMR     0x32    /* Transmit mode Register */
 365#define TCSR    0x34    /* Transmit Command/status Register */
 366#define TICR    0x36    /* Transmit Interrupt Control Register */
 367#define TSR     0x38    /* Transmit Sync Register */
 368#define TCLR    0x3a    /* Transmit count Limit Register */
 369#define TCCR    0x3c    /* Transmit Character count Register */
 370#define TC1R    0x3e    /* Time Constant 1 Register */
 371
 372
 373/*
 374 * MACRO DEFINITIONS FOR DMA REGISTERS
 375 */
 376
 377#define DCR     0x06    /* DMA Control Register (shared) */
 378#define DACR    0x08    /* DMA Array count Register (shared) */
 379#define BDCR    0x12    /* Burst/Dwell Control Register (shared) */
 380#define DIVR    0x14    /* DMA Interrupt Vector Register (shared) */    
 381#define DICR    0x18    /* DMA Interrupt Control Register (shared) */
 382#define CDIR    0x1a    /* Clear DMA Interrupt Register (shared) */
 383#define SDIR    0x1c    /* Set DMA Interrupt Register (shared) */
 384
 385#define TDMR    0x02    /* Transmit DMA mode Register */
 386#define TDIAR   0x1e    /* Transmit DMA Interrupt Arm Register */
 387#define TBCR    0x2a    /* Transmit Byte count Register */
 388#define TARL    0x2c    /* Transmit Address Register (low) */
 389#define TARU    0x2e    /* Transmit Address Register (high) */
 390#define NTBCR   0x3a    /* Next Transmit Byte count Register */
 391#define NTARL   0x3c    /* Next Transmit Address Register (low) */
 392#define NTARU   0x3e    /* Next Transmit Address Register (high) */
 393
 394#define RDMR    0x82    /* Receive DMA mode Register (non-shared) */
 395#define RDIAR   0x9e    /* Receive DMA Interrupt Arm Register */
 396#define RBCR    0xaa    /* Receive Byte count Register */
 397#define RARL    0xac    /* Receive Address Register (low) */
 398#define RARU    0xae    /* Receive Address Register (high) */
 399#define NRBCR   0xba    /* Next Receive Byte count Register */
 400#define NRARL   0xbc    /* Next Receive Address Register (low) */
 401#define NRARU   0xbe    /* Next Receive Address Register (high) */
 402
 403
 404/*
 405 * MACRO DEFINITIONS FOR MODEM STATUS BITS
 406 */
 407
 408#define MODEMSTATUS_DTR 0x80
 409#define MODEMSTATUS_DSR 0x40
 410#define MODEMSTATUS_RTS 0x20
 411#define MODEMSTATUS_CTS 0x10
 412#define MODEMSTATUS_RI  0x04
 413#define MODEMSTATUS_DCD 0x01
 414
 415
 416/*
 417 * Channel Command/Address Register (CCAR) Command Codes
 418 */
 419
 420#define RTCmd_Null                      0x0000
 421#define RTCmd_ResetHighestIus           0x1000
 422#define RTCmd_TriggerChannelLoadDma     0x2000
 423#define RTCmd_TriggerRxDma              0x2800
 424#define RTCmd_TriggerTxDma              0x3000
 425#define RTCmd_TriggerRxAndTxDma         0x3800
 426#define RTCmd_PurgeRxFifo               0x4800
 427#define RTCmd_PurgeTxFifo               0x5000
 428#define RTCmd_PurgeRxAndTxFifo          0x5800
 429#define RTCmd_LoadRcc                   0x6800
 430#define RTCmd_LoadTcc                   0x7000
 431#define RTCmd_LoadRccAndTcc             0x7800
 432#define RTCmd_LoadTC0                   0x8800
 433#define RTCmd_LoadTC1                   0x9000
 434#define RTCmd_LoadTC0AndTC1             0x9800
 435#define RTCmd_SerialDataLSBFirst        0xa000
 436#define RTCmd_SerialDataMSBFirst        0xa800
 437#define RTCmd_SelectBigEndian           0xb000
 438#define RTCmd_SelectLittleEndian        0xb800
 439
 440
 441/*
 442 * DMA Command/Address Register (DCAR) Command Codes
 443 */
 444
 445#define DmaCmd_Null                     0x0000
 446#define DmaCmd_ResetTxChannel           0x1000
 447#define DmaCmd_ResetRxChannel           0x1200
 448#define DmaCmd_StartTxChannel           0x2000
 449#define DmaCmd_StartRxChannel           0x2200
 450#define DmaCmd_ContinueTxChannel        0x3000
 451#define DmaCmd_ContinueRxChannel        0x3200
 452#define DmaCmd_PauseTxChannel           0x4000
 453#define DmaCmd_PauseRxChannel           0x4200
 454#define DmaCmd_AbortTxChannel           0x5000
 455#define DmaCmd_AbortRxChannel           0x5200
 456#define DmaCmd_InitTxChannel            0x7000
 457#define DmaCmd_InitRxChannel            0x7200
 458#define DmaCmd_ResetHighestDmaIus       0x8000
 459#define DmaCmd_ResetAllChannels         0x9000
 460#define DmaCmd_StartAllChannels         0xa000
 461#define DmaCmd_ContinueAllChannels      0xb000
 462#define DmaCmd_PauseAllChannels         0xc000
 463#define DmaCmd_AbortAllChannels         0xd000
 464#define DmaCmd_InitAllChannels          0xf000
 465
 466#define TCmd_Null                       0x0000
 467#define TCmd_ClearTxCRC                 0x2000
 468#define TCmd_SelectTicrTtsaData         0x4000
 469#define TCmd_SelectTicrTxFifostatus     0x5000
 470#define TCmd_SelectTicrIntLevel         0x6000
 471#define TCmd_SelectTicrdma_level                0x7000
 472#define TCmd_SendFrame                  0x8000
 473#define TCmd_SendAbort                  0x9000
 474#define TCmd_EnableDleInsertion         0xc000
 475#define TCmd_DisableDleInsertion        0xd000
 476#define TCmd_ClearEofEom                0xe000
 477#define TCmd_SetEofEom                  0xf000
 478
 479#define RCmd_Null                       0x0000
 480#define RCmd_ClearRxCRC                 0x2000
 481#define RCmd_EnterHuntmode              0x3000
 482#define RCmd_SelectRicrRtsaData         0x4000
 483#define RCmd_SelectRicrRxFifostatus     0x5000
 484#define RCmd_SelectRicrIntLevel         0x6000
 485#define RCmd_SelectRicrdma_level                0x7000
 486
 487/*
 488 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
 489 */
 490 
 491#define RECEIVE_STATUS          BIT5
 492#define RECEIVE_DATA            BIT4
 493#define TRANSMIT_STATUS         BIT3
 494#define TRANSMIT_DATA           BIT2
 495#define IO_PIN                  BIT1
 496#define MISC                    BIT0
 497
 498
 499/*
 500 * Receive status Bits in Receive Command/status Register RCSR
 501 */
 502
 503#define RXSTATUS_SHORT_FRAME            BIT8
 504#define RXSTATUS_CODE_VIOLATION         BIT8
 505#define RXSTATUS_EXITED_HUNT            BIT7
 506#define RXSTATUS_IDLE_RECEIVED          BIT6
 507#define RXSTATUS_BREAK_RECEIVED         BIT5
 508#define RXSTATUS_ABORT_RECEIVED         BIT5
 509#define RXSTATUS_RXBOUND                BIT4
 510#define RXSTATUS_CRC_ERROR              BIT3
 511#define RXSTATUS_FRAMING_ERROR          BIT3
 512#define RXSTATUS_ABORT                  BIT2
 513#define RXSTATUS_PARITY_ERROR           BIT2
 514#define RXSTATUS_OVERRUN                BIT1
 515#define RXSTATUS_DATA_AVAILABLE         BIT0
 516#define RXSTATUS_ALL                    0x01f6
 517#define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
 518
 519/*
 520 * Values for setting transmit idle mode in 
 521 * Transmit Control/status Register (TCSR)
 522 */
 523#define IDLEMODE_FLAGS                  0x0000
 524#define IDLEMODE_ALT_ONE_ZERO           0x0100
 525#define IDLEMODE_ZERO                   0x0200
 526#define IDLEMODE_ONE                    0x0300
 527#define IDLEMODE_ALT_MARK_SPACE         0x0500
 528#define IDLEMODE_SPACE                  0x0600
 529#define IDLEMODE_MARK                   0x0700
 530#define IDLEMODE_MASK                   0x0700
 531
 532/*
 533 * IUSC revision identifiers
 534 */
 535#define IUSC_SL1660                     0x4d44
 536#define IUSC_PRE_SL1660                 0x4553
 537
 538/*
 539 * Transmit status Bits in Transmit Command/status Register (TCSR)
 540 */
 541
 542#define TCSR_PRESERVE                   0x0F00
 543
 544#define TCSR_UNDERWAIT                  BIT11
 545#define TXSTATUS_PREAMBLE_SENT          BIT7
 546#define TXSTATUS_IDLE_SENT              BIT6
 547#define TXSTATUS_ABORT_SENT             BIT5
 548#define TXSTATUS_EOF_SENT               BIT4
 549#define TXSTATUS_EOM_SENT               BIT4
 550#define TXSTATUS_CRC_SENT               BIT3
 551#define TXSTATUS_ALL_SENT               BIT2
 552#define TXSTATUS_UNDERRUN               BIT1
 553#define TXSTATUS_FIFO_EMPTY             BIT0
 554#define TXSTATUS_ALL                    0x00fa
 555#define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
 556                                
 557
 558#define MISCSTATUS_RXC_LATCHED          BIT15
 559#define MISCSTATUS_RXC                  BIT14
 560#define MISCSTATUS_TXC_LATCHED          BIT13
 561#define MISCSTATUS_TXC                  BIT12
 562#define MISCSTATUS_RI_LATCHED           BIT11
 563#define MISCSTATUS_RI                   BIT10
 564#define MISCSTATUS_DSR_LATCHED          BIT9
 565#define MISCSTATUS_DSR                  BIT8
 566#define MISCSTATUS_DCD_LATCHED          BIT7
 567#define MISCSTATUS_DCD                  BIT6
 568#define MISCSTATUS_CTS_LATCHED          BIT5
 569#define MISCSTATUS_CTS                  BIT4
 570#define MISCSTATUS_RCC_UNDERRUN         BIT3
 571#define MISCSTATUS_DPLL_NO_SYNC         BIT2
 572#define MISCSTATUS_BRG1_ZERO            BIT1
 573#define MISCSTATUS_BRG0_ZERO            BIT0
 574
 575#define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
 576#define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
 577
 578#define SICR_RXC_ACTIVE                 BIT15
 579#define SICR_RXC_INACTIVE               BIT14
 580#define SICR_RXC                        (BIT15+BIT14)
 581#define SICR_TXC_ACTIVE                 BIT13
 582#define SICR_TXC_INACTIVE               BIT12
 583#define SICR_TXC                        (BIT13+BIT12)
 584#define SICR_RI_ACTIVE                  BIT11
 585#define SICR_RI_INACTIVE                BIT10
 586#define SICR_RI                         (BIT11+BIT10)
 587#define SICR_DSR_ACTIVE                 BIT9
 588#define SICR_DSR_INACTIVE               BIT8
 589#define SICR_DSR                        (BIT9+BIT8)
 590#define SICR_DCD_ACTIVE                 BIT7
 591#define SICR_DCD_INACTIVE               BIT6
 592#define SICR_DCD                        (BIT7+BIT6)
 593#define SICR_CTS_ACTIVE                 BIT5
 594#define SICR_CTS_INACTIVE               BIT4
 595#define SICR_CTS                        (BIT5+BIT4)
 596#define SICR_RCC_UNDERFLOW              BIT3
 597#define SICR_DPLL_NO_SYNC               BIT2
 598#define SICR_BRG1_ZERO                  BIT1
 599#define SICR_BRG0_ZERO                  BIT0
 600
 601void usc_DisableMasterIrqBit( struct mgsl_struct *info );
 602void usc_EnableMasterIrqBit( struct mgsl_struct *info );
 603void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
 604void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
 605void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
 606
 607#define usc_EnableInterrupts( a, b ) \
 608        usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
 609
 610#define usc_DisableInterrupts( a, b ) \
 611        usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
 612
 613#define usc_EnableMasterIrqBit(a) \
 614        usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
 615
 616#define usc_DisableMasterIrqBit(a) \
 617        usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
 618
 619#define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
 620
 621/*
 622 * Transmit status Bits in Transmit Control status Register (TCSR)
 623 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
 624 */
 625
 626#define TXSTATUS_PREAMBLE_SENT  BIT7
 627#define TXSTATUS_IDLE_SENT      BIT6
 628#define TXSTATUS_ABORT_SENT     BIT5
 629#define TXSTATUS_EOF            BIT4
 630#define TXSTATUS_CRC_SENT       BIT3
 631#define TXSTATUS_ALL_SENT       BIT2
 632#define TXSTATUS_UNDERRUN       BIT1
 633#define TXSTATUS_FIFO_EMPTY     BIT0
 634
 635#define DICR_MASTER             BIT15
 636#define DICR_TRANSMIT           BIT0
 637#define DICR_RECEIVE            BIT1
 638
 639#define usc_EnableDmaInterrupts(a,b) \
 640        usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
 641
 642#define usc_DisableDmaInterrupts(a,b) \
 643        usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
 644
 645#define usc_EnableStatusIrqs(a,b) \
 646        usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
 647
 648#define usc_DisablestatusIrqs(a,b) \
 649        usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
 650
 651/* Transmit status Bits in Transmit Control status Register (TCSR) */
 652/* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
 653
 654
 655#define DISABLE_UNCONDITIONAL    0
 656#define DISABLE_END_OF_FRAME     1
 657#define ENABLE_UNCONDITIONAL     2
 658#define ENABLE_AUTO_CTS          3
 659#define ENABLE_AUTO_DCD          3
 660#define usc_EnableTransmitter(a,b) \
 661        usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
 662#define usc_EnableReceiver(a,b) \
 663        usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
 664
 665static u16  usc_InDmaReg( struct mgsl_struct *info, u16 Port );
 666static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
 667static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
 668
 669static u16  usc_InReg( struct mgsl_struct *info, u16 Port );
 670static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
 671static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
 672void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
 673void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
 674
 675#define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
 676#define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
 677
 678#define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
 679
 680static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
 681static void usc_start_receiver( struct mgsl_struct *info );
 682static void usc_stop_receiver( struct mgsl_struct *info );
 683
 684static void usc_start_transmitter( struct mgsl_struct *info );
 685static void usc_stop_transmitter( struct mgsl_struct *info );
 686static void usc_set_txidle( struct mgsl_struct *info );
 687static void usc_load_txfifo( struct mgsl_struct *info );
 688
 689static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
 690static void usc_enable_loopback( struct mgsl_struct *info, int enable );
 691
 692static void usc_get_serial_signals( struct mgsl_struct *info );
 693static void usc_set_serial_signals( struct mgsl_struct *info );
 694
 695static void usc_reset( struct mgsl_struct *info );
 696
 697static void usc_set_sync_mode( struct mgsl_struct *info );
 698static void usc_set_sdlc_mode( struct mgsl_struct *info );
 699static void usc_set_async_mode( struct mgsl_struct *info );
 700static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
 701
 702static void usc_loopback_frame( struct mgsl_struct *info );
 703
 704static void mgsl_tx_timeout(unsigned long context);
 705
 706
 707static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
 708static void usc_loopmode_insert_request( struct mgsl_struct * info );
 709static int usc_loopmode_active( struct mgsl_struct * info);
 710static void usc_loopmode_send_done( struct mgsl_struct * info );
 711
 712static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
 713
 714#if SYNCLINK_GENERIC_HDLC
 715#define dev_to_port(D) (dev_to_hdlc(D)->priv)
 716static void hdlcdev_tx_done(struct mgsl_struct *info);
 717static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
 718static int  hdlcdev_init(struct mgsl_struct *info);
 719static void hdlcdev_exit(struct mgsl_struct *info);
 720#endif
 721
 722/*
 723 * Defines a BUS descriptor value for the PCI adapter
 724 * local bus address ranges.
 725 */
 726
 727#define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
 728(0x00400020 + \
 729((WrHold) << 30) + \
 730((WrDly)  << 28) + \
 731((RdDly)  << 26) + \
 732((Nwdd)   << 20) + \
 733((Nwad)   << 15) + \
 734((Nxda)   << 13) + \
 735((Nrdd)   << 11) + \
 736((Nrad)   <<  6) )
 737
 738static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
 739
 740/*
 741 * Adapter diagnostic routines
 742 */
 743static bool mgsl_register_test( struct mgsl_struct *info );
 744static bool mgsl_irq_test( struct mgsl_struct *info );
 745static bool mgsl_dma_test( struct mgsl_struct *info );
 746static bool mgsl_memory_test( struct mgsl_struct *info );
 747static int mgsl_adapter_test( struct mgsl_struct *info );
 748
 749/*
 750 * device and resource management routines
 751 */
 752static int mgsl_claim_resources(struct mgsl_struct *info);
 753static void mgsl_release_resources(struct mgsl_struct *info);
 754static void mgsl_add_device(struct mgsl_struct *info);
 755static struct mgsl_struct* mgsl_allocate_device(void);
 756
 757/*
 758 * DMA buffer manupulation functions.
 759 */
 760static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
 761static bool mgsl_get_rx_frame( struct mgsl_struct *info );
 762static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
 763static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
 764static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
 765static int num_free_tx_dma_buffers(struct mgsl_struct *info);
 766static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
 767static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
 768
 769/*
 770 * DMA and Shared Memory buffer allocation and formatting
 771 */
 772static int  mgsl_allocate_dma_buffers(struct mgsl_struct *info);
 773static void mgsl_free_dma_buffers(struct mgsl_struct *info);
 774static int  mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
 775static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
 776static int  mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
 777static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
 778static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
 779static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
 780static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
 781static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
 782static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
 783static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
 784
 785/*
 786 * Bottom half interrupt handlers
 787 */
 788static void mgsl_bh_handler(struct work_struct *work);
 789static void mgsl_bh_receive(struct mgsl_struct *info);
 790static void mgsl_bh_transmit(struct mgsl_struct *info);
 791static void mgsl_bh_status(struct mgsl_struct *info);
 792
 793/*
 794 * Interrupt handler routines and dispatch table.
 795 */
 796static void mgsl_isr_null( struct mgsl_struct *info );
 797static void mgsl_isr_transmit_data( struct mgsl_struct *info );
 798static void mgsl_isr_receive_data( struct mgsl_struct *info );
 799static void mgsl_isr_receive_status( struct mgsl_struct *info );
 800static void mgsl_isr_transmit_status( struct mgsl_struct *info );
 801static void mgsl_isr_io_pin( struct mgsl_struct *info );
 802static void mgsl_isr_misc( struct mgsl_struct *info );
 803static void mgsl_isr_receive_dma( struct mgsl_struct *info );
 804static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
 805
 806typedef void (*isr_dispatch_func)(struct mgsl_struct *);
 807
 808static isr_dispatch_func UscIsrTable[7] =
 809{
 810        mgsl_isr_null,
 811        mgsl_isr_misc,
 812        mgsl_isr_io_pin,
 813        mgsl_isr_transmit_data,
 814        mgsl_isr_transmit_status,
 815        mgsl_isr_receive_data,
 816        mgsl_isr_receive_status
 817};
 818
 819/*
 820 * ioctl call handlers
 821 */
 822static int tiocmget(struct tty_struct *tty);
 823static int tiocmset(struct tty_struct *tty,
 824                    unsigned int set, unsigned int clear);
 825static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
 826        __user *user_icount);
 827static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS  __user *user_params);
 828static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS  __user *new_params);
 829static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
 830static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
 831static int mgsl_txenable(struct mgsl_struct * info, int enable);
 832static int mgsl_txabort(struct mgsl_struct * info);
 833static int mgsl_rxenable(struct mgsl_struct * info, int enable);
 834static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
 835static int mgsl_loopmode_send_done( struct mgsl_struct * info );
 836
 837/* set non-zero on successful registration with PCI subsystem */
 838static bool pci_registered;
 839
 840/*
 841 * Global linked list of SyncLink devices
 842 */
 843static struct mgsl_struct *mgsl_device_list;
 844static int mgsl_device_count;
 845
 846/*
 847 * Set this param to non-zero to load eax with the
 848 * .text section address and breakpoint on module load.
 849 * This is useful for use with gdb and add-symbol-file command.
 850 */
 851static bool break_on_load;
 852
 853/*
 854 * Driver major number, defaults to zero to get auto
 855 * assigned major number. May be forced as module parameter.
 856 */
 857static int ttymajor;
 858
 859/*
 860 * Array of user specified options for ISA adapters.
 861 */
 862static int io[MAX_ISA_DEVICES];
 863static int irq[MAX_ISA_DEVICES];
 864static int dma[MAX_ISA_DEVICES];
 865static int debug_level;
 866static int maxframe[MAX_TOTAL_DEVICES];
 867static int txdmabufs[MAX_TOTAL_DEVICES];
 868static int txholdbufs[MAX_TOTAL_DEVICES];
 869        
 870module_param(break_on_load, bool, 0);
 871module_param(ttymajor, int, 0);
 872module_param_array(io, int, NULL, 0);
 873module_param_array(irq, int, NULL, 0);
 874module_param_array(dma, int, NULL, 0);
 875module_param(debug_level, int, 0);
 876module_param_array(maxframe, int, NULL, 0);
 877module_param_array(txdmabufs, int, NULL, 0);
 878module_param_array(txholdbufs, int, NULL, 0);
 879
 880static char *driver_name = "SyncLink serial driver";
 881static char *driver_version = "$Revision: 4.38 $";
 882
 883static int synclink_init_one (struct pci_dev *dev,
 884                                     const struct pci_device_id *ent);
 885static void synclink_remove_one (struct pci_dev *dev);
 886
 887static struct pci_device_id synclink_pci_tbl[] = {
 888        { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
 889        { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
 890        { 0, }, /* terminate list */
 891};
 892MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
 893
 894MODULE_LICENSE("GPL");
 895
 896static struct pci_driver synclink_pci_driver = {
 897        .name           = "synclink",
 898        .id_table       = synclink_pci_tbl,
 899        .probe          = synclink_init_one,
 900        .remove         = synclink_remove_one,
 901};
 902
 903static struct tty_driver *serial_driver;
 904
 905/* number of characters left in xmit buffer before we ask for more */
 906#define WAKEUP_CHARS 256
 907
 908
 909static void mgsl_change_params(struct mgsl_struct *info);
 910static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
 911
 912/*
 913 * 1st function defined in .text section. Calling this function in
 914 * init_module() followed by a breakpoint allows a remote debugger
 915 * (gdb) to get the .text address for the add-symbol-file command.
 916 * This allows remote debugging of dynamically loadable modules.
 917 */
 918static void* mgsl_get_text_ptr(void)
 919{
 920        return mgsl_get_text_ptr;
 921}
 922
 923static inline int mgsl_paranoia_check(struct mgsl_struct *info,
 924                                        char *name, const char *routine)
 925{
 926#ifdef MGSL_PARANOIA_CHECK
 927        static const char *badmagic =
 928                "Warning: bad magic number for mgsl struct (%s) in %s\n";
 929        static const char *badinfo =
 930                "Warning: null mgsl_struct for (%s) in %s\n";
 931
 932        if (!info) {
 933                printk(badinfo, name, routine);
 934                return 1;
 935        }
 936        if (info->magic != MGSL_MAGIC) {
 937                printk(badmagic, name, routine);
 938                return 1;
 939        }
 940#else
 941        if (!info)
 942                return 1;
 943#endif
 944        return 0;
 945}
 946
 947/**
 948 * line discipline callback wrappers
 949 *
 950 * The wrappers maintain line discipline references
 951 * while calling into the line discipline.
 952 *
 953 * ldisc_receive_buf  - pass receive data to line discipline
 954 */
 955
 956static void ldisc_receive_buf(struct tty_struct *tty,
 957                              const __u8 *data, char *flags, int count)
 958{
 959        struct tty_ldisc *ld;
 960        if (!tty)
 961                return;
 962        ld = tty_ldisc_ref(tty);
 963        if (ld) {
 964                if (ld->ops->receive_buf)
 965                        ld->ops->receive_buf(tty, data, flags, count);
 966                tty_ldisc_deref(ld);
 967        }
 968}
 969
 970/* mgsl_stop()          throttle (stop) transmitter
 971 *      
 972 * Arguments:           tty     pointer to tty info structure
 973 * Return Value:        None
 974 */
 975static void mgsl_stop(struct tty_struct *tty)
 976{
 977        struct mgsl_struct *info = tty->driver_data;
 978        unsigned long flags;
 979        
 980        if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
 981                return;
 982        
 983        if ( debug_level >= DEBUG_LEVEL_INFO )
 984                printk("mgsl_stop(%s)\n",info->device_name);    
 985                
 986        spin_lock_irqsave(&info->irq_spinlock,flags);
 987        if (info->tx_enabled)
 988                usc_stop_transmitter(info);
 989        spin_unlock_irqrestore(&info->irq_spinlock,flags);
 990        
 991}       /* end of mgsl_stop() */
 992
 993/* mgsl_start()         release (start) transmitter
 994 *      
 995 * Arguments:           tty     pointer to tty info structure
 996 * Return Value:        None
 997 */
 998static void mgsl_start(struct tty_struct *tty)
 999{
1000        struct mgsl_struct *info = tty->driver_data;
1001        unsigned long flags;
1002        
1003        if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1004                return;
1005        
1006        if ( debug_level >= DEBUG_LEVEL_INFO )
1007                printk("mgsl_start(%s)\n",info->device_name);   
1008                
1009        spin_lock_irqsave(&info->irq_spinlock,flags);
1010        if (!info->tx_enabled)
1011                usc_start_transmitter(info);
1012        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1013        
1014}       /* end of mgsl_start() */
1015
1016/*
1017 * Bottom half work queue access functions
1018 */
1019
1020/* mgsl_bh_action()     Return next bottom half action to perform.
1021 * Return Value:        BH action code or 0 if nothing to do.
1022 */
1023static int mgsl_bh_action(struct mgsl_struct *info)
1024{
1025        unsigned long flags;
1026        int rc = 0;
1027        
1028        spin_lock_irqsave(&info->irq_spinlock,flags);
1029
1030        if (info->pending_bh & BH_RECEIVE) {
1031                info->pending_bh &= ~BH_RECEIVE;
1032                rc = BH_RECEIVE;
1033        } else if (info->pending_bh & BH_TRANSMIT) {
1034                info->pending_bh &= ~BH_TRANSMIT;
1035                rc = BH_TRANSMIT;
1036        } else if (info->pending_bh & BH_STATUS) {
1037                info->pending_bh &= ~BH_STATUS;
1038                rc = BH_STATUS;
1039        }
1040
1041        if (!rc) {
1042                /* Mark BH routine as complete */
1043                info->bh_running = false;
1044                info->bh_requested = false;
1045        }
1046        
1047        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1048        
1049        return rc;
1050}
1051
1052/*
1053 *      Perform bottom half processing of work items queued by ISR.
1054 */
1055static void mgsl_bh_handler(struct work_struct *work)
1056{
1057        struct mgsl_struct *info =
1058                container_of(work, struct mgsl_struct, task);
1059        int action;
1060
1061        if ( debug_level >= DEBUG_LEVEL_BH )
1062                printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1063                        __FILE__,__LINE__,info->device_name);
1064        
1065        info->bh_running = true;
1066
1067        while((action = mgsl_bh_action(info)) != 0) {
1068        
1069                /* Process work item */
1070                if ( debug_level >= DEBUG_LEVEL_BH )
1071                        printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1072                                __FILE__,__LINE__,action);
1073
1074                switch (action) {
1075                
1076                case BH_RECEIVE:
1077                        mgsl_bh_receive(info);
1078                        break;
1079                case BH_TRANSMIT:
1080                        mgsl_bh_transmit(info);
1081                        break;
1082                case BH_STATUS:
1083                        mgsl_bh_status(info);
1084                        break;
1085                default:
1086                        /* unknown work item ID */
1087                        printk("Unknown work item ID=%08X!\n", action);
1088                        break;
1089                }
1090        }
1091
1092        if ( debug_level >= DEBUG_LEVEL_BH )
1093                printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1094                        __FILE__,__LINE__,info->device_name);
1095}
1096
1097static void mgsl_bh_receive(struct mgsl_struct *info)
1098{
1099        bool (*get_rx_frame)(struct mgsl_struct *info) =
1100                (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1101
1102        if ( debug_level >= DEBUG_LEVEL_BH )
1103                printk( "%s(%d):mgsl_bh_receive(%s)\n",
1104                        __FILE__,__LINE__,info->device_name);
1105        
1106        do
1107        {
1108                if (info->rx_rcc_underrun) {
1109                        unsigned long flags;
1110                        spin_lock_irqsave(&info->irq_spinlock,flags);
1111                        usc_start_receiver(info);
1112                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1113                        return;
1114                }
1115        } while(get_rx_frame(info));
1116}
1117
1118static void mgsl_bh_transmit(struct mgsl_struct *info)
1119{
1120        struct tty_struct *tty = info->port.tty;
1121        unsigned long flags;
1122        
1123        if ( debug_level >= DEBUG_LEVEL_BH )
1124                printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1125                        __FILE__,__LINE__,info->device_name);
1126
1127        if (tty)
1128                tty_wakeup(tty);
1129
1130        /* if transmitter idle and loopmode_send_done_requested
1131         * then start echoing RxD to TxD
1132         */
1133        spin_lock_irqsave(&info->irq_spinlock,flags);
1134        if ( !info->tx_active && info->loopmode_send_done_requested )
1135                usc_loopmode_send_done( info );
1136        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1137}
1138
1139static void mgsl_bh_status(struct mgsl_struct *info)
1140{
1141        if ( debug_level >= DEBUG_LEVEL_BH )
1142                printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1143                        __FILE__,__LINE__,info->device_name);
1144
1145        info->ri_chkcount = 0;
1146        info->dsr_chkcount = 0;
1147        info->dcd_chkcount = 0;
1148        info->cts_chkcount = 0;
1149}
1150
1151/* mgsl_isr_receive_status()
1152 * 
1153 *      Service a receive status interrupt. The type of status
1154 *      interrupt is indicated by the state of the RCSR.
1155 *      This is only used for HDLC mode.
1156 *
1157 * Arguments:           info    pointer to device instance data
1158 * Return Value:        None
1159 */
1160static void mgsl_isr_receive_status( struct mgsl_struct *info )
1161{
1162        u16 status = usc_InReg( info, RCSR );
1163
1164        if ( debug_level >= DEBUG_LEVEL_ISR )   
1165                printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1166                        __FILE__,__LINE__,status);
1167                        
1168        if ( (status & RXSTATUS_ABORT_RECEIVED) && 
1169                info->loopmode_insert_requested &&
1170                usc_loopmode_active(info) )
1171        {
1172                ++info->icount.rxabort;
1173                info->loopmode_insert_requested = false;
1174 
1175                /* clear CMR:13 to start echoing RxD to TxD */
1176                info->cmr_value &= ~BIT13;
1177                usc_OutReg(info, CMR, info->cmr_value);
1178 
1179                /* disable received abort irq (no longer required) */
1180                usc_OutReg(info, RICR,
1181                        (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1182        }
1183
1184        if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1185                if (status & RXSTATUS_EXITED_HUNT)
1186                        info->icount.exithunt++;
1187                if (status & RXSTATUS_IDLE_RECEIVED)
1188                        info->icount.rxidle++;
1189                wake_up_interruptible(&info->event_wait_q);
1190        }
1191
1192        if (status & RXSTATUS_OVERRUN){
1193                info->icount.rxover++;
1194                usc_process_rxoverrun_sync( info );
1195        }
1196
1197        usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1198        usc_UnlatchRxstatusBits( info, status );
1199
1200}       /* end of mgsl_isr_receive_status() */
1201
1202/* mgsl_isr_transmit_status()
1203 * 
1204 *      Service a transmit status interrupt
1205 *      HDLC mode :end of transmit frame
1206 *      Async mode:all data is sent
1207 *      transmit status is indicated by bits in the TCSR.
1208 * 
1209 * Arguments:           info           pointer to device instance data
1210 * Return Value:        None
1211 */
1212static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1213{
1214        u16 status = usc_InReg( info, TCSR );
1215
1216        if ( debug_level >= DEBUG_LEVEL_ISR )   
1217                printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1218                        __FILE__,__LINE__,status);
1219        
1220        usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1221        usc_UnlatchTxstatusBits( info, status );
1222        
1223        if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1224        {
1225                /* finished sending HDLC abort. This may leave  */
1226                /* the TxFifo with data from the aborted frame  */
1227                /* so purge the TxFifo. Also shutdown the DMA   */
1228                /* channel in case there is data remaining in   */
1229                /* the DMA buffer                               */
1230                usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1231                usc_RTCmd( info, RTCmd_PurgeTxFifo );
1232        }
1233 
1234        if ( status & TXSTATUS_EOF_SENT )
1235                info->icount.txok++;
1236        else if ( status & TXSTATUS_UNDERRUN )
1237                info->icount.txunder++;
1238        else if ( status & TXSTATUS_ABORT_SENT )
1239                info->icount.txabort++;
1240        else
1241                info->icount.txunder++;
1242                        
1243        info->tx_active = false;
1244        info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1245        del_timer(&info->tx_timer);     
1246        
1247        if ( info->drop_rts_on_tx_done ) {
1248                usc_get_serial_signals( info );
1249                if ( info->serial_signals & SerialSignal_RTS ) {
1250                        info->serial_signals &= ~SerialSignal_RTS;
1251                        usc_set_serial_signals( info );
1252                }
1253                info->drop_rts_on_tx_done = false;
1254        }
1255
1256#if SYNCLINK_GENERIC_HDLC
1257        if (info->netcount)
1258                hdlcdev_tx_done(info);
1259        else 
1260#endif
1261        {
1262                if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1263                        usc_stop_transmitter(info);
1264                        return;
1265                }
1266                info->pending_bh |= BH_TRANSMIT;
1267        }
1268
1269}       /* end of mgsl_isr_transmit_status() */
1270
1271/* mgsl_isr_io_pin()
1272 * 
1273 *      Service an Input/Output pin interrupt. The type of
1274 *      interrupt is indicated by bits in the MISR
1275 *      
1276 * Arguments:           info           pointer to device instance data
1277 * Return Value:        None
1278 */
1279static void mgsl_isr_io_pin( struct mgsl_struct *info )
1280{
1281        struct  mgsl_icount *icount;
1282        u16 status = usc_InReg( info, MISR );
1283
1284        if ( debug_level >= DEBUG_LEVEL_ISR )   
1285                printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1286                        __FILE__,__LINE__,status);
1287                        
1288        usc_ClearIrqPendingBits( info, IO_PIN );
1289        usc_UnlatchIostatusBits( info, status );
1290
1291        if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1292                      MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1293                icount = &info->icount;
1294                /* update input line counters */
1295                if (status & MISCSTATUS_RI_LATCHED) {
1296                        if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1297                                usc_DisablestatusIrqs(info,SICR_RI);
1298                        icount->rng++;
1299                        if ( status & MISCSTATUS_RI )
1300                                info->input_signal_events.ri_up++;      
1301                        else
1302                                info->input_signal_events.ri_down++;    
1303                }
1304                if (status & MISCSTATUS_DSR_LATCHED) {
1305                        if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1306                                usc_DisablestatusIrqs(info,SICR_DSR);
1307                        icount->dsr++;
1308                        if ( status & MISCSTATUS_DSR )
1309                                info->input_signal_events.dsr_up++;
1310                        else
1311                                info->input_signal_events.dsr_down++;
1312                }
1313                if (status & MISCSTATUS_DCD_LATCHED) {
1314                        if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1315                                usc_DisablestatusIrqs(info,SICR_DCD);
1316                        icount->dcd++;
1317                        if (status & MISCSTATUS_DCD) {
1318                                info->input_signal_events.dcd_up++;
1319                        } else
1320                                info->input_signal_events.dcd_down++;
1321#if SYNCLINK_GENERIC_HDLC
1322                        if (info->netcount) {
1323                                if (status & MISCSTATUS_DCD)
1324                                        netif_carrier_on(info->netdev);
1325                                else
1326                                        netif_carrier_off(info->netdev);
1327                        }
1328#endif
1329                }
1330                if (status & MISCSTATUS_CTS_LATCHED)
1331                {
1332                        if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1333                                usc_DisablestatusIrqs(info,SICR_CTS);
1334                        icount->cts++;
1335                        if ( status & MISCSTATUS_CTS )
1336                                info->input_signal_events.cts_up++;
1337                        else
1338                                info->input_signal_events.cts_down++;
1339                }
1340                wake_up_interruptible(&info->status_event_wait_q);
1341                wake_up_interruptible(&info->event_wait_q);
1342
1343                if ( (info->port.flags & ASYNC_CHECK_CD) && 
1344                     (status & MISCSTATUS_DCD_LATCHED) ) {
1345                        if ( debug_level >= DEBUG_LEVEL_ISR )
1346                                printk("%s CD now %s...", info->device_name,
1347                                       (status & MISCSTATUS_DCD) ? "on" : "off");
1348                        if (status & MISCSTATUS_DCD)
1349                                wake_up_interruptible(&info->port.open_wait);
1350                        else {
1351                                if ( debug_level >= DEBUG_LEVEL_ISR )
1352                                        printk("doing serial hangup...");
1353                                if (info->port.tty)
1354                                        tty_hangup(info->port.tty);
1355                        }
1356                }
1357        
1358                if (tty_port_cts_enabled(&info->port) &&
1359                     (status & MISCSTATUS_CTS_LATCHED) ) {
1360                        if (info->port.tty->hw_stopped) {
1361                                if (status & MISCSTATUS_CTS) {
1362                                        if ( debug_level >= DEBUG_LEVEL_ISR )
1363                                                printk("CTS tx start...");
1364                                        if (info->port.tty)
1365                                                info->port.tty->hw_stopped = 0;
1366                                        usc_start_transmitter(info);
1367                                        info->pending_bh |= BH_TRANSMIT;
1368                                        return;
1369                                }
1370                        } else {
1371                                if (!(status & MISCSTATUS_CTS)) {
1372                                        if ( debug_level >= DEBUG_LEVEL_ISR )
1373                                                printk("CTS tx stop...");
1374                                        if (info->port.tty)
1375                                                info->port.tty->hw_stopped = 1;
1376                                        usc_stop_transmitter(info);
1377                                }
1378                        }
1379                }
1380        }
1381
1382        info->pending_bh |= BH_STATUS;
1383        
1384        /* for diagnostics set IRQ flag */
1385        if ( status & MISCSTATUS_TXC_LATCHED ){
1386                usc_OutReg( info, SICR,
1387                        (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1388                usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1389                info->irq_occurred = true;
1390        }
1391
1392}       /* end of mgsl_isr_io_pin() */
1393
1394/* mgsl_isr_transmit_data()
1395 * 
1396 *      Service a transmit data interrupt (async mode only).
1397 * 
1398 * Arguments:           info    pointer to device instance data
1399 * Return Value:        None
1400 */
1401static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1402{
1403        if ( debug_level >= DEBUG_LEVEL_ISR )   
1404                printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1405                        __FILE__,__LINE__,info->xmit_cnt);
1406                        
1407        usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1408        
1409        if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1410                usc_stop_transmitter(info);
1411                return;
1412        }
1413        
1414        if ( info->xmit_cnt )
1415                usc_load_txfifo( info );
1416        else
1417                info->tx_active = false;
1418                
1419        if (info->xmit_cnt < WAKEUP_CHARS)
1420                info->pending_bh |= BH_TRANSMIT;
1421
1422}       /* end of mgsl_isr_transmit_data() */
1423
1424/* mgsl_isr_receive_data()
1425 * 
1426 *      Service a receive data interrupt. This occurs
1427 *      when operating in asynchronous interrupt transfer mode.
1428 *      The receive data FIFO is flushed to the receive data buffers. 
1429 * 
1430 * Arguments:           info            pointer to device instance data
1431 * Return Value:        None
1432 */
1433static void mgsl_isr_receive_data( struct mgsl_struct *info )
1434{
1435        int Fifocount;
1436        u16 status;
1437        int work = 0;
1438        unsigned char DataByte;
1439        struct  mgsl_icount *icount = &info->icount;
1440        
1441        if ( debug_level >= DEBUG_LEVEL_ISR )   
1442                printk("%s(%d):mgsl_isr_receive_data\n",
1443                        __FILE__,__LINE__);
1444
1445        usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1446        
1447        /* select FIFO status for RICR readback */
1448        usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1449
1450        /* clear the Wordstatus bit so that status readback */
1451        /* only reflects the status of this byte */
1452        usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1453
1454        /* flush the receive FIFO */
1455
1456        while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1457                int flag;
1458
1459                /* read one byte from RxFIFO */
1460                outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1461                      info->io_base + CCAR );
1462                DataByte = inb( info->io_base + CCAR );
1463
1464                /* get the status of the received byte */
1465                status = usc_InReg(info, RCSR);
1466                if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1467                                RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1468                        usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1469                
1470                icount->rx++;
1471                
1472                flag = 0;
1473                if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1474                                RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1475                        printk("rxerr=%04X\n",status);                                  
1476                        /* update error statistics */
1477                        if ( status & RXSTATUS_BREAK_RECEIVED ) {
1478                                status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1479                                icount->brk++;
1480                        } else if (status & RXSTATUS_PARITY_ERROR) 
1481                                icount->parity++;
1482                        else if (status & RXSTATUS_FRAMING_ERROR)
1483                                icount->frame++;
1484                        else if (status & RXSTATUS_OVERRUN) {
1485                                /* must issue purge fifo cmd before */
1486                                /* 16C32 accepts more receive chars */
1487                                usc_RTCmd(info,RTCmd_PurgeRxFifo);
1488                                icount->overrun++;
1489                        }
1490
1491                        /* discard char if tty control flags say so */                                  
1492                        if (status & info->ignore_status_mask)
1493                                continue;
1494                                
1495                        status &= info->read_status_mask;
1496                
1497                        if (status & RXSTATUS_BREAK_RECEIVED) {
1498                                flag = TTY_BREAK;
1499                                if (info->port.flags & ASYNC_SAK)
1500                                        do_SAK(info->port.tty);
1501                        } else if (status & RXSTATUS_PARITY_ERROR)
1502                                flag = TTY_PARITY;
1503                        else if (status & RXSTATUS_FRAMING_ERROR)
1504                                flag = TTY_FRAME;
1505                }       /* end of if (error) */
1506                tty_insert_flip_char(&info->port, DataByte, flag);
1507                if (status & RXSTATUS_OVERRUN) {
1508                        /* Overrun is special, since it's
1509                         * reported immediately, and doesn't
1510                         * affect the current character
1511                         */
1512                        work += tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
1513                }
1514        }
1515
1516        if ( debug_level >= DEBUG_LEVEL_ISR ) {
1517                printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1518                        __FILE__,__LINE__,icount->rx,icount->brk,
1519                        icount->parity,icount->frame,icount->overrun);
1520        }
1521                        
1522        if(work)
1523                tty_flip_buffer_push(&info->port);
1524}
1525
1526/* mgsl_isr_misc()
1527 * 
1528 *      Service a miscellaneous interrupt source.
1529 *      
1530 * Arguments:           info            pointer to device extension (instance data)
1531 * Return Value:        None
1532 */
1533static void mgsl_isr_misc( struct mgsl_struct *info )
1534{
1535        u16 status = usc_InReg( info, MISR );
1536
1537        if ( debug_level >= DEBUG_LEVEL_ISR )   
1538                printk("%s(%d):mgsl_isr_misc status=%04X\n",
1539                        __FILE__,__LINE__,status);
1540                        
1541        if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1542            (info->params.mode == MGSL_MODE_HDLC)) {
1543
1544                /* turn off receiver and rx DMA */
1545                usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1546                usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1547                usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1548                usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1549                usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1550
1551                /* schedule BH handler to restart receiver */
1552                info->pending_bh |= BH_RECEIVE;
1553                info->rx_rcc_underrun = true;
1554        }
1555
1556        usc_ClearIrqPendingBits( info, MISC );
1557        usc_UnlatchMiscstatusBits( info, status );
1558
1559}       /* end of mgsl_isr_misc() */
1560
1561/* mgsl_isr_null()
1562 *
1563 *      Services undefined interrupt vectors from the
1564 *      USC. (hence this function SHOULD never be called)
1565 * 
1566 * Arguments:           info            pointer to device extension (instance data)
1567 * Return Value:        None
1568 */
1569static void mgsl_isr_null( struct mgsl_struct *info )
1570{
1571
1572}       /* end of mgsl_isr_null() */
1573
1574/* mgsl_isr_receive_dma()
1575 * 
1576 *      Service a receive DMA channel interrupt.
1577 *      For this driver there are two sources of receive DMA interrupts
1578 *      as identified in the Receive DMA mode Register (RDMR):
1579 * 
1580 *      BIT3    EOA/EOL         End of List, all receive buffers in receive
1581 *                              buffer list have been filled (no more free buffers
1582 *                              available). The DMA controller has shut down.
1583 * 
1584 *      BIT2    EOB             End of Buffer. This interrupt occurs when a receive
1585 *                              DMA buffer is terminated in response to completion
1586 *                              of a good frame or a frame with errors. The status
1587 *                              of the frame is stored in the buffer entry in the
1588 *                              list of receive buffer entries.
1589 * 
1590 * Arguments:           info            pointer to device instance data
1591 * Return Value:        None
1592 */
1593static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1594{
1595        u16 status;
1596        
1597        /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1598        usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1599
1600        /* Read the receive DMA status to identify interrupt type. */
1601        /* This also clears the status bits. */
1602        status = usc_InDmaReg( info, RDMR );
1603
1604        if ( debug_level >= DEBUG_LEVEL_ISR )   
1605                printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1606                        __FILE__,__LINE__,info->device_name,status);
1607                        
1608        info->pending_bh |= BH_RECEIVE;
1609        
1610        if ( status & BIT3 ) {
1611                info->rx_overflow = true;
1612                info->icount.buf_overrun++;
1613        }
1614
1615}       /* end of mgsl_isr_receive_dma() */
1616
1617/* mgsl_isr_transmit_dma()
1618 *
1619 *      This function services a transmit DMA channel interrupt.
1620 *
1621 *      For this driver there is one source of transmit DMA interrupts
1622 *      as identified in the Transmit DMA Mode Register (TDMR):
1623 *
1624 *      BIT2  EOB       End of Buffer. This interrupt occurs when a
1625 *                      transmit DMA buffer has been emptied.
1626 *
1627 *      The driver maintains enough transmit DMA buffers to hold at least
1628 *      one max frame size transmit frame. When operating in a buffered
1629 *      transmit mode, there may be enough transmit DMA buffers to hold at
1630 *      least two or more max frame size frames. On an EOB condition,
1631 *      determine if there are any queued transmit buffers and copy into
1632 *      transmit DMA buffers if we have room.
1633 *
1634 * Arguments:           info            pointer to device instance data
1635 * Return Value:        None
1636 */
1637static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1638{
1639        u16 status;
1640
1641        /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1642        usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1643
1644        /* Read the transmit DMA status to identify interrupt type. */
1645        /* This also clears the status bits. */
1646
1647        status = usc_InDmaReg( info, TDMR );
1648
1649        if ( debug_level >= DEBUG_LEVEL_ISR )
1650                printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1651                        __FILE__,__LINE__,info->device_name,status);
1652
1653        if ( status & BIT2 ) {
1654                --info->tx_dma_buffers_used;
1655
1656                /* if there are transmit frames queued,
1657                 *  try to load the next one
1658                 */
1659                if ( load_next_tx_holding_buffer(info) ) {
1660                        /* if call returns non-zero value, we have
1661                         * at least one free tx holding buffer
1662                         */
1663                        info->pending_bh |= BH_TRANSMIT;
1664                }
1665        }
1666
1667}       /* end of mgsl_isr_transmit_dma() */
1668
1669/* mgsl_interrupt()
1670 * 
1671 *      Interrupt service routine entry point.
1672 *      
1673 * Arguments:
1674 * 
1675 *      irq             interrupt number that caused interrupt
1676 *      dev_id          device ID supplied during interrupt registration
1677 *      
1678 * Return Value: None
1679 */
1680static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1681{
1682        struct mgsl_struct *info = dev_id;
1683        u16 UscVector;
1684        u16 DmaVector;
1685
1686        if ( debug_level >= DEBUG_LEVEL_ISR )   
1687                printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1688                        __FILE__, __LINE__, info->irq_level);
1689
1690        spin_lock(&info->irq_spinlock);
1691
1692        for(;;) {
1693                /* Read the interrupt vectors from hardware. */
1694                UscVector = usc_InReg(info, IVR) >> 9;
1695                DmaVector = usc_InDmaReg(info, DIVR);
1696                
1697                if ( debug_level >= DEBUG_LEVEL_ISR )   
1698                        printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1699                                __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1700                        
1701                if ( !UscVector && !DmaVector )
1702                        break;
1703                        
1704                /* Dispatch interrupt vector */
1705                if ( UscVector )
1706                        (*UscIsrTable[UscVector])(info);
1707                else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1708                        mgsl_isr_transmit_dma(info);
1709                else
1710                        mgsl_isr_receive_dma(info);
1711
1712                if ( info->isr_overflow ) {
1713                        printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1714                                __FILE__, __LINE__, info->device_name, info->irq_level);
1715                        usc_DisableMasterIrqBit(info);
1716                        usc_DisableDmaInterrupts(info,DICR_MASTER);
1717                        break;
1718                }
1719        }
1720        
1721        /* Request bottom half processing if there's something 
1722         * for it to do and the bh is not already running
1723         */
1724
1725        if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1726                if ( debug_level >= DEBUG_LEVEL_ISR )   
1727                        printk("%s(%d):%s queueing bh task.\n",
1728                                __FILE__,__LINE__,info->device_name);
1729                schedule_work(&info->task);
1730                info->bh_requested = true;
1731        }
1732
1733        spin_unlock(&info->irq_spinlock);
1734        
1735        if ( debug_level >= DEBUG_LEVEL_ISR )   
1736                printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1737                        __FILE__, __LINE__, info->irq_level);
1738
1739        return IRQ_HANDLED;
1740}       /* end of mgsl_interrupt() */
1741
1742/* startup()
1743 * 
1744 *      Initialize and start device.
1745 *      
1746 * Arguments:           info    pointer to device instance data
1747 * Return Value:        0 if success, otherwise error code
1748 */
1749static int startup(struct mgsl_struct * info)
1750{
1751        int retval = 0;
1752        
1753        if ( debug_level >= DEBUG_LEVEL_INFO )
1754                printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1755                
1756        if (info->port.flags & ASYNC_INITIALIZED)
1757                return 0;
1758        
1759        if (!info->xmit_buf) {
1760                /* allocate a page of memory for a transmit buffer */
1761                info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1762                if (!info->xmit_buf) {
1763                        printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1764                                __FILE__,__LINE__,info->device_name);
1765                        return -ENOMEM;
1766                }
1767        }
1768
1769        info->pending_bh = 0;
1770        
1771        memset(&info->icount, 0, sizeof(info->icount));
1772
1773        setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1774        
1775        /* Allocate and claim adapter resources */
1776        retval = mgsl_claim_resources(info);
1777        
1778        /* perform existence check and diagnostics */
1779        if ( !retval )
1780                retval = mgsl_adapter_test(info);
1781                
1782        if ( retval ) {
1783                if (capable(CAP_SYS_ADMIN) && info->port.tty)
1784                        set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1785                mgsl_release_resources(info);
1786                return retval;
1787        }
1788
1789        /* program hardware for current parameters */
1790        mgsl_change_params(info);
1791        
1792        if (info->port.tty)
1793                clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1794
1795        info->port.flags |= ASYNC_INITIALIZED;
1796        
1797        return 0;
1798        
1799}       /* end of startup() */
1800
1801/* shutdown()
1802 *
1803 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1804 *
1805 * Arguments:           info    pointer to device instance data
1806 * Return Value:        None
1807 */
1808static void shutdown(struct mgsl_struct * info)
1809{
1810        unsigned long flags;
1811        
1812        if (!(info->port.flags & ASYNC_INITIALIZED))
1813                return;
1814
1815        if (debug_level >= DEBUG_LEVEL_INFO)
1816                printk("%s(%d):mgsl_shutdown(%s)\n",
1817                         __FILE__,__LINE__, info->device_name );
1818
1819        /* clear status wait queue because status changes */
1820        /* can't happen after shutting down the hardware */
1821        wake_up_interruptible(&info->status_event_wait_q);
1822        wake_up_interruptible(&info->event_wait_q);
1823
1824        del_timer_sync(&info->tx_timer);
1825
1826        if (info->xmit_buf) {
1827                free_page((unsigned long) info->xmit_buf);
1828                info->xmit_buf = NULL;
1829        }
1830
1831        spin_lock_irqsave(&info->irq_spinlock,flags);
1832        usc_DisableMasterIrqBit(info);
1833        usc_stop_receiver(info);
1834        usc_stop_transmitter(info);
1835        usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1836                TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1837        usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1838
1839        /* Disable DMAEN (Port 7, Bit 14) */
1840        /* This disconnects the DMA request signal from the ISA bus */
1841        /* on the ISA adapter. This has no effect for the PCI adapter */
1842        usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1843
1844        /* Disable INTEN (Port 6, Bit12) */
1845        /* This disconnects the IRQ request signal to the ISA bus */
1846        /* on the ISA adapter. This has no effect for the PCI adapter */
1847        usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1848
1849        if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
1850                info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1851                usc_set_serial_signals(info);
1852        }
1853
1854        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1855
1856        mgsl_release_resources(info);   
1857        
1858        if (info->port.tty)
1859                set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1860
1861        info->port.flags &= ~ASYNC_INITIALIZED;
1862        
1863}       /* end of shutdown() */
1864
1865static void mgsl_program_hw(struct mgsl_struct *info)
1866{
1867        unsigned long flags;
1868
1869        spin_lock_irqsave(&info->irq_spinlock,flags);
1870        
1871        usc_stop_receiver(info);
1872        usc_stop_transmitter(info);
1873        info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1874        
1875        if (info->params.mode == MGSL_MODE_HDLC ||
1876            info->params.mode == MGSL_MODE_RAW ||
1877            info->netcount)
1878                usc_set_sync_mode(info);
1879        else
1880                usc_set_async_mode(info);
1881                
1882        usc_set_serial_signals(info);
1883        
1884        info->dcd_chkcount = 0;
1885        info->cts_chkcount = 0;
1886        info->ri_chkcount = 0;
1887        info->dsr_chkcount = 0;
1888
1889        usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);          
1890        usc_EnableInterrupts(info, IO_PIN);
1891        usc_get_serial_signals(info);
1892                
1893        if (info->netcount || info->port.tty->termios.c_cflag & CREAD)
1894                usc_start_receiver(info);
1895                
1896        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1897}
1898
1899/* Reconfigure adapter based on new parameters
1900 */
1901static void mgsl_change_params(struct mgsl_struct *info)
1902{
1903        unsigned cflag;
1904        int bits_per_char;
1905
1906        if (!info->port.tty)
1907                return;
1908                
1909        if (debug_level >= DEBUG_LEVEL_INFO)
1910                printk("%s(%d):mgsl_change_params(%s)\n",
1911                         __FILE__,__LINE__, info->device_name );
1912                         
1913        cflag = info->port.tty->termios.c_cflag;
1914
1915        /* if B0 rate (hangup) specified then negate RTS and DTR */
1916        /* otherwise assert RTS and DTR */
1917        if (cflag & CBAUD)
1918                info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1919        else
1920                info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1921        
1922        /* byte size and parity */
1923        
1924        switch (cflag & CSIZE) {
1925              case CS5: info->params.data_bits = 5; break;
1926              case CS6: info->params.data_bits = 6; break;
1927              case CS7: info->params.data_bits = 7; break;
1928              case CS8: info->params.data_bits = 8; break;
1929              /* Never happens, but GCC is too dumb to figure it out */
1930              default:  info->params.data_bits = 7; break;
1931              }
1932              
1933        if (cflag & CSTOPB)
1934                info->params.stop_bits = 2;
1935        else
1936                info->params.stop_bits = 1;
1937
1938        info->params.parity = ASYNC_PARITY_NONE;
1939        if (cflag & PARENB) {
1940                if (cflag & PARODD)
1941                        info->params.parity = ASYNC_PARITY_ODD;
1942                else
1943                        info->params.parity = ASYNC_PARITY_EVEN;
1944#ifdef CMSPAR
1945                if (cflag & CMSPAR)
1946                        info->params.parity = ASYNC_PARITY_SPACE;
1947#endif
1948        }
1949
1950        /* calculate number of jiffies to transmit a full
1951         * FIFO (32 bytes) at specified data rate
1952         */
1953        bits_per_char = info->params.data_bits + 
1954                        info->params.stop_bits + 1;
1955
1956        /* if port data rate is set to 460800 or less then
1957         * allow tty settings to override, otherwise keep the
1958         * current data rate.
1959         */
1960        if (info->params.data_rate <= 460800)
1961                info->params.data_rate = tty_get_baud_rate(info->port.tty);
1962        
1963        if ( info->params.data_rate ) {
1964                info->timeout = (32*HZ*bits_per_char) / 
1965                                info->params.data_rate;
1966        }
1967        info->timeout += HZ/50;         /* Add .02 seconds of slop */
1968
1969        if (cflag & CRTSCTS)
1970                info->port.flags |= ASYNC_CTS_FLOW;
1971        else
1972                info->port.flags &= ~ASYNC_CTS_FLOW;
1973                
1974        if (cflag & CLOCAL)
1975                info->port.flags &= ~ASYNC_CHECK_CD;
1976        else
1977                info->port.flags |= ASYNC_CHECK_CD;
1978
1979        /* process tty input control flags */
1980        
1981        info->read_status_mask = RXSTATUS_OVERRUN;
1982        if (I_INPCK(info->port.tty))
1983                info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1984        if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1985                info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1986        
1987        if (I_IGNPAR(info->port.tty))
1988                info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1989        if (I_IGNBRK(info->port.tty)) {
1990                info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
1991                /* If ignoring parity and break indicators, ignore 
1992                 * overruns too.  (For real raw support).
1993                 */
1994                if (I_IGNPAR(info->port.tty))
1995                        info->ignore_status_mask |= RXSTATUS_OVERRUN;
1996        }
1997
1998        mgsl_program_hw(info);
1999
2000}       /* end of mgsl_change_params() */
2001
2002/* mgsl_put_char()
2003 * 
2004 *      Add a character to the transmit buffer.
2005 *      
2006 * Arguments:           tty     pointer to tty information structure
2007 *                      ch      character to add to transmit buffer
2008 *              
2009 * Return Value:        None
2010 */
2011static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2012{
2013        struct mgsl_struct *info = tty->driver_data;
2014        unsigned long flags;
2015        int ret = 0;
2016
2017        if (debug_level >= DEBUG_LEVEL_INFO) {
2018                printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
2019                        __FILE__, __LINE__, ch, info->device_name);
2020        }               
2021        
2022        if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2023                return 0;
2024
2025        if (!info->xmit_buf)
2026                return 0;
2027
2028        spin_lock_irqsave(&info->irq_spinlock, flags);
2029        
2030        if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
2031                if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2032                        info->xmit_buf[info->xmit_head++] = ch;
2033                        info->xmit_head &= SERIAL_XMIT_SIZE-1;
2034                        info->xmit_cnt++;
2035                        ret = 1;
2036                }
2037        }
2038        spin_unlock_irqrestore(&info->irq_spinlock, flags);
2039        return ret;
2040        
2041}       /* end of mgsl_put_char() */
2042
2043/* mgsl_flush_chars()
2044 * 
2045 *      Enable transmitter so remaining characters in the
2046 *      transmit buffer are sent.
2047 *      
2048 * Arguments:           tty     pointer to tty information structure
2049 * Return Value:        None
2050 */
2051static void mgsl_flush_chars(struct tty_struct *tty)
2052{
2053        struct mgsl_struct *info = tty->driver_data;
2054        unsigned long flags;
2055                                
2056        if ( debug_level >= DEBUG_LEVEL_INFO )
2057                printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2058                        __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2059        
2060        if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2061                return;
2062
2063        if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2064            !info->xmit_buf)
2065                return;
2066
2067        if ( debug_level >= DEBUG_LEVEL_INFO )
2068                printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2069                        __FILE__,__LINE__,info->device_name );
2070
2071        spin_lock_irqsave(&info->irq_spinlock,flags);
2072        
2073        if (!info->tx_active) {
2074                if ( (info->params.mode == MGSL_MODE_HDLC ||
2075                        info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2076                        /* operating in synchronous (frame oriented) mode */
2077                        /* copy data from circular xmit_buf to */
2078                        /* transmit DMA buffer. */
2079                        mgsl_load_tx_dma_buffer(info,
2080                                 info->xmit_buf,info->xmit_cnt);
2081                }
2082                usc_start_transmitter(info);
2083        }
2084        
2085        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2086        
2087}       /* end of mgsl_flush_chars() */
2088
2089/* mgsl_write()
2090 * 
2091 *      Send a block of data
2092 *      
2093 * Arguments:
2094 * 
2095 *      tty             pointer to tty information structure
2096 *      buf             pointer to buffer containing send data
2097 *      count           size of send data in bytes
2098 *      
2099 * Return Value:        number of characters written
2100 */
2101static int mgsl_write(struct tty_struct * tty,
2102                    const unsigned char *buf, int count)
2103{
2104        int     c, ret = 0;
2105        struct mgsl_struct *info = tty->driver_data;
2106        unsigned long flags;
2107        
2108        if ( debug_level >= DEBUG_LEVEL_INFO )
2109                printk( "%s(%d):mgsl_write(%s) count=%d\n",
2110                        __FILE__,__LINE__,info->device_name,count);
2111        
2112        if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2113                goto cleanup;
2114
2115        if (!info->xmit_buf)
2116                goto cleanup;
2117
2118        if ( info->params.mode == MGSL_MODE_HDLC ||
2119                        info->params.mode == MGSL_MODE_RAW ) {
2120                /* operating in synchronous (frame oriented) mode */
2121                if (info->tx_active) {
2122
2123                        if ( info->params.mode == MGSL_MODE_HDLC ) {
2124                                ret = 0;
2125                                goto cleanup;
2126                        }
2127                        /* transmitter is actively sending data -
2128                         * if we have multiple transmit dma and
2129                         * holding buffers, attempt to queue this
2130                         * frame for transmission at a later time.
2131                         */
2132                        if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2133                                /* no tx holding buffers available */
2134                                ret = 0;
2135                                goto cleanup;
2136                        }
2137
2138                        /* queue transmit frame request */
2139                        ret = count;
2140                        save_tx_buffer_request(info,buf,count);
2141
2142                        /* if we have sufficient tx dma buffers,
2143                         * load the next buffered tx request
2144                         */
2145                        spin_lock_irqsave(&info->irq_spinlock,flags);
2146                        load_next_tx_holding_buffer(info);
2147                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2148                        goto cleanup;
2149                }
2150        
2151                /* if operating in HDLC LoopMode and the adapter  */
2152                /* has yet to be inserted into the loop, we can't */
2153                /* transmit                                       */
2154
2155                if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2156                        !usc_loopmode_active(info) )
2157                {
2158                        ret = 0;
2159                        goto cleanup;
2160                }
2161
2162                if ( info->xmit_cnt ) {
2163                        /* Send accumulated from send_char() calls */
2164                        /* as frame and wait before accepting more data. */
2165                        ret = 0;
2166                        
2167                        /* copy data from circular xmit_buf to */
2168                        /* transmit DMA buffer. */
2169                        mgsl_load_tx_dma_buffer(info,
2170                                info->xmit_buf,info->xmit_cnt);
2171                        if ( debug_level >= DEBUG_LEVEL_INFO )
2172                                printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2173                                        __FILE__,__LINE__,info->device_name);
2174                } else {
2175                        if ( debug_level >= DEBUG_LEVEL_INFO )
2176                                printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2177                                        __FILE__,__LINE__,info->device_name);
2178                        ret = count;
2179                        info->xmit_cnt = count;
2180                        mgsl_load_tx_dma_buffer(info,buf,count);
2181                }
2182        } else {
2183                while (1) {
2184                        spin_lock_irqsave(&info->irq_spinlock,flags);
2185                        c = min_t(int, count,
2186                                min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2187                                    SERIAL_XMIT_SIZE - info->xmit_head));
2188                        if (c <= 0) {
2189                                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2190                                break;
2191                        }
2192                        memcpy(info->xmit_buf + info->xmit_head, buf, c);
2193                        info->xmit_head = ((info->xmit_head + c) &
2194                                           (SERIAL_XMIT_SIZE-1));
2195                        info->xmit_cnt += c;
2196                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2197                        buf += c;
2198                        count -= c;
2199                        ret += c;
2200                }
2201        }       
2202        
2203        if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2204                spin_lock_irqsave(&info->irq_spinlock,flags);
2205                if (!info->tx_active)
2206                        usc_start_transmitter(info);
2207                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2208        }
2209cleanup:        
2210        if ( debug_level >= DEBUG_LEVEL_INFO )
2211                printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2212                        __FILE__,__LINE__,info->device_name,ret);
2213                        
2214        return ret;
2215        
2216}       /* end of mgsl_write() */
2217
2218/* mgsl_write_room()
2219 *
2220 *      Return the count of free bytes in transmit buffer
2221 *      
2222 * Arguments:           tty     pointer to tty info structure
2223 * Return Value:        None
2224 */
2225static int mgsl_write_room(struct tty_struct *tty)
2226{
2227        struct mgsl_struct *info = tty->driver_data;
2228        int     ret;
2229                                
2230        if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2231                return 0;
2232        ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2233        if (ret < 0)
2234                ret = 0;
2235                
2236        if (debug_level >= DEBUG_LEVEL_INFO)
2237                printk("%s(%d):mgsl_write_room(%s)=%d\n",
2238                         __FILE__,__LINE__, info->device_name,ret );
2239                         
2240        if ( info->params.mode == MGSL_MODE_HDLC ||
2241                info->params.mode == MGSL_MODE_RAW ) {
2242                /* operating in synchronous (frame oriented) mode */
2243                if ( info->tx_active )
2244                        return 0;
2245                else
2246                        return HDLC_MAX_FRAME_SIZE;
2247        }
2248        
2249        return ret;
2250        
2251}       /* end of mgsl_write_room() */
2252
2253/* mgsl_chars_in_buffer()
2254 *
2255 *      Return the count of bytes in transmit buffer
2256 *      
2257 * Arguments:           tty     pointer to tty info structure
2258 * Return Value:        None
2259 */
2260static int mgsl_chars_in_buffer(struct tty_struct *tty)
2261{
2262        struct mgsl_struct *info = tty->driver_data;
2263                         
2264        if (debug_level >= DEBUG_LEVEL_INFO)
2265                printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2266                         __FILE__,__LINE__, info->device_name );
2267                         
2268        if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2269                return 0;
2270                
2271        if (debug_level >= DEBUG_LEVEL_INFO)
2272                printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2273                         __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2274                         
2275        if ( info->params.mode == MGSL_MODE_HDLC ||
2276                info->params.mode == MGSL_MODE_RAW ) {
2277                /* operating in synchronous (frame oriented) mode */
2278                if ( info->tx_active )
2279                        return info->max_frame_size;
2280                else
2281                        return 0;
2282        }
2283                         
2284        return info->xmit_cnt;
2285}       /* end of mgsl_chars_in_buffer() */
2286
2287/* mgsl_flush_buffer()
2288 *
2289 *      Discard all data in the send buffer
2290 *      
2291 * Arguments:           tty     pointer to tty info structure
2292 * Return Value:        None
2293 */
2294static void mgsl_flush_buffer(struct tty_struct *tty)
2295{
2296        struct mgsl_struct *info = tty->driver_data;
2297        unsigned long flags;
2298        
2299        if (debug_level >= DEBUG_LEVEL_INFO)
2300                printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2301                         __FILE__,__LINE__, info->device_name );
2302        
2303        if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2304                return;
2305                
2306        spin_lock_irqsave(&info->irq_spinlock,flags); 
2307        info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2308        del_timer(&info->tx_timer);     
2309        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2310        
2311        tty_wakeup(tty);
2312}
2313
2314/* mgsl_send_xchar()
2315 *
2316 *      Send a high-priority XON/XOFF character
2317 *      
2318 * Arguments:           tty     pointer to tty info structure
2319 *                      ch      character to send
2320 * Return Value:        None
2321 */
2322static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2323{
2324        struct mgsl_struct *info = tty->driver_data;
2325        unsigned long flags;
2326
2327        if (debug_level >= DEBUG_LEVEL_INFO)
2328                printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2329                         __FILE__,__LINE__, info->device_name, ch );
2330                         
2331        if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2332                return;
2333
2334        info->x_char = ch;
2335        if (ch) {
2336                /* Make sure transmit interrupts are on */
2337                spin_lock_irqsave(&info->irq_spinlock,flags);
2338                if (!info->tx_enabled)
2339                        usc_start_transmitter(info);
2340                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2341        }
2342}       /* end of mgsl_send_xchar() */
2343
2344/* mgsl_throttle()
2345 * 
2346 *      Signal remote device to throttle send data (our receive data)
2347 *      
2348 * Arguments:           tty     pointer to tty info structure
2349 * Return Value:        None
2350 */
2351static void mgsl_throttle(struct tty_struct * tty)
2352{
2353        struct mgsl_struct *info = tty->driver_data;
2354        unsigned long flags;
2355        
2356        if (debug_level >= DEBUG_LEVEL_INFO)
2357                printk("%s(%d):mgsl_throttle(%s) entry\n",
2358                         __FILE__,__LINE__, info->device_name );
2359
2360        if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2361                return;
2362        
2363        if (I_IXOFF(tty))
2364                mgsl_send_xchar(tty, STOP_CHAR(tty));
2365
2366        if (tty->termios.c_cflag & CRTSCTS) {
2367                spin_lock_irqsave(&info->irq_spinlock,flags);
2368                info->serial_signals &= ~SerialSignal_RTS;
2369                usc_set_serial_signals(info);
2370                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2371        }
2372}       /* end of mgsl_throttle() */
2373
2374/* mgsl_unthrottle()
2375 * 
2376 *      Signal remote device to stop throttling send data (our receive data)
2377 *      
2378 * Arguments:           tty     pointer to tty info structure
2379 * Return Value:        None
2380 */
2381static void mgsl_unthrottle(struct tty_struct * tty)
2382{
2383        struct mgsl_struct *info = tty->driver_data;
2384        unsigned long flags;
2385        
2386        if (debug_level >= DEBUG_LEVEL_INFO)
2387                printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2388                         __FILE__,__LINE__, info->device_name );
2389
2390        if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2391                return;
2392        
2393        if (I_IXOFF(tty)) {
2394                if (info->x_char)
2395                        info->x_char = 0;
2396                else
2397                        mgsl_send_xchar(tty, START_CHAR(tty));
2398        }
2399
2400        if (tty->termios.c_cflag & CRTSCTS) {
2401                spin_lock_irqsave(&info->irq_spinlock,flags);
2402                info->serial_signals |= SerialSignal_RTS;
2403                usc_set_serial_signals(info);
2404                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2405        }
2406        
2407}       /* end of mgsl_unthrottle() */
2408
2409/* mgsl_get_stats()
2410 * 
2411 *      get the current serial parameters information
2412 *
2413 * Arguments:   info            pointer to device instance data
2414 *              user_icount     pointer to buffer to hold returned stats
2415 *      
2416 * Return Value:        0 if success, otherwise error code
2417 */
2418static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2419{
2420        int err;
2421        
2422        if (debug_level >= DEBUG_LEVEL_INFO)
2423                printk("%s(%d):mgsl_get_params(%s)\n",
2424                         __FILE__,__LINE__, info->device_name);
2425                        
2426        if (!user_icount) {
2427                memset(&info->icount, 0, sizeof(info->icount));
2428        } else {
2429                mutex_lock(&info->port.mutex);
2430                COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2431                mutex_unlock(&info->port.mutex);
2432                if (err)
2433                        return -EFAULT;
2434        }
2435        
2436        return 0;
2437        
2438}       /* end of mgsl_get_stats() */
2439
2440/* mgsl_get_params()
2441 * 
2442 *      get the current serial parameters information
2443 *
2444 * Arguments:   info            pointer to device instance data
2445 *              user_params     pointer to buffer to hold returned params
2446 *      
2447 * Return Value:        0 if success, otherwise error code
2448 */
2449static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2450{
2451        int err;
2452        if (debug_level >= DEBUG_LEVEL_INFO)
2453                printk("%s(%d):mgsl_get_params(%s)\n",
2454                         __FILE__,__LINE__, info->device_name);
2455                        
2456        mutex_lock(&info->port.mutex);
2457        COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2458        mutex_unlock(&info->port.mutex);
2459        if (err) {
2460                if ( debug_level >= DEBUG_LEVEL_INFO )
2461                        printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2462                                __FILE__,__LINE__,info->device_name);
2463                return -EFAULT;
2464        }
2465        
2466        return 0;
2467        
2468}       /* end of mgsl_get_params() */
2469
2470/* mgsl_set_params()
2471 * 
2472 *      set the serial parameters
2473 *      
2474 * Arguments:
2475 * 
2476 *      info            pointer to device instance data
2477 *      new_params      user buffer containing new serial params
2478 *
2479 * Return Value:        0 if success, otherwise error code
2480 */
2481static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2482{
2483        unsigned long flags;
2484        MGSL_PARAMS tmp_params;
2485        int err;
2486 
2487        if (debug_level >= DEBUG_LEVEL_INFO)
2488                printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2489                        info->device_name );
2490        COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2491        if (err) {
2492                if ( debug_level >= DEBUG_LEVEL_INFO )
2493                        printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2494                                __FILE__,__LINE__,info->device_name);
2495                return -EFAULT;
2496        }
2497        
2498        mutex_lock(&info->port.mutex);
2499        spin_lock_irqsave(&info->irq_spinlock,flags);
2500        memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2501        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2502        
2503        mgsl_change_params(info);
2504        mutex_unlock(&info->port.mutex);
2505        
2506        return 0;
2507        
2508}       /* end of mgsl_set_params() */
2509
2510/* mgsl_get_txidle()
2511 * 
2512 *      get the current transmit idle mode
2513 *
2514 * Arguments:   info            pointer to device instance data
2515 *              idle_mode       pointer to buffer to hold returned idle mode
2516 *      
2517 * Return Value:        0 if success, otherwise error code
2518 */
2519static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2520{
2521        int err;
2522        
2523        if (debug_level >= DEBUG_LEVEL_INFO)
2524                printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2525                         __FILE__,__LINE__, info->device_name, info->idle_mode);
2526                        
2527        COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2528        if (err) {
2529                if ( debug_level >= DEBUG_LEVEL_INFO )
2530                        printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2531                                __FILE__,__LINE__,info->device_name);
2532                return -EFAULT;
2533        }
2534        
2535        return 0;
2536        
2537}       /* end of mgsl_get_txidle() */
2538
2539/* mgsl_set_txidle()    service ioctl to set transmit idle mode
2540 *      
2541 * Arguments:           info            pointer to device instance data
2542 *                      idle_mode       new idle mode
2543 *
2544 * Return Value:        0 if success, otherwise error code
2545 */
2546static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2547{
2548        unsigned long flags;
2549 
2550        if (debug_level >= DEBUG_LEVEL_INFO)
2551                printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2552                        info->device_name, idle_mode );
2553                        
2554        spin_lock_irqsave(&info->irq_spinlock,flags);
2555        info->idle_mode = idle_mode;
2556        usc_set_txidle( info );
2557        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2558        return 0;
2559        
2560}       /* end of mgsl_set_txidle() */
2561
2562/* mgsl_txenable()
2563 * 
2564 *      enable or disable the transmitter
2565 *      
2566 * Arguments:
2567 * 
2568 *      info            pointer to device instance data
2569 *      enable          1 = enable, 0 = disable
2570 *
2571 * Return Value:        0 if success, otherwise error code
2572 */
2573static int mgsl_txenable(struct mgsl_struct * info, int enable)
2574{
2575        unsigned long flags;
2576 
2577        if (debug_level >= DEBUG_LEVEL_INFO)
2578                printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2579                        info->device_name, enable);
2580                        
2581        spin_lock_irqsave(&info->irq_spinlock,flags);
2582        if ( enable ) {
2583                if ( !info->tx_enabled ) {
2584
2585                        usc_start_transmitter(info);
2586                        /*--------------------------------------------------
2587                         * if HDLC/SDLC Loop mode, attempt to insert the
2588                         * station in the 'loop' by setting CMR:13. Upon
2589                         * receipt of the next GoAhead (RxAbort) sequence,
2590                         * the OnLoop indicator (CCSR:7) should go active
2591                         * to indicate that we are on the loop
2592                         *--------------------------------------------------*/
2593                        if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2594                                usc_loopmode_insert_request( info );
2595                }
2596        } else {
2597                if ( info->tx_enabled )
2598                        usc_stop_transmitter(info);
2599        }
2600        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2601        return 0;
2602        
2603}       /* end of mgsl_txenable() */
2604
2605/* mgsl_txabort()       abort send HDLC frame
2606 *      
2607 * Arguments:           info            pointer to device instance data
2608 * Return Value:        0 if success, otherwise error code
2609 */
2610static int mgsl_txabort(struct mgsl_struct * info)
2611{
2612        unsigned long flags;
2613 
2614        if (debug_level >= DEBUG_LEVEL_INFO)
2615                printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2616                        info->device_name);
2617                        
2618        spin_lock_irqsave(&info->irq_spinlock,flags);
2619        if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2620        {
2621                if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2622                        usc_loopmode_cancel_transmit( info );
2623                else
2624                        usc_TCmd(info,TCmd_SendAbort);
2625        }
2626        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2627        return 0;
2628        
2629}       /* end of mgsl_txabort() */
2630
2631/* mgsl_rxenable()      enable or disable the receiver
2632 *      
2633 * Arguments:           info            pointer to device instance data
2634 *                      enable          1 = enable, 0 = disable
2635 * Return Value:        0 if success, otherwise error code
2636 */
2637static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2638{
2639        unsigned long flags;
2640 
2641        if (debug_level >= DEBUG_LEVEL_INFO)
2642                printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2643                        info->device_name, enable);
2644                        
2645        spin_lock_irqsave(&info->irq_spinlock,flags);
2646        if ( enable ) {
2647                if ( !info->rx_enabled )
2648                        usc_start_receiver(info);
2649        } else {
2650                if ( info->rx_enabled )
2651                        usc_stop_receiver(info);
2652        }
2653        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2654        return 0;
2655        
2656}       /* end of mgsl_rxenable() */
2657
2658/* mgsl_wait_event()    wait for specified event to occur
2659 *      
2660 * Arguments:           info    pointer to device instance data
2661 *                      mask    pointer to bitmask of events to wait for
2662 * Return Value:        0       if successful and bit mask updated with
2663 *                              of events triggerred,
2664 *                      otherwise error code
2665 */
2666static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2667{
2668        unsigned long flags;
2669        int s;
2670        int rc=0;
2671        struct mgsl_icount cprev, cnow;
2672        int events;
2673        int mask;
2674        struct  _input_signal_events oldsigs, newsigs;
2675        DECLARE_WAITQUEUE(wait, current);
2676
2677        COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2678        if (rc) {
2679                return  -EFAULT;
2680        }
2681                 
2682        if (debug_level >= DEBUG_LEVEL_INFO)
2683                printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2684                        info->device_name, mask);
2685
2686        spin_lock_irqsave(&info->irq_spinlock,flags);
2687
2688        /* return immediately if state matches requested events */
2689        usc_get_serial_signals(info);
2690        s = info->serial_signals;
2691        events = mask &
2692                ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2693                  ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2694                  ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2695                  ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2696        if (events) {
2697                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2698                goto exit;
2699        }
2700
2701        /* save current irq counts */
2702        cprev = info->icount;
2703        oldsigs = info->input_signal_events;
2704        
2705        /* enable hunt and idle irqs if needed */
2706        if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2707                u16 oldreg = usc_InReg(info,RICR);
2708                u16 newreg = oldreg +
2709                         (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2710                         (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2711                if (oldreg != newreg)
2712                        usc_OutReg(info, RICR, newreg);
2713        }
2714        
2715        set_current_state(TASK_INTERRUPTIBLE);
2716        add_wait_queue(&info->event_wait_q, &wait);
2717        
2718        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2719        
2720
2721        for(;;) {
2722                schedule();
2723                if (signal_pending(current)) {
2724                        rc = -ERESTARTSYS;
2725                        break;
2726                }
2727                        
2728                /* get current irq counts */
2729                spin_lock_irqsave(&info->irq_spinlock,flags);
2730                cnow = info->icount;
2731                newsigs = info->input_signal_events;
2732                set_current_state(TASK_INTERRUPTIBLE);
2733                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2734
2735                /* if no change, wait aborted for some reason */
2736                if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2737                    newsigs.dsr_down == oldsigs.dsr_down &&
2738                    newsigs.dcd_up   == oldsigs.dcd_up   &&
2739                    newsigs.dcd_down == oldsigs.dcd_down &&
2740                    newsigs.cts_up   == oldsigs.cts_up   &&
2741                    newsigs.cts_down == oldsigs.cts_down &&
2742                    newsigs.ri_up    == oldsigs.ri_up    &&
2743                    newsigs.ri_down  == oldsigs.ri_down  &&
2744                    cnow.exithunt    == cprev.exithunt   &&
2745                    cnow.rxidle      == cprev.rxidle) {
2746                        rc = -EIO;
2747                        break;
2748                }
2749
2750                events = mask &
2751                        ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2752                        (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2753                        (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2754                        (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2755                        (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2756                        (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2757                        (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2758                        (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2759                        (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2760                          (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2761                if (events)
2762                        break;
2763                
2764                cprev = cnow;
2765                oldsigs = newsigs;
2766        }
2767        
2768        remove_wait_queue(&info->event_wait_q, &wait);
2769        set_current_state(TASK_RUNNING);
2770
2771        if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2772                spin_lock_irqsave(&info->irq_spinlock,flags);
2773                if (!waitqueue_active(&info->event_wait_q)) {
2774                        /* disable enable exit hunt mode/idle rcvd IRQs */
2775                        usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2776                                ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2777                }
2778                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2779        }
2780exit:
2781        if ( rc == 0 )
2782                PUT_USER(rc, events, mask_ptr);
2783                
2784        return rc;
2785        
2786}       /* end of mgsl_wait_event() */
2787
2788static int modem_input_wait(struct mgsl_struct *info,int arg)
2789{
2790        unsigned long flags;
2791        int rc;
2792        struct mgsl_icount cprev, cnow;
2793        DECLARE_WAITQUEUE(wait, current);
2794
2795        /* save current irq counts */
2796        spin_lock_irqsave(&info->irq_spinlock,flags);
2797        cprev = info->icount;
2798        add_wait_queue(&info->status_event_wait_q, &wait);
2799        set_current_state(TASK_INTERRUPTIBLE);
2800        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2801
2802        for(;;) {
2803                schedule();
2804                if (signal_pending(current)) {
2805                        rc = -ERESTARTSYS;
2806                        break;
2807                }
2808
2809                /* get new irq counts */
2810                spin_lock_irqsave(&info->irq_spinlock,flags);
2811                cnow = info->icount;
2812                set_current_state(TASK_INTERRUPTIBLE);
2813                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2814
2815                /* if no change, wait aborted for some reason */
2816                if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2817                    cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2818                        rc = -EIO;
2819                        break;
2820                }
2821
2822                /* check for change in caller specified modem input */
2823                if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2824                    (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2825                    (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
2826                    (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2827                        rc = 0;
2828                        break;
2829                }
2830
2831                cprev = cnow;
2832        }
2833        remove_wait_queue(&info->status_event_wait_q, &wait);
2834        set_current_state(TASK_RUNNING);
2835        return rc;
2836}
2837
2838/* return the state of the serial control and status signals
2839 */
2840static int tiocmget(struct tty_struct *tty)
2841{
2842        struct mgsl_struct *info = tty->driver_data;
2843        unsigned int result;
2844        unsigned long flags;
2845
2846        spin_lock_irqsave(&info->irq_spinlock,flags);
2847        usc_get_serial_signals(info);
2848        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2849
2850        result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2851                ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2852                ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2853                ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
2854                ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2855                ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2856
2857        if (debug_level >= DEBUG_LEVEL_INFO)
2858                printk("%s(%d):%s tiocmget() value=%08X\n",
2859                         __FILE__,__LINE__, info->device_name, result );
2860        return result;
2861}
2862
2863/* set modem control signals (DTR/RTS)
2864 */
2865static int tiocmset(struct tty_struct *tty,
2866                                    unsigned int set, unsigned int clear)
2867{
2868        struct mgsl_struct *info = tty->driver_data;
2869        unsigned long flags;
2870
2871        if (debug_level >= DEBUG_LEVEL_INFO)
2872                printk("%s(%d):%s tiocmset(%x,%x)\n",
2873                        __FILE__,__LINE__,info->device_name, set, clear);
2874
2875        if (set & TIOCM_RTS)
2876                info->serial_signals |= SerialSignal_RTS;
2877        if (set & TIOCM_DTR)
2878                info->serial_signals |= SerialSignal_DTR;
2879        if (clear & TIOCM_RTS)
2880                info->serial_signals &= ~SerialSignal_RTS;
2881        if (clear & TIOCM_DTR)
2882                info->serial_signals &= ~SerialSignal_DTR;
2883
2884        spin_lock_irqsave(&info->irq_spinlock,flags);
2885        usc_set_serial_signals(info);
2886        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2887
2888        return 0;
2889}
2890
2891/* mgsl_break()         Set or clear transmit break condition
2892 *
2893 * Arguments:           tty             pointer to tty instance data
2894 *                      break_state     -1=set break condition, 0=clear
2895 * Return Value:        error code
2896 */
2897static int mgsl_break(struct tty_struct *tty, int break_state)
2898{
2899        struct mgsl_struct * info = tty->driver_data;
2900        unsigned long flags;
2901        
2902        if (debug_level >= DEBUG_LEVEL_INFO)
2903                printk("%s(%d):mgsl_break(%s,%d)\n",
2904                         __FILE__,__LINE__, info->device_name, break_state);
2905                         
2906        if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2907                return -EINVAL;
2908
2909        spin_lock_irqsave(&info->irq_spinlock,flags);
2910        if (break_state == -1)
2911                usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2912        else 
2913                usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2914        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2915        return 0;
2916        
2917}       /* end of mgsl_break() */
2918
2919/*
2920 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2921 * Return: write counters to the user passed counter struct
2922 * NB: both 1->0 and 0->1 transitions are counted except for
2923 *     RI where only 0->1 is counted.
2924 */
2925static int msgl_get_icount(struct tty_struct *tty,
2926                                struct serial_icounter_struct *icount)
2927
2928{
2929        struct mgsl_struct * info = tty->driver_data;
2930        struct mgsl_icount cnow;        /* kernel counter temps */
2931        unsigned long flags;
2932
2933        spin_lock_irqsave(&info->irq_spinlock,flags);
2934        cnow = info->icount;
2935        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2936
2937        icount->cts = cnow.cts;
2938        icount->dsr = cnow.dsr;
2939        icount->rng = cnow.rng;
2940        icount->dcd = cnow.dcd;
2941        icount->rx = cnow.rx;
2942        icount->tx = cnow.tx;
2943        icount->frame = cnow.frame;
2944        icount->overrun = cnow.overrun;
2945        icount->parity = cnow.parity;
2946        icount->brk = cnow.brk;
2947        icount->buf_overrun = cnow.buf_overrun;
2948        return 0;
2949}
2950
2951/* mgsl_ioctl() Service an IOCTL request
2952 *      
2953 * Arguments:
2954 * 
2955 *      tty     pointer to tty instance data
2956 *      cmd     IOCTL command code
2957 *      arg     command argument/context
2958 *      
2959 * Return Value:        0 if success, otherwise error code
2960 */
2961static int mgsl_ioctl(struct tty_struct *tty,
2962                    unsigned int cmd, unsigned long arg)
2963{
2964        struct mgsl_struct * info = tty->driver_data;
2965        
2966        if (debug_level >= DEBUG_LEVEL_INFO)
2967                printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2968                        info->device_name, cmd );
2969        
2970        if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2971                return -ENODEV;
2972
2973        if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2974            (cmd != TIOCMIWAIT)) {
2975                if (tty->flags & (1 << TTY_IO_ERROR))
2976                    return -EIO;
2977        }
2978
2979        return mgsl_ioctl_common(info, cmd, arg);
2980}
2981
2982static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2983{
2984        void __user *argp = (void __user *)arg;
2985        
2986        switch (cmd) {
2987                case MGSL_IOCGPARAMS:
2988                        return mgsl_get_params(info, argp);
2989                case MGSL_IOCSPARAMS:
2990                        return mgsl_set_params(info, argp);
2991                case MGSL_IOCGTXIDLE:
2992                        return mgsl_get_txidle(info, argp);
2993                case MGSL_IOCSTXIDLE:
2994                        return mgsl_set_txidle(info,(int)arg);
2995                case MGSL_IOCTXENABLE:
2996                        return mgsl_txenable(info,(int)arg);
2997                case MGSL_IOCRXENABLE:
2998                        return mgsl_rxenable(info,(int)arg);
2999                case MGSL_IOCTXABORT:
3000                        return mgsl_txabort(info);
3001                case MGSL_IOCGSTATS:
3002                        return mgsl_get_stats(info, argp);
3003                case MGSL_IOCWAITEVENT:
3004                        return mgsl_wait_event(info, argp);
3005                case MGSL_IOCLOOPTXDONE:
3006                        return mgsl_loopmode_send_done(info);
3007                /* Wait for modem input (DCD,RI,DSR,CTS) change
3008                 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3009                 */
3010                case TIOCMIWAIT:
3011                        return modem_input_wait(info,(int)arg);
3012
3013                default:
3014                        return -ENOIOCTLCMD;
3015        }
3016        return 0;
3017}
3018
3019/* mgsl_set_termios()
3020 * 
3021 *      Set new termios settings
3022 *      
3023 * Arguments:
3024 * 
3025 *      tty             pointer to tty structure
3026 *      termios         pointer to buffer to hold returned old termios
3027 *      
3028 * Return Value:                None
3029 */
3030static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3031{
3032        struct mgsl_struct *info = tty->driver_data;
3033        unsigned long flags;
3034        
3035        if (debug_level >= DEBUG_LEVEL_INFO)
3036                printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3037                        tty->driver->name );
3038        
3039        mgsl_change_params(info);
3040
3041        /* Handle transition to B0 status */
3042        if (old_termios->c_cflag & CBAUD &&
3043            !(tty->termios.c_cflag & CBAUD)) {
3044                info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3045                spin_lock_irqsave(&info->irq_spinlock,flags);
3046                usc_set_serial_signals(info);
3047                spin_unlock_irqrestore(&info->irq_spinlock,flags);
3048        }
3049        
3050        /* Handle transition away from B0 status */
3051        if (!(old_termios->c_cflag & CBAUD) &&
3052            tty->termios.c_cflag & CBAUD) {
3053                info->serial_signals |= SerialSignal_DTR;
3054                if (!(tty->termios.c_cflag & CRTSCTS) || 
3055                    !test_bit(TTY_THROTTLED, &tty->flags)) {
3056                        info->serial_signals |= SerialSignal_RTS;
3057                }
3058                spin_lock_irqsave(&info->irq_spinlock,flags);
3059                usc_set_serial_signals(info);
3060                spin_unlock_irqrestore(&info->irq_spinlock,flags);
3061        }
3062        
3063        /* Handle turning off CRTSCTS */
3064        if (old_termios->c_cflag & CRTSCTS &&
3065            !(tty->termios.c_cflag & CRTSCTS)) {
3066                tty->hw_stopped = 0;
3067                mgsl_start(tty);
3068        }
3069
3070}       /* end of mgsl_set_termios() */
3071
3072/* mgsl_close()
3073 * 
3074 *      Called when port is closed. Wait for remaining data to be
3075 *      sent. Disable port and free resources.
3076 *      
3077 * Arguments:
3078 * 
3079 *      tty     pointer to open tty structure
3080 *      filp    pointer to open file object
3081 *      
3082 * Return Value:        None
3083 */
3084static void mgsl_close(struct tty_struct *tty, struct file * filp)
3085{
3086        struct mgsl_struct * info = tty->driver_data;
3087
3088        if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3089                return;
3090        
3091        if (debug_level >= DEBUG_LEVEL_INFO)
3092                printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3093                         __FILE__,__LINE__, info->device_name, info->port.count);
3094
3095        if (tty_port_close_start(&info->port, tty, filp) == 0)                   
3096                goto cleanup;
3097
3098        mutex_lock(&info->port.mutex);
3099        if (info->port.flags & ASYNC_INITIALIZED)
3100                mgsl_wait_until_sent(tty, info->timeout);
3101        mgsl_flush_buffer(tty);
3102        tty_ldisc_flush(tty);
3103        shutdown(info);
3104        mutex_unlock(&info->port.mutex);
3105
3106        tty_port_close_end(&info->port, tty);   
3107        info->port.tty = NULL;
3108cleanup:                        
3109        if (debug_level >= DEBUG_LEVEL_INFO)
3110                printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3111                        tty->driver->name, info->port.count);
3112                        
3113}       /* end of mgsl_close() */
3114
3115/* mgsl_wait_until_sent()
3116 *
3117 *      Wait until the transmitter is empty.
3118 *
3119 * Arguments:
3120 *
3121 *      tty             pointer to tty info structure
3122 *      timeout         time to wait for send completion
3123 *
3124 * Return Value:        None
3125 */
3126static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3127{
3128        struct mgsl_struct * info = tty->driver_data;
3129        unsigned long orig_jiffies, char_time;
3130
3131        if (!info )
3132                return;
3133
3134        if (debug_level >= DEBUG_LEVEL_INFO)
3135                printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3136                         __FILE__,__LINE__, info->device_name );
3137      
3138        if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3139                return;
3140
3141        if (!(info->port.flags & ASYNC_INITIALIZED))
3142                goto exit;
3143         
3144        orig_jiffies = jiffies;
3145      
3146        /* Set check interval to 1/5 of estimated time to
3147         * send a character, and make it at least 1. The check
3148         * interval should also be less than the timeout.
3149         * Note: use tight timings here to satisfy the NIST-PCTS.
3150         */ 
3151
3152        if ( info->params.data_rate ) {
3153                char_time = info->timeout/(32 * 5);
3154                if (!char_time)
3155                        char_time++;
3156        } else
3157                char_time = 1;
3158                
3159        if (timeout)
3160                char_time = min_t(unsigned long, char_time, timeout);
3161                
3162        if ( info->params.mode == MGSL_MODE_HDLC ||
3163                info->params.mode == MGSL_MODE_RAW ) {
3164                while (info->tx_active) {
3165                        msleep_interruptible(jiffies_to_msecs(char_time));
3166                        if (signal_pending(current))
3167                                break;
3168                        if (timeout && time_after(jiffies, orig_jiffies + timeout))
3169                                break;
3170                }
3171        } else {
3172                while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3173                        info->tx_enabled) {
3174                        msleep_interruptible(jiffies_to_msecs(char_time));
3175                        if (signal_pending(current))
3176                                break;
3177                        if (timeout && time_after(jiffies, orig_jiffies + timeout))
3178                                break;
3179                }
3180        }
3181      
3182exit:
3183        if (debug_level >= DEBUG_LEVEL_INFO)
3184                printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3185                         __FILE__,__LINE__, info->device_name );
3186                         
3187}       /* end of mgsl_wait_until_sent() */
3188
3189/* mgsl_hangup()
3190 *
3191 *      Called by tty_hangup() when a hangup is signaled.
3192 *      This is the same as to closing all open files for the port.
3193 *
3194 * Arguments:           tty     pointer to associated tty object
3195 * Return Value:        None
3196 */
3197static void mgsl_hangup(struct tty_struct *tty)
3198{
3199        struct mgsl_struct * info = tty->driver_data;
3200        
3201        if (debug_level >= DEBUG_LEVEL_INFO)
3202                printk("%s(%d):mgsl_hangup(%s)\n",
3203                         __FILE__,__LINE__, info->device_name );
3204                         
3205        if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3206                return;
3207
3208        mgsl_flush_buffer(tty);
3209        shutdown(info);
3210        
3211        info->port.count = 0;   
3212        info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3213        info->port.tty = NULL;
3214
3215        wake_up_interruptible(&info->port.open_wait);
3216        
3217}       /* end of mgsl_hangup() */
3218
3219/*
3220 * carrier_raised()
3221 *
3222 *      Return true if carrier is raised
3223 */
3224
3225static int carrier_raised(struct tty_port *port)
3226{
3227        unsigned long flags;
3228        struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3229        
3230        spin_lock_irqsave(&info->irq_spinlock, flags);
3231        usc_get_serial_signals(info);
3232        spin_unlock_irqrestore(&info->irq_spinlock, flags);
3233        return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3234}
3235
3236static void dtr_rts(struct tty_port *port, int on)
3237{
3238        struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3239        unsigned long flags;
3240
3241        spin_lock_irqsave(&info->irq_spinlock,flags);
3242        if (on)
3243                info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3244        else
3245                info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3246        usc_set_serial_signals(info);
3247        spin_unlock_irqrestore(&info->irq_spinlock,flags);
3248}
3249
3250
3251/* block_til_ready()
3252 * 
3253 *      Block the current process until the specified port
3254 *      is ready to be opened.
3255 *      
3256 * Arguments:
3257 * 
3258 *      tty             pointer to tty info structure
3259 *      filp            pointer to open file object
3260 *      info            pointer to device instance data
3261 *      
3262 * Return Value:        0 if success, otherwise error code
3263 */
3264static int block_til_ready(struct tty_struct *tty, struct file * filp,
3265                           struct mgsl_struct *info)
3266{
3267        DECLARE_WAITQUEUE(wait, current);
3268        int             retval;
3269        bool            do_clocal = false;
3270        bool            extra_count = false;
3271        unsigned long   flags;
3272        int             dcd;
3273        struct tty_port *port = &info->port;
3274        
3275        if (debug_level >= DEBUG_LEVEL_INFO)
3276                printk("%s(%d):block_til_ready on %s\n",
3277                         __FILE__,__LINE__, tty->driver->name );
3278
3279        if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3280                /* nonblock mode is set or port is not enabled */
3281                port->flags |= ASYNC_NORMAL_ACTIVE;
3282                return 0;
3283        }
3284
3285        if (tty->termios.c_cflag & CLOCAL)
3286                do_clocal = true;
3287
3288        /* Wait for carrier detect and the line to become
3289         * free (i.e., not in use by the callout).  While we are in
3290         * this loop, port->count is dropped by one, so that
3291         * mgsl_close() knows when to free things.  We restore it upon
3292         * exit, either normal or abnormal.
3293         */
3294         
3295        retval = 0;
3296        add_wait_queue(&port->open_wait, &wait);
3297        
3298        if (debug_level >= DEBUG_LEVEL_INFO)
3299                printk("%s(%d):block_til_ready before block on %s count=%d\n",
3300                         __FILE__,__LINE__, tty->driver->name, port->count );
3301
3302        spin_lock_irqsave(&info->irq_spinlock, flags);
3303        if (!tty_hung_up_p(filp)) {
3304                extra_count = true;
3305                port->count--;
3306        }
3307        spin_unlock_irqrestore(&info->irq_spinlock, flags);
3308        port->blocked_open++;
3309        
3310        while (1) {
3311                if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags))
3312                        tty_port_raise_dtr_rts(port);
3313                
3314                set_current_state(TASK_INTERRUPTIBLE);
3315                
3316                if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3317                        retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3318                                        -EAGAIN : -ERESTARTSYS;
3319                        break;
3320                }
3321                
3322                dcd = tty_port_carrier_raised(&info->port);
3323                
3324                if (!(port->flags & ASYNC_CLOSING) && (do_clocal || dcd))
3325                        break;
3326                        
3327                if (signal_pending(current)) {
3328                        retval = -ERESTARTSYS;
3329                        break;
3330                }
3331                
3332                if (debug_level >= DEBUG_LEVEL_INFO)
3333                        printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3334                                 __FILE__,__LINE__, tty->driver->name, port->count );
3335                                 
3336                tty_unlock(tty);
3337                schedule();
3338                tty_lock(tty);
3339        }
3340        
3341        set_current_state(TASK_RUNNING);
3342        remove_wait_queue(&port->open_wait, &wait);
3343        
3344        /* FIXME: Racy on hangup during close wait */
3345        if (extra_count)
3346                port->count++;
3347        port->blocked_open--;
3348        
3349        if (debug_level >= DEBUG_LEVEL_INFO)
3350                printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3351                         __FILE__,__LINE__, tty->driver->name, port->count );
3352                         
3353        if (!retval)
3354                port->flags |= ASYNC_NORMAL_ACTIVE;
3355                
3356        return retval;
3357        
3358}       /* end of block_til_ready() */
3359
3360static int mgsl_install(struct tty_driver *driver, struct tty_struct *tty)
3361{
3362        struct mgsl_struct *info;
3363        int line = tty->index;
3364
3365        /* verify range of specified line number */
3366        if (line >= mgsl_device_count) {
3367                printk("%s(%d):mgsl_open with invalid line #%d.\n",
3368                        __FILE__, __LINE__, line);
3369                return -ENODEV;
3370        }
3371
3372        /* find the info structure for the specified line */
3373        info = mgsl_device_list;
3374        while (info && info->line != line)
3375                info = info->next_device;
3376        if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3377                return -ENODEV;
3378        tty->driver_data = info;
3379
3380        return tty_port_install(&info->port, driver, tty);
3381}
3382
3383/* mgsl_open()
3384 *
3385 *      Called when a port is opened.  Init and enable port.
3386 *      Perform serial-specific initialization for the tty structure.
3387 *
3388 * Arguments:           tty     pointer to tty info structure
3389 *                      filp    associated file pointer
3390 *
3391 * Return Value:        0 if success, otherwise error code
3392 */
3393static int mgsl_open(struct tty_struct *tty, struct file * filp)
3394{
3395        struct mgsl_struct *info = tty->driver_data;
3396        unsigned long flags;
3397        int retval;
3398
3399        info->port.tty = tty;
3400                
3401        if (debug_level >= DEBUG_LEVEL_INFO)
3402                printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3403                         __FILE__,__LINE__,tty->driver->name, info->port.count);
3404
3405        /* If port is closing, signal caller to try again */
3406        if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
3407                if (info->port.flags & ASYNC_CLOSING)
3408                        interruptible_sleep_on(&info->port.close_wait);
3409                retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
3410                        -EAGAIN : -ERESTARTSYS);
3411                goto cleanup;
3412        }
3413        
3414        info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3415
3416        spin_lock_irqsave(&info->netlock, flags);
3417        if (info->netcount) {
3418                retval = -EBUSY;
3419                spin_unlock_irqrestore(&info->netlock, flags);
3420                goto cleanup;
3421        }
3422        info->port.count++;
3423        spin_unlock_irqrestore(&info->netlock, flags);
3424
3425        if (info->port.count == 1) {
3426                /* 1st open on this device, init hardware */
3427                retval = startup(info);
3428                if (retval < 0)
3429                        goto cleanup;
3430        }
3431
3432        retval = block_til_ready(tty, filp, info);
3433        if (retval) {
3434                if (debug_level >= DEBUG_LEVEL_INFO)
3435                        printk("%s(%d):block_til_ready(%s) returned %d\n",
3436                                 __FILE__,__LINE__, info->device_name, retval);
3437                goto cleanup;
3438        }
3439
3440        if (debug_level >= DEBUG_LEVEL_INFO)
3441                printk("%s(%d):mgsl_open(%s) success\n",
3442                         __FILE__,__LINE__, info->device_name);
3443        retval = 0;
3444        
3445cleanup:                        
3446        if (retval) {
3447                if (tty->count == 1)
3448                        info->port.tty = NULL; /* tty layer will release tty struct */
3449                if(info->port.count)
3450                        info->port.count--;
3451        }
3452        
3453        return retval;
3454        
3455}       /* end of mgsl_open() */
3456
3457/*
3458 * /proc fs routines....
3459 */
3460
3461static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
3462{
3463        char    stat_buf[30];
3464        unsigned long flags;
3465
3466        if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3467                seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3468                        info->device_name, info->io_base, info->irq_level,
3469                        info->phys_memory_base, info->phys_lcr_base);
3470        } else {
3471                seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
3472                        info->device_name, info->io_base, 
3473                        info->irq_level, info->dma_level);
3474        }
3475
3476        /* output current serial signal states */
3477        spin_lock_irqsave(&info->irq_spinlock,flags);
3478        usc_get_serial_signals(info);
3479        spin_unlock_irqrestore(&info->irq_spinlock,flags);
3480        
3481        stat_buf[0] = 0;
3482        stat_buf[1] = 0;
3483        if (info->serial_signals & SerialSignal_RTS)
3484                strcat(stat_buf, "|RTS");
3485        if (info->serial_signals & SerialSignal_CTS)
3486                strcat(stat_buf, "|CTS");
3487        if (info->serial_signals & SerialSignal_DTR)
3488                strcat(stat_buf, "|DTR");
3489        if (info->serial_signals & SerialSignal_DSR)
3490                strcat(stat_buf, "|DSR");
3491        if (info->serial_signals & SerialSignal_DCD)
3492                strcat(stat_buf, "|CD");
3493        if (info->serial_signals & SerialSignal_RI)
3494                strcat(stat_buf, "|RI");
3495
3496        if (info->params.mode == MGSL_MODE_HDLC ||
3497            info->params.mode == MGSL_MODE_RAW ) {
3498                seq_printf(m, " HDLC txok:%d rxok:%d",
3499                              info->icount.txok, info->icount.rxok);
3500                if (info->icount.txunder)
3501                        seq_printf(m, " txunder:%d", info->icount.txunder);
3502                if (info->icount.txabort)
3503                        seq_printf(m, " txabort:%d", info->icount.txabort);
3504                if (info->icount.rxshort)
3505                        seq_printf(m, " rxshort:%d", info->icount.rxshort);
3506                if (info->icount.rxlong)
3507                        seq_printf(m, " rxlong:%d", info->icount.rxlong);
3508                if (info->icount.rxover)
3509                        seq_printf(m, " rxover:%d", info->icount.rxover);
3510                if (info->icount.rxcrc)
3511                        seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
3512        } else {
3513                seq_printf(m, " ASYNC tx:%d rx:%d",
3514                              info->icount.tx, info->icount.rx);
3515                if (info->icount.frame)
3516                        seq_printf(m, " fe:%d", info->icount.frame);
3517                if (info->icount.parity)
3518                        seq_printf(m, " pe:%d", info->icount.parity);
3519                if (info->icount.brk)
3520                        seq_printf(m, " brk:%d", info->icount.brk);
3521                if (info->icount.overrun)
3522                        seq_printf(m, " oe:%d", info->icount.overrun);
3523        }
3524        
3525        /* Append serial signal status to end */
3526        seq_printf(m, " %s\n", stat_buf+1);
3527        
3528        seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3529         info->tx_active,info->bh_requested,info->bh_running,
3530         info->pending_bh);
3531         
3532        spin_lock_irqsave(&info->irq_spinlock,flags);
3533        {       
3534        u16 Tcsr = usc_InReg( info, TCSR );
3535        u16 Tdmr = usc_InDmaReg( info, TDMR );
3536        u16 Ticr = usc_InReg( info, TICR );
3537        u16 Rscr = usc_InReg( info, RCSR );
3538        u16 Rdmr = usc_InDmaReg( info, RDMR );
3539        u16 Ricr = usc_InReg( info, RICR );
3540        u16 Icr = usc_InReg( info, ICR );
3541        u16 Dccr = usc_InReg( info, DCCR );
3542        u16 Tmr = usc_InReg( info, TMR );
3543        u16 Tccr = usc_InReg( info, TCCR );
3544        u16 Ccar = inw( info->io_base + CCAR );
3545        seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3546                        "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3547                        Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3548        }
3549        spin_unlock_irqrestore(&info->irq_spinlock,flags);
3550}
3551
3552/* Called to print information about devices */
3553static int mgsl_proc_show(struct seq_file *m, void *v)
3554{
3555        struct mgsl_struct *info;
3556        
3557        seq_printf(m, "synclink driver:%s\n", driver_version);
3558        
3559        info = mgsl_device_list;
3560        while( info ) {
3561                line_info(m, info);
3562                info = info->next_device;
3563        }
3564        return 0;
3565}
3566
3567static int mgsl_proc_open(struct inode *inode, struct file *file)
3568{
3569        return single_open(file, mgsl_proc_show, NULL);
3570}
3571
3572static const struct file_operations mgsl_proc_fops = {
3573        .owner          = THIS_MODULE,
3574        .open           = mgsl_proc_open,
3575        .read           = seq_read,
3576        .llseek         = seq_lseek,
3577        .release        = single_release,
3578};
3579
3580/* mgsl_allocate_dma_buffers()
3581 * 
3582 *      Allocate and format DMA buffers (ISA adapter)
3583 *      or format shared memory buffers (PCI adapter).
3584 * 
3585 * Arguments:           info    pointer to device instance data
3586 * Return Value:        0 if success, otherwise error
3587 */
3588static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3589{
3590        unsigned short BuffersPerFrame;
3591
3592        info->last_mem_alloc = 0;
3593
3594        /* Calculate the number of DMA buffers necessary to hold the */
3595        /* largest allowable frame size. Note: If the max frame size is */
3596        /* not an even multiple of the DMA buffer size then we need to */
3597        /* round the buffer count per frame up one. */
3598
3599        BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3600        if ( info->max_frame_size % DMABUFFERSIZE )
3601                BuffersPerFrame++;
3602
3603        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3604                /*
3605                 * The PCI adapter has 256KBytes of shared memory to use.
3606                 * This is 64 PAGE_SIZE buffers.
3607                 *
3608                 * The first page is used for padding at this time so the
3609                 * buffer list does not begin at offset 0 of the PCI
3610                 * adapter's shared memory.
3611                 *
3612                 * The 2nd page is used for the buffer list. A 4K buffer
3613                 * list can hold 128 DMA_BUFFER structures at 32 bytes
3614                 * each.
3615                 *
3616                 * This leaves 62 4K pages.
3617                 *
3618                 * The next N pages are used for transmit frame(s). We
3619                 * reserve enough 4K page blocks to hold the required
3620                 * number of transmit dma buffers (num_tx_dma_buffers),
3621                 * each of MaxFrameSize size.
3622                 *
3623                 * Of the remaining pages (62-N), determine how many can
3624                 * be used to receive full MaxFrameSize inbound frames
3625                 */
3626                info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3627                info->rx_buffer_count = 62 - info->tx_buffer_count;
3628        } else {
3629                /* Calculate the number of PAGE_SIZE buffers needed for */
3630                /* receive and transmit DMA buffers. */
3631
3632
3633                /* Calculate the number of DMA buffers necessary to */
3634                /* hold 7 max size receive frames and one max size transmit frame. */
3635                /* The receive buffer count is bumped by one so we avoid an */
3636                /* End of List condition if all receive buffers are used when */
3637                /* using linked list DMA buffers. */
3638
3639                info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3640                info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3641                
3642                /* 
3643                 * limit total TxBuffers & RxBuffers to 62 4K total 
3644                 * (ala PCI Allocation) 
3645                 */
3646                
3647                if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3648                        info->rx_buffer_count = 62 - info->tx_buffer_count;
3649
3650        }
3651
3652        if ( debug_level >= DEBUG_LEVEL_INFO )
3653                printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3654                        __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3655        
3656        if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3657                  mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 || 
3658                  mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 || 
3659                  mgsl_alloc_intermediate_rxbuffer_memory(info) < 0  ||
3660                  mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3661                printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3662                return -ENOMEM;
3663        }
3664        
3665        mgsl_reset_rx_dma_buffers( info );
3666        mgsl_reset_tx_dma_buffers( info );
3667
3668        return 0;
3669
3670}       /* end of mgsl_allocate_dma_buffers() */
3671
3672/*
3673 * mgsl_alloc_buffer_list_memory()
3674 * 
3675 * Allocate a common DMA buffer for use as the
3676 * receive and transmit buffer lists.
3677 * 
3678 * A buffer list is a set of buffer entries where each entry contains
3679 * a pointer to an actual buffer and a pointer to the next buffer entry
3680 * (plus some other info about the buffer).
3681 * 
3682 * The buffer entries for a list are built to form a circular list so
3683 * that when the entire list has been traversed you start back at the
3684 * beginning.
3685 * 
3686 * This function allocates memory for just the buffer entries.
3687 * The links (pointer to next entry) are filled in with the physical
3688 * address of the next entry so the adapter can navigate the list
3689 * using bus master DMA. The pointers to the actual buffers are filled
3690 * out later when the actual buffers are allocated.
3691 * 
3692 * Arguments:           info    pointer to device instance data
3693 * Return Value:        0 if success, otherwise error
3694 */
3695static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3696{
3697        unsigned int i;
3698
3699        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3700                /* PCI adapter uses shared memory. */
3701                info->buffer_list = info->memory_base + info->last_mem_alloc;
3702                info->buffer_list_phys = info->last_mem_alloc;
3703                info->last_mem_alloc += BUFFERLISTSIZE;
3704        } else {
3705                /* ISA adapter uses system memory. */
3706                /* The buffer lists are allocated as a common buffer that both */
3707                /* the processor and adapter can access. This allows the driver to */
3708                /* inspect portions of the buffer while other portions are being */
3709                /* updated by the adapter using Bus Master DMA. */
3710
3711                info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3712                if (info->buffer_list == NULL)
3713                        return -ENOMEM;
3714                info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3715        }
3716
3717        /* We got the memory for the buffer entry lists. */
3718        /* Initialize the memory block to all zeros. */
3719        memset( info->buffer_list, 0, BUFFERLISTSIZE );
3720
3721        /* Save virtual address pointers to the receive and */
3722        /* transmit buffer lists. (Receive 1st). These pointers will */
3723        /* be used by the processor to access the lists. */
3724        info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3725        info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3726        info->tx_buffer_list += info->rx_buffer_count;
3727
3728        /*
3729         * Build the links for the buffer entry lists such that
3730         * two circular lists are built. (Transmit and Receive).
3731         *
3732         * Note: the links are physical addresses
3733         * which are read by the adapter to determine the next
3734         * buffer entry to use.
3735         */
3736
3737        for ( i = 0; i < info->rx_buffer_count; i++ ) {
3738                /* calculate and store physical address of this buffer entry */
3739                info->rx_buffer_list[i].phys_entry =
3740                        info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3741
3742                /* calculate and store physical address of */
3743                /* next entry in cirular list of entries */
3744
3745                info->rx_buffer_list[i].link = info->buffer_list_phys;
3746
3747                if ( i < info->rx_buffer_count - 1 )
3748                        info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3749        }
3750
3751        for ( i = 0; i < info->tx_buffer_count; i++ ) {
3752                /* calculate and store physical address of this buffer entry */
3753                info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3754                        ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3755
3756                /* calculate and store physical address of */
3757                /* next entry in cirular list of entries */
3758
3759                info->tx_buffer_list[i].link = info->buffer_list_phys +
3760                        info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3761
3762                if ( i < info->tx_buffer_count - 1 )
3763                        info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3764        }
3765
3766        return 0;
3767
3768}       /* end of mgsl_alloc_buffer_list_memory() */
3769
3770/* Free DMA buffers allocated for use as the
3771 * receive and transmit buffer lists.
3772 * Warning:
3773 * 
3774 *      The data transfer buffers associated with the buffer list
3775 *      MUST be freed before freeing the buffer list itself because
3776 *      the buffer list contains the information necessary to free
3777 *      the individual buffers!
3778 */
3779static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3780{
3781        if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3782                dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3783                
3784        info->buffer_list = NULL;
3785        info->rx_buffer_list = NULL;
3786        info->tx_buffer_list = NULL;
3787
3788}       /* end of mgsl_free_buffer_list_memory() */
3789
3790/*
3791 * mgsl_alloc_frame_memory()
3792 * 
3793 *      Allocate the frame DMA buffers used by the specified buffer list.
3794 *      Each DMA buffer will be one memory page in size. This is necessary
3795 *      because memory can fragment enough that it may be impossible
3796 *      contiguous pages.
3797 * 
3798 * Arguments:
3799 * 
3800 *      info            pointer to device instance data
3801 *      BufferList      pointer to list of buffer entries
3802 *      Buffercount     count of buffer entries in buffer list
3803 * 
3804 * Return Value:        0 if success, otherwise -ENOMEM
3805 */
3806static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3807{
3808        int i;
3809        u32 phys_addr;
3810
3811        /* Allocate page sized buffers for the receive buffer list */
3812
3813        for ( i = 0; i < Buffercount; i++ ) {
3814                if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3815                        /* PCI adapter uses shared memory buffers. */
3816                        BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3817                        phys_addr = info->last_mem_alloc;
3818                        info->last_mem_alloc += DMABUFFERSIZE;
3819                } else {
3820                        /* ISA adapter uses system memory. */
3821                        BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3822                        if (BufferList[i].virt_addr == NULL)
3823                                return -ENOMEM;
3824                        phys_addr = (u32)(BufferList[i].dma_addr);
3825                }
3826                BufferList[i].phys_addr = phys_addr;
3827        }
3828
3829        return 0;
3830
3831}       /* end of mgsl_alloc_frame_memory() */
3832
3833/*
3834 * mgsl_free_frame_memory()
3835 * 
3836 *      Free the buffers associated with
3837 *      each buffer entry of a buffer list.
3838 * 
3839 * Arguments:
3840 * 
3841 *      info            pointer to device instance data
3842 *      BufferList      pointer to list of buffer entries
3843 *      Buffercount     count of buffer entries in buffer list
3844 * 
3845 * Return Value:        None
3846 */
3847static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3848{
3849        int i;
3850
3851        if ( BufferList ) {
3852                for ( i = 0 ; i < Buffercount ; i++ ) {
3853                        if ( BufferList[i].virt_addr ) {
3854                                if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3855                                        dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3856                                BufferList[i].virt_addr = NULL;
3857                        }
3858                }
3859        }
3860
3861}       /* end of mgsl_free_frame_memory() */
3862
3863/* mgsl_free_dma_buffers()
3864 * 
3865 *      Free DMA buffers
3866 *      
3867 * Arguments:           info    pointer to device instance data
3868 * Return Value:        None
3869 */
3870static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3871{
3872        mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3873        mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3874        mgsl_free_buffer_list_memory( info );
3875
3876}       /* end of mgsl_free_dma_buffers() */
3877
3878
3879/*
3880 * mgsl_alloc_intermediate_rxbuffer_memory()
3881 * 
3882 *      Allocate a buffer large enough to hold max_frame_size. This buffer
3883 *      is used to pass an assembled frame to the line discipline.
3884 * 
3885 * Arguments:
3886 * 
3887 *      info            pointer to device instance data
3888 * 
3889 * Return Value:        0 if success, otherwise -ENOMEM
3890 */
3891static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3892{
3893        info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3894        if ( info->intermediate_rxbuffer == NULL )
3895                return -ENOMEM;
3896        /* unused flag buffer to satisfy receive_buf calling interface */
3897        info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3898        if (!info->flag_buf) {
3899                kfree(info->intermediate_rxbuffer);
3900                info->intermediate_rxbuffer = NULL;
3901                return -ENOMEM;
3902        }
3903        return 0;
3904
3905}       /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3906
3907/*
3908 * mgsl_free_intermediate_rxbuffer_memory()
3909 * 
3910 * 
3911 * Arguments:
3912 * 
3913 *      info            pointer to device instance data
3914 * 
3915 * Return Value:        None
3916 */
3917static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3918{
3919        kfree(info->intermediate_rxbuffer);
3920        info->intermediate_rxbuffer = NULL;
3921        kfree(info->flag_buf);
3922        info->flag_buf = NULL;
3923
3924}       /* end of mgsl_free_intermediate_rxbuffer_memory() */
3925
3926/*
3927 * mgsl_alloc_intermediate_txbuffer_memory()
3928 *
3929 *      Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3930 *      This buffer is used to load transmit frames into the adapter's dma transfer
3931 *      buffers when there is sufficient space.
3932 *
3933 * Arguments:
3934 *
3935 *      info            pointer to device instance data
3936 *
3937 * Return Value:        0 if success, otherwise -ENOMEM
3938 */
3939static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3940{
3941        int i;
3942
3943        if ( debug_level >= DEBUG_LEVEL_INFO )
3944                printk("%s %s(%d)  allocating %d tx holding buffers\n",
3945                                info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3946
3947        memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3948
3949        for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3950                info->tx_holding_buffers[i].buffer =
3951                        kmalloc(info->max_frame_size, GFP_KERNEL);
3952                if (info->tx_holding_buffers[i].buffer == NULL) {
3953                        for (--i; i >= 0; i--) {
3954                                kfree(info->tx_holding_buffers[i].buffer);
3955                                info->tx_holding_buffers[i].buffer = NULL;
3956                        }
3957                        return -ENOMEM;
3958                }
3959        }
3960
3961        return 0;
3962
3963}       /* end of mgsl_alloc_intermediate_txbuffer_memory() */
3964
3965/*
3966 * mgsl_free_intermediate_txbuffer_memory()
3967 *
3968 *
3969 * Arguments:
3970 *
3971 *      info            pointer to device instance data
3972 *
3973 * Return Value:        None
3974 */
3975static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
3976{
3977        int i;
3978
3979        for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
3980                kfree(info->tx_holding_buffers[i].buffer);
3981                info->tx_holding_buffers[i].buffer = NULL;
3982        }
3983
3984        info->get_tx_holding_index = 0;
3985        info->put_tx_holding_index = 0;
3986        info->tx_holding_count = 0;
3987
3988}       /* end of mgsl_free_intermediate_txbuffer_memory() */
3989
3990
3991/*
3992 * load_next_tx_holding_buffer()
3993 *
3994 * attempts to load the next buffered tx request into the
3995 * tx dma buffers
3996 *
3997 * Arguments:
3998 *
3999 *      info            pointer to device instance data
4000 *
4001 * Return Value:        true if next buffered tx request loaded
4002 *                      into adapter's tx dma buffer,
4003 *                      false otherwise
4004 */
4005static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
4006{
4007        bool ret = false;
4008
4009        if ( info->tx_holding_count ) {
4010                /* determine if we have enough tx dma buffers
4011                 * to accommodate the next tx frame
4012                 */
4013                struct tx_holding_buffer *ptx =
4014                        &info->tx_holding_buffers[info->get_tx_holding_index];
4015                int num_free = num_free_tx_dma_buffers(info);
4016                int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4017                if ( ptx->buffer_size % DMABUFFERSIZE )
4018                        ++num_needed;
4019
4020                if (num_needed <= num_free) {
4021                        info->xmit_cnt = ptx->buffer_size;
4022                        mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4023
4024                        --info->tx_holding_count;
4025                        if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4026                                info->get_tx_holding_index=0;
4027
4028                        /* restart transmit timer */
4029                        mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4030
4031                        ret = true;
4032                }
4033        }
4034
4035        return ret;
4036}
4037
4038/*
4039 * save_tx_buffer_request()
4040 *
4041 * attempt to store transmit frame request for later transmission
4042 *
4043 * Arguments:
4044 *
4045 *      info            pointer to device instance data
4046 *      Buffer          pointer to buffer containing frame to load
4047 *      BufferSize      size in bytes of frame in Buffer
4048 *
4049 * Return Value:        1 if able to store, 0 otherwise
4050 */
4051static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4052{
4053        struct tx_holding_buffer *ptx;
4054
4055        if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4056                return 0;               /* all buffers in use */
4057        }
4058
4059        ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4060        ptx->buffer_size = BufferSize;
4061        memcpy( ptx->buffer, Buffer, BufferSize);
4062
4063        ++info->tx_holding_count;
4064        if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4065                info->put_tx_holding_index=0;
4066
4067        return 1;
4068}
4069
4070static int mgsl_claim_resources(struct mgsl_struct *info)
4071{
4072        if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4073                printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4074                        __FILE__,__LINE__,info->device_name, info->io_base);
4075                return -ENODEV;
4076        }
4077        info->io_addr_requested = true;
4078        
4079        if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4080                info->device_name, info ) < 0 ) {
4081                printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n",
4082                        __FILE__,__LINE__,info->device_name, info->irq_level );
4083                goto errout;
4084        }
4085        info->irq_requested = true;
4086        
4087        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4088                if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4089                        printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4090                                __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4091                        goto errout;
4092                }
4093                info->shared_mem_requested = true;
4094                if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4095                        printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4096                                __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4097                        goto errout;
4098                }
4099                info->lcr_mem_requested = true;
4100
4101                info->memory_base = ioremap_nocache(info->phys_memory_base,
4102                                                                0x40000);
4103                if (!info->memory_base) {
4104                        printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
4105                                __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4106                        goto errout;
4107                }
4108                
4109                if ( !mgsl_memory_test(info) ) {
4110                        printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4111                                __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4112                        goto errout;
4113                }
4114                
4115                info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4116                                                                PAGE_SIZE);
4117                if (!info->lcr_base) {
4118                        printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
4119                                __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4120                        goto errout;
4121                }
4122                info->lcr_base += info->lcr_offset;
4123                
4124        } else {
4125                /* claim DMA channel */
4126                
4127                if (request_dma(info->dma_level,info->device_name) < 0){
4128                        printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n",
4129                                __FILE__,__LINE__,info->device_name, info->dma_level );
4130                        mgsl_release_resources( info );
4131                        return -ENODEV;
4132                }
4133                info->dma_requested = true;
4134
4135                /* ISA adapter uses bus master DMA */           
4136                set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4137                enable_dma(info->dma_level);
4138        }
4139        
4140        if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4141                printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
4142                        __FILE__,__LINE__,info->device_name, info->dma_level );
4143                goto errout;
4144        }       
4145        
4146        return 0;
4147errout:
4148        mgsl_release_resources(info);
4149        return -ENODEV;
4150
4151}       /* end of mgsl_claim_resources() */
4152
4153static void mgsl_release_resources(struct mgsl_struct *info)
4154{
4155        if ( debug_level >= DEBUG_LEVEL_INFO )
4156                printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4157                        __FILE__,__LINE__,info->device_name );
4158                        
4159        if ( info->irq_requested ) {
4160                free_irq(info->irq_level, info);
4161                info->irq_requested = false;
4162        }
4163        if ( info->dma_requested ) {
4164                disable_dma(info->dma_level);
4165                free_dma(info->dma_level);
4166                info->dma_requested = false;
4167        }
4168        mgsl_free_dma_buffers(info);
4169        mgsl_free_intermediate_rxbuffer_memory(info);
4170        mgsl_free_intermediate_txbuffer_memory(info);
4171        
4172        if ( info->io_addr_requested ) {
4173                release_region(info->io_base,info->io_addr_size);
4174                info->io_addr_requested = false;
4175        }
4176        if ( info->shared_mem_requested ) {
4177                release_mem_region(info->phys_memory_base,0x40000);
4178                info->shared_mem_requested = false;
4179        }
4180        if ( info->lcr_mem_requested ) {
4181                release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4182                info->lcr_mem_requested = false;
4183        }
4184        if (info->memory_base){
4185                iounmap(info->memory_base);
4186                info->memory_base = NULL;
4187        }
4188        if (info->lcr_base){
4189                iounmap(info->lcr_base - info->lcr_offset);
4190                info->lcr_base = NULL;
4191        }
4192        
4193        if ( debug_level >= DEBUG_LEVEL_INFO )
4194                printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4195                        __FILE__,__LINE__,info->device_name );
4196                        
4197}       /* end of mgsl_release_resources() */
4198
4199/* mgsl_add_device()
4200 * 
4201 *      Add the specified device instance data structure to the
4202 *      global linked list of devices and increment the device count.
4203 *      
4204 * Arguments:           info    pointer to device instance data
4205 * Return Value:        None
4206 */
4207static void mgsl_add_device( struct mgsl_struct *info )
4208{
4209        info->next_device = NULL;
4210        info->line = mgsl_device_count;
4211        sprintf(info->device_name,"ttySL%d",info->line);
4212        
4213        if (info->line < MAX_TOTAL_DEVICES) {
4214                if (maxframe[info->line])
4215                        info->max_frame_size = maxframe[info->line];
4216
4217                if (txdmabufs[info->line]) {
4218                        info->num_tx_dma_buffers = txdmabufs[info->line];
4219                        if (info->num_tx_dma_buffers < 1)
4220                                info->num_tx_dma_buffers = 1;
4221                }
4222
4223                if (txholdbufs[info->line]) {
4224                        info->num_tx_holding_buffers = txholdbufs[info->line];
4225                        if (info->num_tx_holding_buffers < 1)
4226                                info->num_tx_holding_buffers = 1;
4227                        else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4228                                info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4229                }
4230        }
4231
4232        mgsl_device_count++;
4233        
4234        if ( !mgsl_device_list )
4235                mgsl_device_list = info;
4236        else {  
4237                struct mgsl_struct *current_dev = mgsl_device_list;
4238                while( current_dev->next_device )
4239                        current_dev = current_dev->next_device;
4240                current_dev->next_device = info;
4241        }
4242        
4243        if ( info->max_frame_size < 4096 )
4244                info->max_frame_size = 4096;
4245        else if ( info->max_frame_size > 65535 )
4246                info->max_frame_size = 65535;
4247        
4248        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4249                printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4250                        info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4251                        info->phys_memory_base, info->phys_lcr_base,
4252                        info->max_frame_size );
4253        } else {
4254                printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4255                        info->device_name, info->io_base, info->irq_level, info->dma_level,
4256                        info->max_frame_size );
4257        }
4258
4259#if SYNCLINK_GENERIC_HDLC
4260        hdlcdev_init(info);
4261#endif
4262
4263}       /* end of mgsl_add_device() */
4264
4265static const struct tty_port_operations mgsl_port_ops = {
4266        .carrier_raised = carrier_raised,
4267        .dtr_rts = dtr_rts,
4268};
4269
4270
4271/* mgsl_allocate_device()
4272 * 
4273 *      Allocate and initialize a device instance structure
4274 *      
4275 * Arguments:           none
4276 * Return Value:        pointer to mgsl_struct if success, otherwise NULL
4277 */
4278static struct mgsl_struct* mgsl_allocate_device(void)
4279{
4280        struct mgsl_struct *info;
4281        
4282        info = kzalloc(sizeof(struct mgsl_struct),
4283                 GFP_KERNEL);
4284                 
4285        if (!info) {
4286                printk("Error can't allocate device instance data\n");
4287        } else {
4288                tty_port_init(&info->port);
4289                info->port.ops = &mgsl_port_ops;
4290                info->magic = MGSL_MAGIC;
4291                INIT_WORK(&info->task, mgsl_bh_handler);
4292                info->max_frame_size = 4096;
4293                info->port.close_delay = 5*HZ/10;
4294                info->port.closing_wait = 30*HZ;
4295                init_waitqueue_head(&info->status_event_wait_q);
4296                init_waitqueue_head(&info->event_wait_q);
4297                spin_lock_init(&info->irq_spinlock);
4298                spin_lock_init(&info->netlock);
4299                memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4300                info->idle_mode = HDLC_TXIDLE_FLAGS;            
4301                info->num_tx_dma_buffers = 1;
4302                info->num_tx_holding_buffers = 0;
4303        }
4304        
4305        return info;
4306
4307}       /* end of mgsl_allocate_device()*/
4308
4309static const struct tty_operations mgsl_ops = {
4310        .install = mgsl_install,
4311        .open = mgsl_open,
4312        .close = mgsl_close,
4313        .write = mgsl_write,
4314        .put_char = mgsl_put_char,
4315        .flush_chars = mgsl_flush_chars,
4316        .write_room = mgsl_write_room,
4317        .chars_in_buffer = mgsl_chars_in_buffer,
4318        .flush_buffer = mgsl_flush_buffer,
4319        .ioctl = mgsl_ioctl,
4320        .throttle = mgsl_throttle,
4321        .unthrottle = mgsl_unthrottle,
4322        .send_xchar = mgsl_send_xchar,
4323        .break_ctl = mgsl_break,
4324        .wait_until_sent = mgsl_wait_until_sent,
4325        .set_termios = mgsl_set_termios,
4326        .stop = mgsl_stop,
4327        .start = mgsl_start,
4328        .hangup = mgsl_hangup,
4329        .tiocmget = tiocmget,
4330        .tiocmset = tiocmset,
4331        .get_icount = msgl_get_icount,
4332        .proc_fops = &mgsl_proc_fops,
4333};
4334
4335/*
4336 * perform tty device initialization
4337 */
4338static int mgsl_init_tty(void)
4339{
4340        int rc;
4341
4342        serial_driver = alloc_tty_driver(128);
4343        if (!serial_driver)
4344                return -ENOMEM;
4345        
4346        serial_driver->driver_name = "synclink";
4347        serial_driver->name = "ttySL";
4348        serial_driver->major = ttymajor;
4349        serial_driver->minor_start = 64;
4350        serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4351        serial_driver->subtype = SERIAL_TYPE_NORMAL;
4352        serial_driver->init_termios = tty_std_termios;
4353        serial_driver->init_termios.c_cflag =
4354                B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4355        serial_driver->init_termios.c_ispeed = 9600;
4356        serial_driver->init_termios.c_ospeed = 9600;
4357        serial_driver->flags = TTY_DRIVER_REAL_RAW;
4358        tty_set_operations(serial_driver, &mgsl_ops);
4359        if ((rc = tty_register_driver(serial_driver)) < 0) {
4360                printk("%s(%d):Couldn't register serial driver\n",
4361                        __FILE__,__LINE__);
4362                put_tty_driver(serial_driver);
4363                serial_driver = NULL;
4364                return rc;
4365        }
4366                        
4367        printk("%s %s, tty major#%d\n",
4368                driver_name, driver_version,
4369                serial_driver->major);
4370        return 0;
4371}
4372
4373/* enumerate user specified ISA adapters
4374 */
4375static void mgsl_enum_isa_devices(void)
4376{
4377        struct mgsl_struct *info;
4378        int i;
4379                
4380        /* Check for user specified ISA devices */
4381        
4382        for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4383                if ( debug_level >= DEBUG_LEVEL_INFO )
4384                        printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4385                                io[i], irq[i], dma[i] );
4386                
4387                info = mgsl_allocate_device();
4388                if ( !info ) {
4389                        /* error allocating device instance data */
4390                        if ( debug_level >= DEBUG_LEVEL_ERROR )
4391                                printk( "can't allocate device instance data.\n");
4392                        continue;
4393                }
4394                
4395                /* Copy user configuration info to device instance data */
4396                info->io_base = (unsigned int)io[i];
4397                info->irq_level = (unsigned int)irq[i];
4398                info->irq_level = irq_canonicalize(info->irq_level);
4399                info->dma_level = (unsigned int)dma[i];
4400                info->bus_type = MGSL_BUS_TYPE_ISA;
4401                info->io_addr_size = 16;
4402                info->irq_flags = 0;
4403                
4404                mgsl_add_device( info );
4405        }
4406}
4407
4408static void synclink_cleanup(void)
4409{
4410        int rc;
4411        struct mgsl_struct *info;
4412        struct mgsl_struct *tmp;
4413
4414        printk("Unloading %s: %s\n", driver_name, driver_version);
4415
4416        if (serial_driver) {
4417                if ((rc = tty_unregister_driver(serial_driver)))
4418                        printk("%s(%d) failed to unregister tty driver err=%d\n",
4419                               __FILE__,__LINE__,rc);
4420                put_tty_driver(serial_driver);
4421        }
4422
4423        info = mgsl_device_list;
4424        while(info) {
4425#if SYNCLINK_GENERIC_HDLC
4426                hdlcdev_exit(info);
4427#endif
4428                mgsl_release_resources(info);
4429                tmp = info;
4430                info = info->next_device;
4431                tty_port_destroy(&tmp->port);
4432                kfree(tmp);
4433        }
4434        
4435        if (pci_registered)
4436                pci_unregister_driver(&synclink_pci_driver);
4437}
4438
4439static int __init synclink_init(void)
4440{
4441        int rc;
4442
4443        if (break_on_load) {
4444                mgsl_get_text_ptr();
4445                BREAKPOINT();
4446        }
4447
4448        printk("%s %s\n", driver_name, driver_version);
4449
4450        mgsl_enum_isa_devices();
4451        if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4452                printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4453        else
4454                pci_registered = true;
4455
4456        if ((rc = mgsl_init_tty()) < 0)
4457                goto error;
4458
4459        return 0;
4460
4461error:
4462        synclink_cleanup();
4463        return rc;
4464}
4465
4466static void __exit synclink_exit(void)
4467{
4468        synclink_cleanup();
4469}
4470
4471module_init(synclink_init);
4472module_exit(synclink_exit);
4473
4474/*
4475 * usc_RTCmd()
4476 *
4477 * Issue a USC Receive/Transmit command to the
4478 * Channel Command/Address Register (CCAR).
4479 *
4480 * Notes:
4481 *
4482 *    The command is encoded in the most significant 5 bits <15..11>
4483 *    of the CCAR value. Bits <10..7> of the CCAR must be preserved
4484 *    and Bits <6..0> must be written as zeros.
4485 *
4486 * Arguments:
4487 *
4488 *    info   pointer to device information structure
4489 *    Cmd    command mask (use symbolic macros)
4490 *
4491 * Return Value:
4492 *
4493 *    None
4494 */
4495static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4496{
4497        /* output command to CCAR in bits <15..11> */
4498        /* preserve bits <10..7>, bits <6..0> must be zero */
4499
4500        outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4501
4502        /* Read to flush write to CCAR */
4503        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4504                inw( info->io_base + CCAR );
4505
4506}       /* end of usc_RTCmd() */
4507
4508/*
4509 * usc_DmaCmd()
4510 *
4511 *    Issue a DMA command to the DMA Command/Address Register (DCAR).
4512 *
4513 * Arguments:
4514 *
4515 *    info   pointer to device information structure
4516 *    Cmd    DMA command mask (usc_DmaCmd_XX Macros)
4517 *
4518 * Return Value:
4519 *
4520 *       None
4521 */
4522static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4523{
4524        /* write command mask to DCAR */
4525        outw( Cmd + info->mbre_bit, info->io_base );
4526
4527        /* Read to flush write to DCAR */
4528        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4529                inw( info->io_base );
4530
4531}       /* end of usc_DmaCmd() */
4532
4533/*
4534 * usc_OutDmaReg()
4535 *
4536 *    Write a 16-bit value to a USC DMA register
4537 *
4538 * Arguments:
4539 *
4540 *    info      pointer to device info structure
4541 *    RegAddr   register address (number) for write
4542 *    RegValue  16-bit value to write to register
4543 *
4544 * Return Value:
4545 *
4546 *    None
4547 *
4548 */
4549static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4550{
4551        /* Note: The DCAR is located at the adapter base address */
4552        /* Note: must preserve state of BIT8 in DCAR */
4553
4554        outw( RegAddr + info->mbre_bit, info->io_base );
4555        outw( RegValue, info->io_base );
4556
4557        /* Read to flush write to DCAR */
4558        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4559                inw( info->io_base );
4560
4561}       /* end of usc_OutDmaReg() */
4562 
4563/*
4564 * usc_InDmaReg()
4565 *
4566 *    Read a 16-bit value from a DMA register
4567 *
4568 * Arguments:
4569 *
4570 *    info     pointer to device info structure
4571 *    RegAddr  register address (number) to read from
4572 *
4573 * Return Value:
4574 *
4575 *    The 16-bit value read from register
4576 *
4577 */
4578static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4579{
4580        /* Note: The DCAR is located at the adapter base address */
4581        /* Note: must preserve state of BIT8 in DCAR */
4582
4583        outw( RegAddr + info->mbre_bit, info->io_base );
4584        return inw( info->io_base );
4585
4586}       /* end of usc_InDmaReg() */
4587
4588/*
4589 *
4590 * usc_OutReg()
4591 *
4592 *    Write a 16-bit value to a USC serial channel register 
4593 *
4594 * Arguments:
4595 *
4596 *    info      pointer to device info structure
4597 *    RegAddr   register address (number) to write to
4598 *    RegValue  16-bit value to write to register
4599 *
4600 * Return Value:
4601 *
4602 *    None
4603 *
4604 */
4605static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4606{
4607        outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4608        outw( RegValue, info->io_base + CCAR );
4609
4610        /* Read to flush write to CCAR */
4611        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4612                inw( info->io_base + CCAR );
4613
4614}       /* end of usc_OutReg() */
4615
4616/*
4617 * usc_InReg()
4618 *
4619 *    Reads a 16-bit value from a USC serial channel register
4620 *
4621 * Arguments:
4622 *
4623 *    info       pointer to device extension
4624 *    RegAddr    register address (number) to read from
4625 *
4626 * Return Value:
4627 *
4628 *    16-bit value read from register
4629 */
4630static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4631{
4632        outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4633        return inw( info->io_base + CCAR );
4634
4635}       /* end of usc_InReg() */
4636
4637/* usc_set_sdlc_mode()
4638 *
4639 *    Set up the adapter for SDLC DMA communications.
4640 *
4641 * Arguments:           info    pointer to device instance data
4642 * Return Value:        NONE
4643 */
4644static void usc_set_sdlc_mode( struct mgsl_struct *info )
4645{
4646        u16 RegValue;
4647        bool PreSL1660;
4648        
4649        /*
4650         * determine if the IUSC on the adapter is pre-SL1660. If
4651         * not, take advantage of the UnderWait feature of more
4652         * modern chips. If an underrun occurs and this bit is set,
4653         * the transmitter will idle the programmed idle pattern
4654         * until the driver has time to service the underrun. Otherwise,
4655         * the dma controller may get the cycles previously requested
4656         * and begin transmitting queued tx data.
4657         */
4658        usc_OutReg(info,TMCR,0x1f);
4659        RegValue=usc_InReg(info,TMDR);
4660        PreSL1660 = (RegValue == IUSC_PRE_SL1660);
4661
4662        if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4663        {
4664           /*
4665           ** Channel Mode Register (CMR)
4666           **
4667           ** <15..14>    10    Tx Sub Modes, Send Flag on Underrun
4668           ** <13>        0     0 = Transmit Disabled (initially)
4669           ** <12>        0     1 = Consecutive Idles share common 0
4670           ** <11..8>     1110  Transmitter Mode = HDLC/SDLC Loop
4671           ** <7..4>      0000  Rx Sub Modes, addr/ctrl field handling
4672           ** <3..0>      0110  Receiver Mode = HDLC/SDLC
4673           **
4674           ** 1000 1110 0000 0110 = 0x8e06
4675           */
4676           RegValue = 0x8e06;
4677 
4678           /*--------------------------------------------------
4679            * ignore user options for UnderRun Actions and
4680            * preambles
4681            *--------------------------------------------------*/
4682        }
4683        else
4684        {       
4685                /* Channel mode Register (CMR)
4686                 *
4687                 * <15..14>  00    Tx Sub modes, Underrun Action
4688                 * <13>      0     1 = Send Preamble before opening flag
4689                 * <12>      0     1 = Consecutive Idles share common 0
4690                 * <11..8>   0110  Transmitter mode = HDLC/SDLC
4691                 * <7..4>    0000  Rx Sub modes, addr/ctrl field handling
4692                 * <3..0>    0110  Receiver mode = HDLC/SDLC
4693                 *
4694                 * 0000 0110 0000 0110 = 0x0606
4695                 */
4696                if (info->params.mode == MGSL_MODE_RAW) {
4697                        RegValue = 0x0001;              /* Set Receive mode = external sync */
4698
4699                        usc_OutReg( info, IOCR,         /* Set IOCR DCD is RxSync Detect Input */
4700                                (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4701
4702                        /*
4703                         * TxSubMode:
4704                         *      CMR <15>                0       Don't send CRC on Tx Underrun
4705                         *      CMR <14>                x       undefined
4706                         *      CMR <13>                0       Send preamble before openning sync
4707                         *      CMR <12>                0       Send 8-bit syncs, 1=send Syncs per TxLength
4708                         *
4709                         * TxMode:
4710                         *      CMR <11-8)      0100    MonoSync
4711                         *
4712                         *      0x00 0100 xxxx xxxx  04xx
4713                         */
4714                        RegValue |= 0x0400;
4715                }
4716                else {
4717
4718                RegValue = 0x0606;
4719
4720                if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4721                        RegValue |= BIT14;
4722                else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4723                        RegValue |= BIT15;
4724                else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4725                        RegValue |= BIT15 + BIT14;
4726                }
4727
4728                if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4729                        RegValue |= BIT13;
4730        }
4731
4732        if ( info->params.mode == MGSL_MODE_HDLC &&
4733                (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4734                RegValue |= BIT12;
4735
4736        if ( info->params.addr_filter != 0xff )
4737        {
4738                /* set up receive address filtering */
4739                usc_OutReg( info, RSR, info->params.addr_filter );
4740                RegValue |= BIT4;
4741        }
4742
4743        usc_OutReg( info, CMR, RegValue );
4744        info->cmr_value = RegValue;
4745
4746        /* Receiver mode Register (RMR)
4747         *
4748         * <15..13>  000    encoding
4749         * <12..11>  00     FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4750         * <10>      1      1 = Set CRC to all 1s (use for SDLC/HDLC)
4751         * <9>       0      1 = Include Receive chars in CRC
4752         * <8>       1      1 = Use Abort/PE bit as abort indicator
4753         * <7..6>    00     Even parity
4754         * <5>       0      parity disabled
4755         * <4..2>    000    Receive Char Length = 8 bits
4756         * <1..0>    00     Disable Receiver
4757         *
4758         * 0000 0101 0000 0000 = 0x0500
4759         */
4760
4761        RegValue = 0x0500;
4762
4763        switch ( info->params.encoding ) {
4764        case HDLC_ENCODING_NRZB:               RegValue |= BIT13; break;
4765        case HDLC_ENCODING_NRZI_MARK:          RegValue |= BIT14; break;
4766        case HDLC_ENCODING_NRZI_SPACE:         RegValue |= BIT14 + BIT13; break;
4767        case HDLC_ENCODING_BIPHASE_MARK:       RegValue |= BIT15; break;
4768        case HDLC_ENCODING_BIPHASE_SPACE:      RegValue |= BIT15 + BIT13; break;
4769        case HDLC_ENCODING_BIPHASE_LEVEL:      RegValue |= BIT15 + BIT14; break;
4770        case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4771        }
4772
4773        if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4774                RegValue |= BIT9;
4775        else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4776                RegValue |= ( BIT12 | BIT10 | BIT9 );
4777
4778        usc_OutReg( info, RMR, RegValue );
4779
4780        /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4781        /* When an opening flag of an SDLC frame is recognized the */
4782        /* Receive Character count (RCC) is loaded with the value in */
4783        /* RCLR. The RCC is decremented for each received byte.  The */
4784        /* value of RCC is stored after the closing flag of the frame */
4785        /* allowing the frame size to be computed. */
4786
4787        usc_OutReg( info, RCLR, RCLRVALUE );
4788
4789        usc_RCmd( info, RCmd_SelectRicrdma_level );
4790
4791        /* Receive Interrupt Control Register (RICR)
4792         *
4793         * <15..8>      ?       RxFIFO DMA Request Level
4794         * <7>          0       Exited Hunt IA (Interrupt Arm)
4795         * <6>          0       Idle Received IA
4796         * <5>          0       Break/Abort IA
4797         * <4>          0       Rx Bound IA
4798         * <3>          1       Queued status reflects oldest 2 bytes in FIFO
4799         * <2>          0       Abort/PE IA
4800         * <1>          1       Rx Overrun IA
4801         * <0>          0       Select TC0 value for readback
4802         *
4803         *      0000 0000 0000 1000 = 0x000a
4804         */
4805
4806        /* Carry over the Exit Hunt and Idle Received bits */
4807        /* in case they have been armed by usc_ArmEvents.   */
4808
4809        RegValue = usc_InReg( info, RICR ) & 0xc0;
4810
4811        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4812                usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4813        else
4814                usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4815
4816        /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4817
4818        usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4819        usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4820
4821        /* Transmit mode Register (TMR)
4822         *      
4823         * <15..13>     000     encoding
4824         * <12..11>     00      FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4825         * <10>         1       1 = Start CRC as all 1s (use for SDLC/HDLC)
4826         * <9>          0       1 = Tx CRC Enabled
4827         * <8>          0       1 = Append CRC to end of transmit frame
4828         * <7..6>       00      Transmit parity Even
4829         * <5>          0       Transmit parity Disabled
4830         * <4..2>       000     Tx Char Length = 8 bits
4831         * <1..0>       00      Disable Transmitter
4832         *
4833         *      0000 0100 0000 0000 = 0x0400
4834         */
4835
4836        RegValue = 0x0400;
4837
4838        switch ( info->params.encoding ) {
4839        case HDLC_ENCODING_NRZB:               RegValue |= BIT13; break;
4840        case HDLC_ENCODING_NRZI_MARK:          RegValue |= BIT14; break;
4841        case HDLC_ENCODING_NRZI_SPACE:         RegValue |= BIT14 + BIT13; break;
4842        case HDLC_ENCODING_BIPHASE_MARK:       RegValue |= BIT15; break;
4843        case HDLC_ENCODING_BIPHASE_SPACE:      RegValue |= BIT15 + BIT13; break;
4844        case HDLC_ENCODING_BIPHASE_LEVEL:      RegValue |= BIT15 + BIT14; break;
4845        case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4846        }
4847
4848        if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4849                RegValue |= BIT9 + BIT8;
4850        else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4851                RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4852
4853        usc_OutReg( info, TMR, RegValue );
4854
4855        usc_set_txidle( info );
4856
4857
4858        usc_TCmd( info, TCmd_SelectTicrdma_level );
4859
4860        /* Transmit Interrupt Control Register (TICR)
4861         *
4862         * <15..8>      ?       Transmit FIFO DMA Level
4863         * <7>          0       Present IA (Interrupt Arm)
4864         * <6>          0       Idle Sent IA
4865         * <5>          1       Abort Sent IA
4866         * <4>          1       EOF/EOM Sent IA
4867         * <3>          0       CRC Sent IA
4868         * <2>          1       1 = Wait for SW Trigger to Start Frame
4869         * <1>          1       Tx Underrun IA
4870         * <0>          0       TC0 constant on read back
4871         *
4872         *      0000 0000 0011 0110 = 0x0036
4873         */
4874
4875        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4876                usc_OutReg( info, TICR, 0x0736 );
4877        else                                                            
4878                usc_OutReg( info, TICR, 0x1436 );
4879
4880        usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4881        usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4882
4883        /*
4884        ** Transmit Command/Status Register (TCSR)
4885        **
4886        ** <15..12>     0000    TCmd
4887        ** <11>         0/1     UnderWait
4888        ** <10..08>     000     TxIdle
4889        ** <7>          x       PreSent
4890        ** <6>          x       IdleSent
4891        ** <5>          x       AbortSent
4892        ** <4>          x       EOF/EOM Sent
4893        ** <3>          x       CRC Sent
4894        ** <2>          x       All Sent
4895        ** <1>          x       TxUnder
4896        ** <0>          x       TxEmpty
4897        ** 
4898        ** 0000 0000 0000 0000 = 0x0000
4899        */
4900        info->tcsr_value = 0;
4901
4902        if ( !PreSL1660 )
4903                info->tcsr_value |= TCSR_UNDERWAIT;
4904                
4905        usc_OutReg( info, TCSR, info->tcsr_value );
4906
4907        /* Clock mode Control Register (CMCR)
4908         *
4909         * <15..14>     00      counter 1 Source = Disabled
4910         * <13..12>     00      counter 0 Source = Disabled
4911         * <11..10>     11      BRG1 Input is TxC Pin
4912         * <9..8>       11      BRG0 Input is TxC Pin
4913         * <7..6>       01      DPLL Input is BRG1 Output
4914         * <5..3>       XXX     TxCLK comes from Port 0
4915         * <2..0>       XXX     RxCLK comes from Port 1
4916         *
4917         *      0000 1111 0111 0111 = 0x0f77
4918         */
4919
4920        RegValue = 0x0f40;
4921
4922        if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4923                RegValue |= 0x0003;     /* RxCLK from DPLL */
4924        else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4925                RegValue |= 0x0004;     /* RxCLK from BRG0 */
4926        else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4927                RegValue |= 0x0006;     /* RxCLK from TXC Input */
4928        else
4929                RegValue |= 0x0007;     /* RxCLK from Port1 */
4930
4931        if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4932                RegValue |= 0x0018;     /* TxCLK from DPLL */
4933        else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4934                RegValue |= 0x0020;     /* TxCLK from BRG0 */
4935        else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4936                RegValue |= 0x0038;     /* RxCLK from TXC Input */
4937        else
4938                RegValue |= 0x0030;     /* TxCLK from Port0 */
4939
4940        usc_OutReg( info, CMCR, RegValue );
4941
4942
4943        /* Hardware Configuration Register (HCR)
4944         *
4945         * <15..14>     00      CTR0 Divisor:00=32,01=16,10=8,11=4
4946         * <13>         0       CTR1DSel:0=CTR0Div determines CTR0Div
4947         * <12>         0       CVOK:0=report code violation in biphase
4948         * <11..10>     00      DPLL Divisor:00=32,01=16,10=8,11=4
4949         * <9..8>       XX      DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4950         * <7..6>       00      reserved
4951         * <5>          0       BRG1 mode:0=continuous,1=single cycle
4952         * <4>          X       BRG1 Enable
4953         * <3..2>       00      reserved
4954         * <1>          0       BRG0 mode:0=continuous,1=single cycle
4955         * <0>          0       BRG0 Enable
4956         */
4957
4958        RegValue = 0x0000;
4959
4960        if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
4961                u32 XtalSpeed;
4962                u32 DpllDivisor;
4963                u16 Tc;
4964
4965                /*  DPLL is enabled. Use BRG1 to provide continuous reference clock  */
4966                /*  for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4967
4968                if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4969                        XtalSpeed = 11059200;
4970                else
4971                        XtalSpeed = 14745600;
4972
4973                if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4974                        DpllDivisor = 16;
4975                        RegValue |= BIT10;
4976                }
4977                else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4978                        DpllDivisor = 8;
4979                        RegValue |= BIT11;
4980                }
4981                else
4982                        DpllDivisor = 32;
4983
4984                /*  Tc = (Xtal/Speed) - 1 */
4985                /*  If twice the remainder of (Xtal/Speed) is greater than Speed */
4986                /*  then rounding up gives a more precise time constant. Instead */
4987                /*  of rounding up and then subtracting 1 we just don't subtract */
4988                /*  the one in this case. */
4989
4990                /*--------------------------------------------------
4991                 * ejz: for DPLL mode, application should use the
4992                 * same clock speed as the partner system, even 
4993                 * though clocking is derived from the input RxData.
4994                 * In case the user uses a 0 for the clock speed,
4995                 * default to 0xffffffff and don't try to divide by
4996                 * zero
4997                 *--------------------------------------------------*/
4998                if ( info->params.clock_speed )
4999                {
5000                        Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
5001                        if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
5002                               / info->params.clock_speed) )
5003                                Tc--;
5004                }
5005                else
5006                        Tc = -1;
5007                                  
5008
5009                /* Write 16-bit Time Constant for BRG1 */
5010                usc_OutReg( info, TC1R, Tc );
5011
5012                RegValue |= BIT4;               /* enable BRG1 */
5013
5014                switch ( info->params.encoding ) {
5015                case HDLC_ENCODING_NRZ:
5016                case HDLC_ENCODING_NRZB:
5017                case HDLC_ENCODING_NRZI_MARK:
5018                case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5019                case HDLC_ENCODING_BIPHASE_MARK:
5020                case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5021                case HDLC_ENCODING_BIPHASE_LEVEL:
5022                case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5023                }
5024        }
5025
5026        usc_OutReg( info, HCR, RegValue );
5027
5028
5029        /* Channel Control/status Register (CCSR)
5030         *
5031         * <15>         X       RCC FIFO Overflow status (RO)
5032         * <14>         X       RCC FIFO Not Empty status (RO)
5033         * <13>         0       1 = Clear RCC FIFO (WO)
5034         * <12>         X       DPLL Sync (RW)
5035         * <11>         X       DPLL 2 Missed Clocks status (RO)
5036         * <10>         X       DPLL 1 Missed Clock status (RO)
5037         * <9..8>       00      DPLL Resync on rising and falling edges (RW)
5038         * <7>          X       SDLC Loop On status (RO)
5039         * <6>          X       SDLC Loop Send status (RO)
5040         * <5>          1       Bypass counters for TxClk and RxClk (RW)
5041         * <4..2>       000     Last Char of SDLC frame has 8 bits (RW)
5042         * <1..0>       00      reserved
5043         *
5044         *      0000 0000 0010 0000 = 0x0020
5045         */
5046
5047        usc_OutReg( info, CCSR, 0x1020 );
5048
5049
5050        if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5051                usc_OutReg( info, SICR,
5052                            (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5053        }
5054        
5055
5056        /* enable Master Interrupt Enable bit (MIE) */
5057        usc_EnableMasterIrqBit( info );
5058
5059        usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5060                                TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5061
5062        /* arm RCC underflow interrupt */
5063        usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5064        usc_EnableInterrupts(info, MISC);
5065
5066        info->mbre_bit = 0;
5067        outw( 0, info->io_base );                       /* clear Master Bus Enable (DCAR) */
5068        usc_DmaCmd( info, DmaCmd_ResetAllChannels );    /* disable both DMA channels */
5069        info->mbre_bit = BIT8;
5070        outw( BIT8, info->io_base );                    /* set Master Bus Enable (DCAR) */
5071
5072        if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5073                /* Enable DMAEN (Port 7, Bit 14) */
5074                /* This connects the DMA request signal to the ISA bus */
5075                usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5076        }
5077
5078        /* DMA Control Register (DCR)
5079         *
5080         * <15..14>     10      Priority mode = Alternating Tx/Rx
5081         *              01      Rx has priority
5082         *              00      Tx has priority
5083         *
5084         * <13>         1       Enable Priority Preempt per DCR<15..14>
5085         *                      (WARNING DCR<11..10> must be 00 when this is 1)
5086         *              0       Choose activate channel per DCR<11..10>
5087         *
5088         * <12>         0       Little Endian for Array/List
5089         * <11..10>     00      Both Channels can use each bus grant
5090         * <9..6>       0000    reserved
5091         * <5>          0       7 CLK - Minimum Bus Re-request Interval
5092         * <4>          0       1 = drive D/C and S/D pins
5093         * <3>          1       1 = Add one wait state to all DMA cycles.
5094         * <2>          0       1 = Strobe /UAS on every transfer.
5095         * <1..0>       11      Addr incrementing only affects LS24 bits
5096         *
5097         *      0110 0000 0000 1011 = 0x600b
5098         */
5099
5100        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5101                /* PCI adapter does not need DMA wait state */
5102                usc_OutDmaReg( info, DCR, 0xa00b );
5103        }
5104        else
5105                usc_OutDmaReg( info, DCR, 0x800b );
5106
5107
5108        /* Receive DMA mode Register (RDMR)
5109         *
5110         * <15..14>     11      DMA mode = Linked List Buffer mode
5111         * <13>         1       RSBinA/L = store Rx status Block in Arrary/List entry
5112         * <12>         1       Clear count of List Entry after fetching
5113         * <11..10>     00      Address mode = Increment
5114         * <9>          1       Terminate Buffer on RxBound
5115         * <8>          0       Bus Width = 16bits
5116         * <7..0>       ?       status Bits (write as 0s)
5117         *
5118         * 1111 0010 0000 0000 = 0xf200
5119         */
5120
5121        usc_OutDmaReg( info, RDMR, 0xf200 );
5122
5123
5124        /* Transmit DMA mode Register (TDMR)
5125         *
5126         * <15..14>     11      DMA mode = Linked List Buffer mode
5127         * <13>         1       TCBinA/L = fetch Tx Control Block from List entry
5128         * <12>         1       Clear count of List Entry after fetching
5129         * <11..10>     00      Address mode = Increment
5130         * <9>          1       Terminate Buffer on end of frame
5131         * <8>          0       Bus Width = 16bits
5132         * <7..0>       ?       status Bits (Read Only so write as 0)
5133         *
5134         *      1111 0010 0000 0000 = 0xf200
5135         */
5136
5137        usc_OutDmaReg( info, TDMR, 0xf200 );
5138
5139
5140        /* DMA Interrupt Control Register (DICR)
5141         *
5142         * <15>         1       DMA Interrupt Enable
5143         * <14>         0       1 = Disable IEO from USC
5144         * <13>         0       1 = Don't provide vector during IntAck
5145         * <12>         1       1 = Include status in Vector
5146         * <10..2>      0       reserved, Must be 0s
5147         * <1>          0       1 = Rx DMA Interrupt Enabled
5148         * <0>          0       1 = Tx DMA Interrupt Enabled
5149         *
5150         *      1001 0000 0000 0000 = 0x9000
5151         */
5152
5153        usc_OutDmaReg( info, DICR, 0x9000 );
5154
5155        usc_InDmaReg( info, RDMR );             /* clear pending receive DMA IRQ bits */
5156        usc_InDmaReg( info, TDMR );             /* clear pending transmit DMA IRQ bits */
5157        usc_OutDmaReg( info, CDIR, 0x0303 );    /* clear IUS and Pending for Tx and Rx */
5158
5159        /* Channel Control Register (CCR)
5160         *
5161         * <15..14>     10      Use 32-bit Tx Control Blocks (TCBs)
5162         * <13>         0       Trigger Tx on SW Command Disabled
5163         * <12>         0       Flag Preamble Disabled
5164         * <11..10>     00      Preamble Length
5165         * <9..8>       00      Preamble Pattern
5166         * <7..6>       10      Use 32-bit Rx status Blocks (RSBs)
5167         * <5>          0       Trigger Rx on SW Command Disabled
5168         * <4..0>       0       reserved
5169         *
5170         *      1000 0000 1000 0000 = 0x8080
5171         */
5172
5173        RegValue = 0x8080;
5174
5175        switch ( info->params.preamble_length ) {
5176        case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5177        case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5178        case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5179        }
5180
5181        switch ( info->params.preamble ) {
5182        case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5183        case HDLC_PREAMBLE_PATTERN_ONES:  RegValue |= BIT8; break;
5184        case HDLC_PREAMBLE_PATTERN_10:    RegValue |= BIT9; break;
5185        case HDLC_PREAMBLE_PATTERN_01:    RegValue |= BIT9 + BIT8; break;
5186        }
5187
5188        usc_OutReg( info, CCR, RegValue );
5189
5190
5191        /*
5192         * Burst/Dwell Control Register
5193         *
5194         * <15..8>      0x20    Maximum number of transfers per bus grant
5195         * <7..0>       0x00    Maximum number of clock cycles per bus grant
5196         */
5197
5198        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5199                /* don't limit bus occupancy on PCI adapter */
5200                usc_OutDmaReg( info, BDCR, 0x0000 );
5201        }
5202        else
5203                usc_OutDmaReg( info, BDCR, 0x2000 );
5204
5205        usc_stop_transmitter(info);
5206        usc_stop_receiver(info);
5207        
5208}       /* end of usc_set_sdlc_mode() */
5209
5210/* usc_enable_loopback()
5211 *
5212 * Set the 16C32 for internal loopback mode.
5213 * The TxCLK and RxCLK signals are generated from the BRG0 and
5214 * the TxD is looped back to the RxD internally.
5215 *
5216 * Arguments:           info    pointer to device instance data
5217 *                      enable  1 = enable loopback, 0 = disable
5218 * Return Value:        None