linux/drivers/spi/spi-pxa2xx.c
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   1/*
   2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   3 * Copyright (C) 2013, Intel Corporation
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; either version 2 of the License, or
   8 * (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18 */
  19
  20#include <linux/init.h>
  21#include <linux/module.h>
  22#include <linux/device.h>
  23#include <linux/ioport.h>
  24#include <linux/errno.h>
  25#include <linux/err.h>
  26#include <linux/interrupt.h>
  27#include <linux/platform_device.h>
  28#include <linux/spi/pxa2xx_spi.h>
  29#include <linux/spi/spi.h>
  30#include <linux/workqueue.h>
  31#include <linux/delay.h>
  32#include <linux/gpio.h>
  33#include <linux/slab.h>
  34#include <linux/clk.h>
  35#include <linux/pm_runtime.h>
  36#include <linux/acpi.h>
  37
  38#include <asm/io.h>
  39#include <asm/irq.h>
  40#include <asm/delay.h>
  41
  42#include "spi-pxa2xx.h"
  43
  44MODULE_AUTHOR("Stephen Street");
  45MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
  46MODULE_LICENSE("GPL");
  47MODULE_ALIAS("platform:pxa2xx-spi");
  48
  49#define MAX_BUSES 3
  50
  51#define TIMOUT_DFLT             1000
  52
  53/*
  54 * for testing SSCR1 changes that require SSP restart, basically
  55 * everything except the service and interrupt enables, the pxa270 developer
  56 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
  57 * list, but the PXA255 dev man says all bits without really meaning the
  58 * service and interrupt enables
  59 */
  60#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  61                                | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  62                                | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  63                                | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  64                                | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
  65                                | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  66
  67#define LPSS_RX_THRESH_DFLT     64
  68#define LPSS_TX_LOTHRESH_DFLT   160
  69#define LPSS_TX_HITHRESH_DFLT   224
  70
  71/* Offset from drv_data->lpss_base */
  72#define SSP_REG                 0x0c
  73#define SPI_CS_CONTROL          0x18
  74#define SPI_CS_CONTROL_SW_MODE  BIT(0)
  75#define SPI_CS_CONTROL_CS_HIGH  BIT(1)
  76
  77static bool is_lpss_ssp(const struct driver_data *drv_data)
  78{
  79        return drv_data->ssp_type == LPSS_SSP;
  80}
  81
  82/*
  83 * Read and write LPSS SSP private registers. Caller must first check that
  84 * is_lpss_ssp() returns true before these can be called.
  85 */
  86static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
  87{
  88        WARN_ON(!drv_data->lpss_base);
  89        return readl(drv_data->lpss_base + offset);
  90}
  91
  92static void __lpss_ssp_write_priv(struct driver_data *drv_data,
  93                                  unsigned offset, u32 value)
  94{
  95        WARN_ON(!drv_data->lpss_base);
  96        writel(value, drv_data->lpss_base + offset);
  97}
  98
  99/*
 100 * lpss_ssp_setup - perform LPSS SSP specific setup
 101 * @drv_data: pointer to the driver private data
 102 *
 103 * Perform LPSS SSP specific setup. This function must be called first if
 104 * one is going to use LPSS SSP private registers.
 105 */
 106static void lpss_ssp_setup(struct driver_data *drv_data)
 107{
 108        unsigned offset = 0x400;
 109        u32 value, orig;
 110
 111        if (!is_lpss_ssp(drv_data))
 112                return;
 113
 114        /*
 115         * Perform auto-detection of the LPSS SSP private registers. They
 116         * can be either at 1k or 2k offset from the base address.
 117         */
 118        orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
 119
 120        value = orig | SPI_CS_CONTROL_SW_MODE;
 121        writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
 122        value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
 123        if (value != (orig | SPI_CS_CONTROL_SW_MODE)) {
 124                offset = 0x800;
 125                goto detection_done;
 126        }
 127
 128        value &= ~SPI_CS_CONTROL_SW_MODE;
 129        writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
 130        value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
 131        if (value != orig) {
 132                offset = 0x800;
 133                goto detection_done;
 134        }
 135
 136detection_done:
 137        /* Now set the LPSS base */
 138        drv_data->lpss_base = drv_data->ioaddr + offset;
 139
 140        /* Enable software chip select control */
 141        value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
 142        __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
 143
 144        /* Enable multiblock DMA transfers */
 145        if (drv_data->master_info->enable_dma)
 146                __lpss_ssp_write_priv(drv_data, SSP_REG, 1);
 147}
 148
 149static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
 150{
 151        u32 value;
 152
 153        if (!is_lpss_ssp(drv_data))
 154                return;
 155
 156        value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL);
 157        if (enable)
 158                value &= ~SPI_CS_CONTROL_CS_HIGH;
 159        else
 160                value |= SPI_CS_CONTROL_CS_HIGH;
 161        __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
 162}
 163
 164static void cs_assert(struct driver_data *drv_data)
 165{
 166        struct chip_data *chip = drv_data->cur_chip;
 167
 168        if (drv_data->ssp_type == CE4100_SSP) {
 169                write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
 170                return;
 171        }
 172
 173        if (chip->cs_control) {
 174                chip->cs_control(PXA2XX_CS_ASSERT);
 175                return;
 176        }
 177
 178        if (gpio_is_valid(chip->gpio_cs)) {
 179                gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
 180                return;
 181        }
 182
 183        lpss_ssp_cs_control(drv_data, true);
 184}
 185
 186static void cs_deassert(struct driver_data *drv_data)
 187{
 188        struct chip_data *chip = drv_data->cur_chip;
 189
 190        if (drv_data->ssp_type == CE4100_SSP)
 191                return;
 192
 193        if (chip->cs_control) {
 194                chip->cs_control(PXA2XX_CS_DEASSERT);
 195                return;
 196        }
 197
 198        if (gpio_is_valid(chip->gpio_cs)) {
 199                gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
 200                return;
 201        }
 202
 203        lpss_ssp_cs_control(drv_data, false);
 204}
 205
 206int pxa2xx_spi_flush(struct driver_data *drv_data)
 207{
 208        unsigned long limit = loops_per_jiffy << 1;
 209
 210        void __iomem *reg = drv_data->ioaddr;
 211
 212        do {
 213                while (read_SSSR(reg) & SSSR_RNE) {
 214                        read_SSDR(reg);
 215                }
 216        } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
 217        write_SSSR_CS(drv_data, SSSR_ROR);
 218
 219        return limit;
 220}
 221
 222static int null_writer(struct driver_data *drv_data)
 223{
 224        void __iomem *reg = drv_data->ioaddr;
 225        u8 n_bytes = drv_data->n_bytes;
 226
 227        if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
 228                || (drv_data->tx == drv_data->tx_end))
 229                return 0;
 230
 231        write_SSDR(0, reg);
 232        drv_data->tx += n_bytes;
 233
 234        return 1;
 235}
 236
 237static int null_reader(struct driver_data *drv_data)
 238{
 239        void __iomem *reg = drv_data->ioaddr;
 240        u8 n_bytes = drv_data->n_bytes;
 241
 242        while ((read_SSSR(reg) & SSSR_RNE)
 243                && (drv_data->rx < drv_data->rx_end)) {
 244                read_SSDR(reg);
 245                drv_data->rx += n_bytes;
 246        }
 247
 248        return drv_data->rx == drv_data->rx_end;
 249}
 250
 251static int u8_writer(struct driver_data *drv_data)
 252{
 253        void __iomem *reg = drv_data->ioaddr;
 254
 255        if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
 256                || (drv_data->tx == drv_data->tx_end))
 257                return 0;
 258
 259        write_SSDR(*(u8 *)(drv_data->tx), reg);
 260        ++drv_data->tx;
 261
 262        return 1;
 263}
 264
 265static int u8_reader(struct driver_data *drv_data)
 266{
 267        void __iomem *reg = drv_data->ioaddr;
 268
 269        while ((read_SSSR(reg) & SSSR_RNE)
 270                && (drv_data->rx < drv_data->rx_end)) {
 271                *(u8 *)(drv_data->rx) = read_SSDR(reg);
 272                ++drv_data->rx;
 273        }
 274
 275        return drv_data->rx == drv_data->rx_end;
 276}
 277
 278static int u16_writer(struct driver_data *drv_data)
 279{
 280        void __iomem *reg = drv_data->ioaddr;
 281
 282        if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
 283                || (drv_data->tx == drv_data->tx_end))
 284                return 0;
 285
 286        write_SSDR(*(u16 *)(drv_data->tx), reg);
 287        drv_data->tx += 2;
 288
 289        return 1;
 290}
 291
 292static int u16_reader(struct driver_data *drv_data)
 293{
 294        void __iomem *reg = drv_data->ioaddr;
 295
 296        while ((read_SSSR(reg) & SSSR_RNE)
 297                && (drv_data->rx < drv_data->rx_end)) {
 298                *(u16 *)(drv_data->rx) = read_SSDR(reg);
 299                drv_data->rx += 2;
 300        }
 301
 302        return drv_data->rx == drv_data->rx_end;
 303}
 304
 305static int u32_writer(struct driver_data *drv_data)
 306{
 307        void __iomem *reg = drv_data->ioaddr;
 308
 309        if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
 310                || (drv_data->tx == drv_data->tx_end))
 311                return 0;
 312
 313        write_SSDR(*(u32 *)(drv_data->tx), reg);
 314        drv_data->tx += 4;
 315
 316        return 1;
 317}
 318
 319static int u32_reader(struct driver_data *drv_data)
 320{
 321        void __iomem *reg = drv_data->ioaddr;
 322
 323        while ((read_SSSR(reg) & SSSR_RNE)
 324                && (drv_data->rx < drv_data->rx_end)) {
 325                *(u32 *)(drv_data->rx) = read_SSDR(reg);
 326                drv_data->rx += 4;
 327        }
 328
 329        return drv_data->rx == drv_data->rx_end;
 330}
 331
 332void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
 333{
 334        struct spi_message *msg = drv_data->cur_msg;
 335        struct spi_transfer *trans = drv_data->cur_transfer;
 336
 337        /* Move to next transfer */
 338        if (trans->transfer_list.next != &msg->transfers) {
 339                drv_data->cur_transfer =
 340                        list_entry(trans->transfer_list.next,
 341                                        struct spi_transfer,
 342                                        transfer_list);
 343                return RUNNING_STATE;
 344        } else
 345                return DONE_STATE;
 346}
 347
 348/* caller already set message->status; dma and pio irqs are blocked */
 349static void giveback(struct driver_data *drv_data)
 350{
 351        struct spi_transfer* last_transfer;
 352        struct spi_message *msg;
 353
 354        msg = drv_data->cur_msg;
 355        drv_data->cur_msg = NULL;
 356        drv_data->cur_transfer = NULL;
 357
 358        last_transfer = list_entry(msg->transfers.prev,
 359                                        struct spi_transfer,
 360                                        transfer_list);
 361
 362        /* Delay if requested before any change in chip select */
 363        if (last_transfer->delay_usecs)
 364                udelay(last_transfer->delay_usecs);
 365
 366        /* Drop chip select UNLESS cs_change is true or we are returning
 367         * a message with an error, or next message is for another chip
 368         */
 369        if (!last_transfer->cs_change)
 370                cs_deassert(drv_data);
 371        else {
 372                struct spi_message *next_msg;
 373
 374                /* Holding of cs was hinted, but we need to make sure
 375                 * the next message is for the same chip.  Don't waste
 376                 * time with the following tests unless this was hinted.
 377                 *
 378                 * We cannot postpone this until pump_messages, because
 379                 * after calling msg->complete (below) the driver that
 380                 * sent the current message could be unloaded, which
 381                 * could invalidate the cs_control() callback...
 382                 */
 383
 384                /* get a pointer to the next message, if any */
 385                next_msg = spi_get_next_queued_message(drv_data->master);
 386
 387                /* see if the next and current messages point
 388                 * to the same chip
 389                 */
 390                if (next_msg && next_msg->spi != msg->spi)
 391                        next_msg = NULL;
 392                if (!next_msg || msg->state == ERROR_STATE)
 393                        cs_deassert(drv_data);
 394        }
 395
 396        spi_finalize_current_message(drv_data->master);
 397        drv_data->cur_chip = NULL;
 398}
 399
 400static void reset_sccr1(struct driver_data *drv_data)
 401{
 402        void __iomem *reg = drv_data->ioaddr;
 403        struct chip_data *chip = drv_data->cur_chip;
 404        u32 sccr1_reg;
 405
 406        sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
 407        sccr1_reg &= ~SSCR1_RFT;
 408        sccr1_reg |= chip->threshold;
 409        write_SSCR1(sccr1_reg, reg);
 410}
 411
 412static void int_error_stop(struct driver_data *drv_data, const char* msg)
 413{
 414        void __iomem *reg = drv_data->ioaddr;
 415
 416        /* Stop and reset SSP */
 417        write_SSSR_CS(drv_data, drv_data->clear_sr);
 418        reset_sccr1(drv_data);
 419        if (!pxa25x_ssp_comp(drv_data))
 420                write_SSTO(0, reg);
 421        pxa2xx_spi_flush(drv_data);
 422        write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 423
 424        dev_err(&drv_data->pdev->dev, "%s\n", msg);
 425
 426        drv_data->cur_msg->state = ERROR_STATE;
 427        tasklet_schedule(&drv_data->pump_transfers);
 428}
 429
 430static void int_transfer_complete(struct driver_data *drv_data)
 431{
 432        void __iomem *reg = drv_data->ioaddr;
 433
 434        /* Stop SSP */
 435        write_SSSR_CS(drv_data, drv_data->clear_sr);
 436        reset_sccr1(drv_data);
 437        if (!pxa25x_ssp_comp(drv_data))
 438                write_SSTO(0, reg);
 439
 440        /* Update total byte transferred return count actual bytes read */
 441        drv_data->cur_msg->actual_length += drv_data->len -
 442                                (drv_data->rx_end - drv_data->rx);
 443
 444        /* Transfer delays and chip select release are
 445         * handled in pump_transfers or giveback
 446         */
 447
 448        /* Move to next transfer */
 449        drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
 450
 451        /* Schedule transfer tasklet */
 452        tasklet_schedule(&drv_data->pump_transfers);
 453}
 454
 455static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 456{
 457        void __iomem *reg = drv_data->ioaddr;
 458
 459        u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
 460                        drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
 461
 462        u32 irq_status = read_SSSR(reg) & irq_mask;
 463
 464        if (irq_status & SSSR_ROR) {
 465                int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
 466                return IRQ_HANDLED;
 467        }
 468
 469        if (irq_status & SSSR_TINT) {
 470                write_SSSR(SSSR_TINT, reg);
 471                if (drv_data->read(drv_data)) {
 472                        int_transfer_complete(drv_data);
 473                        return IRQ_HANDLED;
 474                }
 475        }
 476
 477        /* Drain rx fifo, Fill tx fifo and prevent overruns */
 478        do {
 479                if (drv_data->read(drv_data)) {
 480                        int_transfer_complete(drv_data);
 481                        return IRQ_HANDLED;
 482                }
 483        } while (drv_data->write(drv_data));
 484
 485        if (drv_data->read(drv_data)) {
 486                int_transfer_complete(drv_data);
 487                return IRQ_HANDLED;
 488        }
 489
 490        if (drv_data->tx == drv_data->tx_end) {
 491                u32 bytes_left;
 492                u32 sccr1_reg;
 493
 494                sccr1_reg = read_SSCR1(reg);
 495                sccr1_reg &= ~SSCR1_TIE;
 496
 497                /*
 498                 * PXA25x_SSP has no timeout, set up rx threshould for the
 499                 * remaining RX bytes.
 500                 */
 501                if (pxa25x_ssp_comp(drv_data)) {
 502
 503                        sccr1_reg &= ~SSCR1_RFT;
 504
 505                        bytes_left = drv_data->rx_end - drv_data->rx;
 506                        switch (drv_data->n_bytes) {
 507                        case 4:
 508                                bytes_left >>= 1;
 509                        case 2:
 510                                bytes_left >>= 1;
 511                        }
 512
 513                        if (bytes_left > RX_THRESH_DFLT)
 514                                bytes_left = RX_THRESH_DFLT;
 515
 516                        sccr1_reg |= SSCR1_RxTresh(bytes_left);
 517                }
 518                write_SSCR1(sccr1_reg, reg);
 519        }
 520
 521        /* We did something */
 522        return IRQ_HANDLED;
 523}
 524
 525static irqreturn_t ssp_int(int irq, void *dev_id)
 526{
 527        struct driver_data *drv_data = dev_id;
 528        void __iomem *reg = drv_data->ioaddr;
 529        u32 sccr1_reg;
 530        u32 mask = drv_data->mask_sr;
 531        u32 status;
 532
 533        /*
 534         * The IRQ might be shared with other peripherals so we must first
 535         * check that are we RPM suspended or not. If we are we assume that
 536         * the IRQ was not for us (we shouldn't be RPM suspended when the
 537         * interrupt is enabled).
 538         */
 539        if (pm_runtime_suspended(&drv_data->pdev->dev))
 540                return IRQ_NONE;
 541
 542        sccr1_reg = read_SSCR1(reg);
 543        status = read_SSSR(reg);
 544
 545        /* Ignore possible writes if we don't need to write */
 546        if (!(sccr1_reg & SSCR1_TIE))
 547                mask &= ~SSSR_TFS;
 548
 549        if (!(status & mask))
 550                return IRQ_NONE;
 551
 552        if (!drv_data->cur_msg) {
 553
 554                write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 555                write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 556                if (!pxa25x_ssp_comp(drv_data))
 557                        write_SSTO(0, reg);
 558                write_SSSR_CS(drv_data, drv_data->clear_sr);
 559
 560                dev_err(&drv_data->pdev->dev, "bad message state "
 561                        "in interrupt handler\n");
 562
 563                /* Never fail */
 564                return IRQ_HANDLED;
 565        }
 566
 567        return drv_data->transfer_handler(drv_data);
 568}
 569
 570static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
 571{
 572        unsigned long ssp_clk = drv_data->max_clk_rate;
 573        const struct ssp_device *ssp = drv_data->ssp;
 574
 575        rate = min_t(int, ssp_clk, rate);
 576
 577        if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
 578                return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
 579        else
 580                return ((ssp_clk / rate - 1) & 0xfff) << 8;
 581}
 582
 583static void pump_transfers(unsigned long data)
 584{
 585        struct driver_data *drv_data = (struct driver_data *)data;
 586        struct spi_message *message = NULL;
 587        struct spi_transfer *transfer = NULL;
 588        struct spi_transfer *previous = NULL;
 589        struct chip_data *chip = NULL;
 590        void __iomem *reg = drv_data->ioaddr;
 591        u32 clk_div = 0;
 592        u8 bits = 0;
 593        u32 speed = 0;
 594        u32 cr0;
 595        u32 cr1;
 596        u32 dma_thresh = drv_data->cur_chip->dma_threshold;
 597        u32 dma_burst = drv_data->cur_chip->dma_burst_size;
 598
 599        /* Get current state information */
 600        message = drv_data->cur_msg;
 601        transfer = drv_data->cur_transfer;
 602        chip = drv_data->cur_chip;
 603
 604        /* Handle for abort */
 605        if (message->state == ERROR_STATE) {
 606                message->status = -EIO;
 607                giveback(drv_data);
 608                return;
 609        }
 610
 611        /* Handle end of message */
 612        if (message->state == DONE_STATE) {
 613                message->status = 0;
 614                giveback(drv_data);
 615                return;
 616        }
 617
 618        /* Delay if requested at end of transfer before CS change */
 619        if (message->state == RUNNING_STATE) {
 620                previous = list_entry(transfer->transfer_list.prev,
 621                                        struct spi_transfer,
 622                                        transfer_list);
 623                if (previous->delay_usecs)
 624                        udelay(previous->delay_usecs);
 625
 626                /* Drop chip select only if cs_change is requested */
 627                if (previous->cs_change)
 628                        cs_deassert(drv_data);
 629        }
 630
 631        /* Check if we can DMA this transfer */
 632        if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
 633
 634                /* reject already-mapped transfers; PIO won't always work */
 635                if (message->is_dma_mapped
 636                                || transfer->rx_dma || transfer->tx_dma) {
 637                        dev_err(&drv_data->pdev->dev,
 638                                "pump_transfers: mapped transfer length "
 639                                "of %u is greater than %d\n",
 640                                transfer->len, MAX_DMA_LEN);
 641                        message->status = -EINVAL;
 642                        giveback(drv_data);
 643                        return;
 644                }
 645
 646                /* warn ... we force this to PIO mode */
 647                if (printk_ratelimit())
 648                        dev_warn(&message->spi->dev, "pump_transfers: "
 649                                "DMA disabled for transfer length %ld "
 650                                "greater than %d\n",
 651                                (long)drv_data->len, MAX_DMA_LEN);
 652        }
 653
 654        /* Setup the transfer state based on the type of transfer */
 655        if (pxa2xx_spi_flush(drv_data) == 0) {
 656                dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
 657                message->status = -EIO;
 658                giveback(drv_data);
 659                return;
 660        }
 661        drv_data->n_bytes = chip->n_bytes;
 662        drv_data->tx = (void *)transfer->tx_buf;
 663        drv_data->tx_end = drv_data->tx + transfer->len;
 664        drv_data->rx = transfer->rx_buf;
 665        drv_data->rx_end = drv_data->rx + transfer->len;
 666        drv_data->rx_dma = transfer->rx_dma;
 667        drv_data->tx_dma = transfer->tx_dma;
 668        drv_data->len = transfer->len;
 669        drv_data->write = drv_data->tx ? chip->write : null_writer;
 670        drv_data->read = drv_data->rx ? chip->read : null_reader;
 671
 672        /* Change speed and bit per word on a per transfer */
 673        cr0 = chip->cr0;
 674        if (transfer->speed_hz || transfer->bits_per_word) {
 675
 676                bits = chip->bits_per_word;
 677                speed = chip->speed_hz;
 678
 679                if (transfer->speed_hz)
 680                        speed = transfer->speed_hz;
 681
 682                if (transfer->bits_per_word)
 683                        bits = transfer->bits_per_word;
 684
 685                clk_div = ssp_get_clk_div(drv_data, speed);
 686
 687                if (bits <= 8) {
 688                        drv_data->n_bytes = 1;
 689                        drv_data->read = drv_data->read != null_reader ?
 690                                                u8_reader : null_reader;
 691                        drv_data->write = drv_data->write != null_writer ?
 692                                                u8_writer : null_writer;
 693                } else if (bits <= 16) {
 694                        drv_data->n_bytes = 2;
 695                        drv_data->read = drv_data->read != null_reader ?
 696                                                u16_reader : null_reader;
 697                        drv_data->write = drv_data->write != null_writer ?
 698                                                u16_writer : null_writer;
 699                } else if (bits <= 32) {
 700                        drv_data->n_bytes = 4;
 701                        drv_data->read = drv_data->read != null_reader ?
 702                                                u32_reader : null_reader;
 703                        drv_data->write = drv_data->write != null_writer ?
 704                                                u32_writer : null_writer;
 705                }
 706                /* if bits/word is changed in dma mode, then must check the
 707                 * thresholds and burst also */
 708                if (chip->enable_dma) {
 709                        if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
 710                                                        message->spi,
 711                                                        bits, &dma_burst,
 712                                                        &dma_thresh))
 713                                if (printk_ratelimit())
 714                                        dev_warn(&message->spi->dev,
 715                                                "pump_transfers: "
 716                                                "DMA burst size reduced to "
 717                                                "match bits_per_word\n");
 718                }
 719
 720                cr0 = clk_div
 721                        | SSCR0_Motorola
 722                        | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
 723                        | SSCR0_SSE
 724                        | (bits > 16 ? SSCR0_EDSS : 0);
 725        }
 726
 727        message->state = RUNNING_STATE;
 728
 729        drv_data->dma_mapped = 0;
 730        if (pxa2xx_spi_dma_is_possible(drv_data->len))
 731                drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
 732        if (drv_data->dma_mapped) {
 733
 734                /* Ensure we have the correct interrupt handler */
 735                drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
 736
 737                pxa2xx_spi_dma_prepare(drv_data, dma_burst);
 738
 739                /* Clear status and start DMA engine */
 740                cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
 741                write_SSSR(drv_data->clear_sr, reg);
 742
 743                pxa2xx_spi_dma_start(drv_data);
 744        } else {
 745                /* Ensure we have the correct interrupt handler */
 746                drv_data->transfer_handler = interrupt_transfer;
 747
 748                /* Clear status  */
 749                cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
 750                write_SSSR_CS(drv_data, drv_data->clear_sr);
 751        }
 752
 753        if (is_lpss_ssp(drv_data)) {
 754                if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold)
 755                        write_SSIRF(chip->lpss_rx_threshold, reg);
 756                if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold)
 757                        write_SSITF(chip->lpss_tx_threshold, reg);
 758        }
 759
 760        /* see if we need to reload the config registers */
 761        if ((read_SSCR0(reg) != cr0)
 762                || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
 763                        (cr1 & SSCR1_CHANGE_MASK)) {
 764
 765                /* stop the SSP, and update the other bits */
 766                write_SSCR0(cr0 & ~SSCR0_SSE, reg);
 767                if (!pxa25x_ssp_comp(drv_data))
 768                        write_SSTO(chip->timeout, reg);
 769                /* first set CR1 without interrupt and service enables */
 770                write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
 771                /* restart the SSP */
 772                write_SSCR0(cr0, reg);
 773
 774        } else {
 775                if (!pxa25x_ssp_comp(drv_data))
 776                        write_SSTO(chip->timeout, reg);
 777        }
 778
 779        cs_assert(drv_data);
 780
 781        /* after chip select, release the data by enabling service
 782         * requests and interrupts, without changing any mode bits */
 783        write_SSCR1(cr1, reg);
 784}
 785
 786static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
 787                                           struct spi_message *msg)
 788{
 789        struct driver_data *drv_data = spi_master_get_devdata(master);
 790
 791        drv_data->cur_msg = msg;
 792        /* Initial message state*/
 793        drv_data->cur_msg->state = START_STATE;
 794        drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
 795                                                struct spi_transfer,
 796                                                transfer_list);
 797
 798        /* prepare to setup the SSP, in pump_transfers, using the per
 799         * chip configuration */
 800        drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
 801
 802        /* Mark as busy and launch transfers */
 803        tasklet_schedule(&drv_data->pump_transfers);
 804        return 0;
 805}
 806
 807static int pxa2xx_spi_prepare_transfer(struct spi_master *master)
 808{
 809        struct driver_data *drv_data = spi_master_get_devdata(master);
 810
 811        pm_runtime_get_sync(&drv_data->pdev->dev);
 812        return 0;
 813}
 814
 815static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
 816{
 817        struct driver_data *drv_data = spi_master_get_devdata(master);
 818
 819        /* Disable the SSP now */
 820        write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE,
 821                    drv_data->ioaddr);
 822
 823        pm_runtime_mark_last_busy(&drv_data->pdev->dev);
 824        pm_runtime_put_autosuspend(&drv_data->pdev->dev);
 825        return 0;
 826}
 827
 828static int setup_cs(struct spi_device *spi, struct chip_data *chip,
 829                    struct pxa2xx_spi_chip *chip_info)
 830{
 831        int err = 0;
 832
 833        if (chip == NULL || chip_info == NULL)
 834                return 0;
 835
 836        /* NOTE: setup() can be called multiple times, possibly with
 837         * different chip_info, release previously requested GPIO
 838         */
 839        if (gpio_is_valid(chip->gpio_cs))
 840                gpio_free(chip->gpio_cs);
 841
 842        /* If (*cs_control) is provided, ignore GPIO chip select */
 843        if (chip_info->cs_control) {
 844                chip->cs_control = chip_info->cs_control;
 845                return 0;
 846        }
 847
 848        if (gpio_is_valid(chip_info->gpio_cs)) {
 849                err = gpio_request(chip_info->gpio_cs, "SPI_CS");
 850                if (err) {
 851                        dev_err(&spi->dev, "failed to request chip select "
 852                                        "GPIO%d\n", chip_info->gpio_cs);
 853                        return err;
 854                }
 855
 856                chip->gpio_cs = chip_info->gpio_cs;
 857                chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
 858
 859                err = gpio_direction_output(chip->gpio_cs,
 860                                        !chip->gpio_cs_inverted);
 861        }
 862
 863        return err;
 864}
 865
 866static int setup(struct spi_device *spi)
 867{
 868        struct pxa2xx_spi_chip *chip_info = NULL;
 869        struct chip_data *chip;
 870        struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 871        unsigned int clk_div;
 872        uint tx_thres, tx_hi_thres, rx_thres;
 873
 874        if (is_lpss_ssp(drv_data)) {
 875                tx_thres = LPSS_TX_LOTHRESH_DFLT;
 876                tx_hi_thres = LPSS_TX_HITHRESH_DFLT;
 877                rx_thres = LPSS_RX_THRESH_DFLT;
 878        } else {
 879                tx_thres = TX_THRESH_DFLT;
 880                tx_hi_thres = 0;
 881                rx_thres = RX_THRESH_DFLT;
 882        }
 883
 884        /* Only alloc on first setup */
 885        chip = spi_get_ctldata(spi);
 886        if (!chip) {
 887                chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 888                if (!chip) {
 889                        dev_err(&spi->dev,
 890                                "failed setup: can't allocate chip data\n");
 891                        return -ENOMEM;
 892                }
 893
 894                if (drv_data->ssp_type == CE4100_SSP) {
 895                        if (spi->chip_select > 4) {
 896                                dev_err(&spi->dev, "failed setup: "
 897                                "cs number must not be > 4.\n");
 898                                kfree(chip);
 899                                return -EINVAL;
 900                        }
 901
 902                        chip->frm = spi->chip_select;
 903                } else
 904                        chip->gpio_cs = -1;
 905                chip->enable_dma = 0;
 906                chip->timeout = TIMOUT_DFLT;
 907        }
 908
 909        /* protocol drivers may change the chip settings, so...
 910         * if chip_info exists, use it */
 911        chip_info = spi->controller_data;
 912
 913        /* chip_info isn't always needed */
 914        chip->cr1 = 0;
 915        if (chip_info) {
 916                if (chip_info->timeout)
 917                        chip->timeout = chip_info->timeout;
 918                if (chip_info->tx_threshold)
 919                        tx_thres = chip_info->tx_threshold;
 920                if (chip_info->tx_hi_threshold)
 921                        tx_hi_thres = chip_info->tx_hi_threshold;
 922                if (chip_info->rx_threshold)
 923                        rx_thres = chip_info->rx_threshold;
 924                chip->enable_dma = drv_data->master_info->enable_dma;
 925                chip->dma_threshold = 0;
 926                if (chip_info->enable_loopback)
 927                        chip->cr1 = SSCR1_LBM;
 928        } else if (ACPI_HANDLE(&spi->dev)) {
 929                /*
 930                 * Slave devices enumerated from ACPI namespace don't
 931                 * usually have chip_info but we still might want to use
 932                 * DMA with them.
 933                 */
 934                chip->enable_dma = drv_data->master_info->enable_dma;
 935        }
 936
 937        chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
 938                        (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
 939
 940        chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
 941        chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
 942                                | SSITF_TxHiThresh(tx_hi_thres);
 943
 944        /* set dma burst and threshold outside of chip_info path so that if
 945         * chip_info goes away after setting chip->enable_dma, the
 946         * burst and threshold can still respond to changes in bits_per_word */
 947        if (chip->enable_dma) {
 948                /* set up legal burst and threshold for dma */
 949                if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
 950                                                spi->bits_per_word,
 951                                                &chip->dma_burst_size,
 952                                                &chip->dma_threshold)) {
 953                        dev_warn(&spi->dev, "in setup: DMA burst size reduced "
 954                                        "to match bits_per_word\n");
 955                }
 956        }
 957
 958        clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz);
 959        chip->speed_hz = spi->max_speed_hz;
 960
 961        chip->cr0 = clk_div
 962                        | SSCR0_Motorola
 963                        | SSCR0_DataSize(spi->bits_per_word > 16 ?
 964                                spi->bits_per_word - 16 : spi->bits_per_word)
 965                        | SSCR0_SSE
 966                        | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
 967        chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
 968        chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
 969                        | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
 970
 971        if (spi->mode & SPI_LOOP)
 972                chip->cr1 |= SSCR1_LBM;
 973
 974        /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
 975        if (!pxa25x_ssp_comp(drv_data))
 976                dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
 977                        drv_data->max_clk_rate
 978                                / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
 979                        chip->enable_dma ? "DMA" : "PIO");
 980        else
 981                dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
 982                        drv_data->max_clk_rate / 2
 983                                / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
 984                        chip->enable_dma ? "DMA" : "PIO");
 985
 986        if (spi->bits_per_word <= 8) {
 987                chip->n_bytes = 1;
 988                chip->read = u8_reader;
 989                chip->write = u8_writer;
 990        } else if (spi->bits_per_word <= 16) {
 991                chip->n_bytes = 2;
 992                chip->read = u16_reader;
 993                chip->write = u16_writer;
 994        } else if (spi->bits_per_word <= 32) {
 995                chip->cr0 |= SSCR0_EDSS;
 996                chip->n_bytes = 4;
 997                chip->read = u32_reader;
 998                chip->write = u32_writer;
 999        }
1000        chip->bits_per_word = spi->bits_per_word;
1001
1002        spi_set_ctldata(spi, chip);
1003
1004        if (drv_data->ssp_type == CE4100_SSP)
1005                return 0;
1006
1007        return setup_cs(spi, chip, chip_info);
1008}
1009
1010static void cleanup(struct spi_device *spi)
1011{
1012        struct chip_data *chip = spi_get_ctldata(spi);
1013        struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1014
1015        if (!chip)
1016                return;
1017
1018        if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1019                gpio_free(chip->gpio_cs);
1020
1021        kfree(chip);
1022}
1023
1024#ifdef CONFIG_ACPI
1025static struct pxa2xx_spi_master *
1026pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1027{
1028        struct pxa2xx_spi_master *pdata;
1029        struct acpi_device *adev;
1030        struct ssp_device *ssp;
1031        struct resource *res;
1032        int devid;
1033
1034        if (!ACPI_HANDLE(&pdev->dev) ||
1035            acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
1036                return NULL;
1037
1038        pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1039        if (!pdata) {
1040                dev_err(&pdev->dev,
1041                        "failed to allocate memory for platform data\n");
1042                return NULL;
1043        }
1044
1045        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1046        if (!res)
1047                return NULL;
1048
1049        ssp = &pdata->ssp;
1050
1051        ssp->phys_base = res->start;
1052        ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1053        if (IS_ERR(ssp->mmio_base))
1054                return NULL;
1055
1056        ssp->clk = devm_clk_get(&pdev->dev, NULL);
1057        ssp->irq = platform_get_irq(pdev, 0);
1058        ssp->type = LPSS_SSP;
1059        ssp->pdev = pdev;
1060
1061        ssp->port_id = -1;
1062        if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid))
1063                ssp->port_id = devid;
1064
1065        pdata->num_chipselect = 1;
1066        pdata->enable_dma = true;
1067
1068        return pdata;
1069}
1070
1071static struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1072        { "INT33C0", 0 },
1073        { "INT33C1", 0 },
1074        { "80860F0E", 0 },
1075        { },
1076};
1077MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1078#else
1079static inline struct pxa2xx_spi_master *
1080pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1081{
1082        return NULL;
1083}
1084#endif
1085
1086static int pxa2xx_spi_probe(struct platform_device *pdev)
1087{
1088        struct device *dev = &pdev->dev;
1089        struct pxa2xx_spi_master *platform_info;
1090        struct spi_master *master;
1091        struct driver_data *drv_data;
1092        struct ssp_device *ssp;
1093        int status;
1094
1095        platform_info = dev_get_platdata(dev);
1096        if (!platform_info) {
1097                platform_info = pxa2xx_spi_acpi_get_pdata(pdev);
1098                if (!platform_info) {
1099                        dev_err(&pdev->dev, "missing platform data\n");
1100                        return -ENODEV;
1101                }
1102        }
1103
1104        ssp = pxa_ssp_request(pdev->id, pdev->name);
1105        if (!ssp)
1106                ssp = &platform_info->ssp;
1107
1108        if (!ssp->mmio_base) {
1109                dev_err(&pdev->dev, "failed to get ssp\n");
1110                return -ENODEV;
1111        }
1112
1113        /* Allocate master with space for drv_data and null dma buffer */
1114        master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1115        if (!master) {
1116                dev_err(&pdev->dev, "cannot alloc spi_master\n");
1117                pxa_ssp_free(ssp);
1118                return -ENOMEM;
1119        }
1120        drv_data = spi_master_get_devdata(master);
1121        drv_data->master = master;
1122        drv_data->master_info = platform_info;
1123        drv_data->pdev = pdev;
1124        drv_data->ssp = ssp;
1125
1126        master->dev.parent = &pdev->dev;
1127        master->dev.of_node = pdev->dev.of_node;
1128        /* the spi->mode bits understood by this driver: */
1129        master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1130
1131        master->bus_num = ssp->port_id;
1132        master->num_chipselect = platform_info->num_chipselect;
1133        master->dma_alignment = DMA_ALIGNMENT;
1134        master->cleanup = cleanup;
1135        master->setup = setup;
1136        master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1137        master->prepare_transfer_hardware = pxa2xx_spi_prepare_transfer;
1138        master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1139
1140        drv_data->ssp_type = ssp->type;
1141        drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT);
1142
1143        drv_data->ioaddr = ssp->mmio_base;
1144        drv_data->ssdr_physical = ssp->phys_base + SSDR;
1145        if (pxa25x_ssp_comp(drv_data)) {
1146                master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1147                drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1148                drv_data->dma_cr1 = 0;
1149                drv_data->clear_sr = SSSR_ROR;
1150                drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1151        } else {
1152                master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1153                drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1154                drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1155                drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1156                drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1157        }
1158
1159        status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1160                        drv_data);
1161        if (status < 0) {
1162                dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1163                goto out_error_master_alloc;
1164        }
1165
1166        /* Setup DMA if requested */
1167        drv_data->tx_channel = -1;
1168        drv_data->rx_channel = -1;
1169        if (platform_info->enable_dma) {
1170                status = pxa2xx_spi_dma_setup(drv_data);
1171                if (status) {
1172                        dev_dbg(dev, "no DMA channels available, using PIO\n");
1173                        platform_info->enable_dma = false;
1174                }
1175        }
1176
1177        /* Enable SOC clock */
1178        clk_prepare_enable(ssp->clk);
1179
1180        drv_data->max_clk_rate = clk_get_rate(ssp->clk);
1181
1182        /* Load default SSP configuration */
1183        write_SSCR0(0, drv_data->ioaddr);
1184        write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1185                                SSCR1_TxTresh(TX_THRESH_DFLT),
1186                                drv_data->ioaddr);
1187        write_SSCR0(SSCR0_SCR(2)
1188                        | SSCR0_Motorola
1189                        | SSCR0_DataSize(8),
1190                        drv_data->ioaddr);
1191        if (!pxa25x_ssp_comp(drv_data))
1192                write_SSTO(0, drv_data->ioaddr);
1193        write_SSPSP(0, drv_data->ioaddr);
1194
1195        lpss_ssp_setup(drv_data);
1196
1197        tasklet_init(&drv_data->pump_transfers, pump_transfers,
1198                     (unsigned long)drv_data);
1199
1200        /* Register with the SPI framework */
1201        platform_set_drvdata(pdev, drv_data);
1202        status = spi_register_master(master);
1203        if (status != 0) {
1204                dev_err(&pdev->dev, "problem registering spi master\n");
1205                goto out_error_clock_enabled;
1206        }
1207
1208        pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1209        pm_runtime_use_autosuspend(&pdev->dev);
1210        pm_runtime_set_active(&pdev->dev);
1211        pm_runtime_enable(&pdev->dev);
1212
1213        return status;
1214
1215out_error_clock_enabled:
1216        clk_disable_unprepare(ssp->clk);
1217        pxa2xx_spi_dma_release(drv_data);
1218        free_irq(ssp->irq, drv_data);
1219
1220out_error_master_alloc:
1221        spi_master_put(master);
1222        pxa_ssp_free(ssp);
1223        return status;
1224}
1225
1226static int pxa2xx_spi_remove(struct platform_device *pdev)
1227{
1228        struct driver_data *drv_data = platform_get_drvdata(pdev);
1229        struct ssp_device *ssp;
1230
1231        if (!drv_data)
1232                return 0;
1233        ssp = drv_data->ssp;
1234
1235        pm_runtime_get_sync(&pdev->dev);
1236
1237        /* Disable the SSP at the peripheral and SOC level */
1238        write_SSCR0(0, drv_data->ioaddr);
1239        clk_disable_unprepare(ssp->clk);
1240
1241        /* Release DMA */
1242        if (drv_data->master_info->enable_dma)
1243                pxa2xx_spi_dma_release(drv_data);
1244
1245        pm_runtime_put_noidle(&pdev->dev);
1246        pm_runtime_disable(&pdev->dev);
1247
1248        /* Release IRQ */
1249        free_irq(ssp->irq, drv_data);
1250
1251        /* Release SSP */
1252        pxa_ssp_free(ssp);
1253
1254        /* Disconnect from the SPI framework */
1255        spi_unregister_master(drv_data->master);
1256
1257        return 0;
1258}
1259
1260static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1261{
1262        int status = 0;
1263
1264        if ((status = pxa2xx_spi_remove(pdev)) != 0)
1265                dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1266}
1267
1268#ifdef CONFIG_PM
1269static int pxa2xx_spi_suspend(struct device *dev)
1270{
1271        struct driver_data *drv_data = dev_get_drvdata(dev);
1272        struct ssp_device *ssp = drv_data->ssp;
1273        int status = 0;
1274
1275        status = spi_master_suspend(drv_data->master);
1276        if (status != 0)
1277                return status;
1278        write_SSCR0(0, drv_data->ioaddr);
1279        clk_disable_unprepare(ssp->clk);
1280
1281        return 0;
1282}
1283
1284static int pxa2xx_spi_resume(struct device *dev)
1285{
1286        struct driver_data *drv_data = dev_get_drvdata(dev);
1287        struct ssp_device *ssp = drv_data->ssp;
1288        int status = 0;
1289
1290        pxa2xx_spi_dma_resume(drv_data);
1291
1292        /* Enable the SSP clock */
1293        clk_prepare_enable(ssp->clk);
1294
1295        /* Start the queue running */
1296        status = spi_master_resume(drv_data->master);
1297        if (status != 0) {
1298                dev_err(dev, "problem starting queue (%d)\n", status);
1299                return status;
1300        }
1301
1302        return 0;
1303}
1304#endif
1305
1306#ifdef CONFIG_PM_RUNTIME
1307static int pxa2xx_spi_runtime_suspend(struct device *dev)
1308{
1309        struct driver_data *drv_data = dev_get_drvdata(dev);
1310
1311        clk_disable_unprepare(drv_data->ssp->clk);
1312        return 0;
1313}
1314
1315static int pxa2xx_spi_runtime_resume(struct device *dev)
1316{
1317        struct driver_data *drv_data = dev_get_drvdata(dev);
1318
1319        clk_prepare_enable(drv_data->ssp->clk);
1320        return 0;
1321}
1322#endif
1323
1324static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1325        SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1326        SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1327                           pxa2xx_spi_runtime_resume, NULL)
1328};
1329
1330static struct platform_driver driver = {
1331        .driver = {
1332                .name   = "pxa2xx-spi",
1333                .owner  = THIS_MODULE,
1334                .pm     = &pxa2xx_spi_pm_ops,
1335                .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1336        },
1337        .probe = pxa2xx_spi_probe,
1338        .remove = pxa2xx_spi_remove,
1339        .shutdown = pxa2xx_spi_shutdown,
1340};
1341
1342static int __init pxa2xx_spi_init(void)
1343{
1344        return platform_driver_register(&driver);
1345}
1346subsys_initcall(pxa2xx_spi_init);
1347
1348static void __exit pxa2xx_spi_exit(void)
1349{
1350        platform_driver_unregister(&driver);
1351}
1352module_exit(pxa2xx_spi_exit);
1353
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