linux/drivers/spi/spi-bfin5xx.c
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   1/*
   2 * Blackfin On-Chip SPI Driver
   3 *
   4 * Copyright 2004-2010 Analog Devices Inc.
   5 *
   6 * Enter bugs at http://blackfin.uclinux.org/
   7 *
   8 * Licensed under the GPL-2 or later.
   9 */
  10
  11#include <linux/init.h>
  12#include <linux/module.h>
  13#include <linux/delay.h>
  14#include <linux/device.h>
  15#include <linux/slab.h>
  16#include <linux/io.h>
  17#include <linux/ioport.h>
  18#include <linux/irq.h>
  19#include <linux/errno.h>
  20#include <linux/interrupt.h>
  21#include <linux/platform_device.h>
  22#include <linux/dma-mapping.h>
  23#include <linux/spi/spi.h>
  24#include <linux/workqueue.h>
  25
  26#include <asm/dma.h>
  27#include <asm/portmux.h>
  28#include <asm/bfin5xx_spi.h>
  29#include <asm/cacheflush.h>
  30
  31#define DRV_NAME        "bfin-spi"
  32#define DRV_AUTHOR      "Bryan Wu, Luke Yang"
  33#define DRV_DESC        "Blackfin on-chip SPI Controller Driver"
  34#define DRV_VERSION     "1.0"
  35
  36MODULE_AUTHOR(DRV_AUTHOR);
  37MODULE_DESCRIPTION(DRV_DESC);
  38MODULE_LICENSE("GPL");
  39
  40#define START_STATE     ((void *)0)
  41#define RUNNING_STATE   ((void *)1)
  42#define DONE_STATE      ((void *)2)
  43#define ERROR_STATE     ((void *)-1)
  44
  45struct bfin_spi_master_data;
  46
  47struct bfin_spi_transfer_ops {
  48        void (*write) (struct bfin_spi_master_data *);
  49        void (*read) (struct bfin_spi_master_data *);
  50        void (*duplex) (struct bfin_spi_master_data *);
  51};
  52
  53struct bfin_spi_master_data {
  54        /* Driver model hookup */
  55        struct platform_device *pdev;
  56
  57        /* SPI framework hookup */
  58        struct spi_master *master;
  59
  60        /* Regs base of SPI controller */
  61        struct bfin_spi_regs __iomem *regs;
  62
  63        /* Pin request list */
  64        u16 *pin_req;
  65
  66        /* BFIN hookup */
  67        struct bfin5xx_spi_master *master_info;
  68
  69        /* Driver message queue */
  70        struct workqueue_struct *workqueue;
  71        struct work_struct pump_messages;
  72        spinlock_t lock;
  73        struct list_head queue;
  74        int busy;
  75        bool running;
  76
  77        /* Message Transfer pump */
  78        struct tasklet_struct pump_transfers;
  79
  80        /* Current message transfer state info */
  81        struct spi_message *cur_msg;
  82        struct spi_transfer *cur_transfer;
  83        struct bfin_spi_slave_data *cur_chip;
  84        size_t len_in_bytes;
  85        size_t len;
  86        void *tx;
  87        void *tx_end;
  88        void *rx;
  89        void *rx_end;
  90
  91        /* DMA stuffs */
  92        int dma_channel;
  93        int dma_mapped;
  94        int dma_requested;
  95        dma_addr_t rx_dma;
  96        dma_addr_t tx_dma;
  97
  98        int irq_requested;
  99        int spi_irq;
 100
 101        size_t rx_map_len;
 102        size_t tx_map_len;
 103        u8 n_bytes;
 104        u16 ctrl_reg;
 105        u16 flag_reg;
 106
 107        int cs_change;
 108        const struct bfin_spi_transfer_ops *ops;
 109};
 110
 111struct bfin_spi_slave_data {
 112        u16 ctl_reg;
 113        u16 baud;
 114        u16 flag;
 115
 116        u8 chip_select_num;
 117        u8 enable_dma;
 118        u16 cs_chg_udelay;      /* Some devices require > 255usec delay */
 119        u32 cs_gpio;
 120        u16 idle_tx_val;
 121        u8 pio_interrupt;       /* use spi data irq */
 122        const struct bfin_spi_transfer_ops *ops;
 123};
 124
 125static void bfin_spi_enable(struct bfin_spi_master_data *drv_data)
 126{
 127        bfin_write_or(&drv_data->regs->ctl, BIT_CTL_ENABLE);
 128}
 129
 130static void bfin_spi_disable(struct bfin_spi_master_data *drv_data)
 131{
 132        bfin_write_and(&drv_data->regs->ctl, ~BIT_CTL_ENABLE);
 133}
 134
 135/* Caculate the SPI_BAUD register value based on input HZ */
 136static u16 hz_to_spi_baud(u32 speed_hz)
 137{
 138        u_long sclk = get_sclk();
 139        u16 spi_baud = (sclk / (2 * speed_hz));
 140
 141        if ((sclk % (2 * speed_hz)) > 0)
 142                spi_baud++;
 143
 144        if (spi_baud < MIN_SPI_BAUD_VAL)
 145                spi_baud = MIN_SPI_BAUD_VAL;
 146
 147        return spi_baud;
 148}
 149
 150static int bfin_spi_flush(struct bfin_spi_master_data *drv_data)
 151{
 152        unsigned long limit = loops_per_jiffy << 1;
 153
 154        /* wait for stop and clear stat */
 155        while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF) && --limit)
 156                cpu_relax();
 157
 158        bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
 159
 160        return limit;
 161}
 162
 163/* Chip select operation functions for cs_change flag */
 164static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip)
 165{
 166        if (likely(chip->chip_select_num < MAX_CTRL_CS))
 167                bfin_write_and(&drv_data->regs->flg, ~chip->flag);
 168        else
 169                gpio_set_value(chip->cs_gpio, 0);
 170}
 171
 172static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data,
 173                                 struct bfin_spi_slave_data *chip)
 174{
 175        if (likely(chip->chip_select_num < MAX_CTRL_CS))
 176                bfin_write_or(&drv_data->regs->flg, chip->flag);
 177        else
 178                gpio_set_value(chip->cs_gpio, 1);
 179
 180        /* Move delay here for consistency */
 181        if (chip->cs_chg_udelay)
 182                udelay(chip->cs_chg_udelay);
 183}
 184
 185/* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
 186static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data,
 187                                      struct bfin_spi_slave_data *chip)
 188{
 189        if (chip->chip_select_num < MAX_CTRL_CS)
 190                bfin_write_or(&drv_data->regs->flg, chip->flag >> 8);
 191}
 192
 193static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data,
 194                                       struct bfin_spi_slave_data *chip)
 195{
 196        if (chip->chip_select_num < MAX_CTRL_CS)
 197                bfin_write_and(&drv_data->regs->flg, ~(chip->flag >> 8));
 198}
 199
 200/* stop controller and re-config current chip*/
 201static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data)
 202{
 203        struct bfin_spi_slave_data *chip = drv_data->cur_chip;
 204
 205        /* Clear status and disable clock */
 206        bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
 207        bfin_spi_disable(drv_data);
 208        dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
 209
 210        SSYNC();
 211
 212        /* Load the registers */
 213        bfin_write(&drv_data->regs->ctl, chip->ctl_reg);
 214        bfin_write(&drv_data->regs->baud, chip->baud);
 215
 216        bfin_spi_enable(drv_data);
 217        bfin_spi_cs_active(drv_data, chip);
 218}
 219
 220/* used to kick off transfer in rx mode and read unwanted RX data */
 221static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data)
 222{
 223        (void) bfin_read(&drv_data->regs->rdbr);
 224}
 225
 226static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data)
 227{
 228        /* clear RXS (we check for RXS inside the loop) */
 229        bfin_spi_dummy_read(drv_data);
 230
 231        while (drv_data->tx < drv_data->tx_end) {
 232                bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
 233                /* wait until transfer finished.
 234                   checking SPIF or TXS may not guarantee transfer completion */
 235                while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
 236                        cpu_relax();
 237                /* discard RX data and clear RXS */
 238                bfin_spi_dummy_read(drv_data);
 239        }
 240}
 241
 242static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data)
 243{
 244        u16 tx_val = drv_data->cur_chip->idle_tx_val;
 245
 246        /* discard old RX data and clear RXS */
 247        bfin_spi_dummy_read(drv_data);
 248
 249        while (drv_data->rx < drv_data->rx_end) {
 250                bfin_write(&drv_data->regs->tdbr, tx_val);
 251                while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
 252                        cpu_relax();
 253                *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
 254        }
 255}
 256
 257static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data)
 258{
 259        /* discard old RX data and clear RXS */
 260        bfin_spi_dummy_read(drv_data);
 261
 262        while (drv_data->rx < drv_data->rx_end) {
 263                bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
 264                while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
 265                        cpu_relax();
 266                *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
 267        }
 268}
 269
 270static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = {
 271        .write  = bfin_spi_u8_writer,
 272        .read   = bfin_spi_u8_reader,
 273        .duplex = bfin_spi_u8_duplex,
 274};
 275
 276static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data)
 277{
 278        /* clear RXS (we check for RXS inside the loop) */
 279        bfin_spi_dummy_read(drv_data);
 280
 281        while (drv_data->tx < drv_data->tx_end) {
 282                bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
 283                drv_data->tx += 2;
 284                /* wait until transfer finished.
 285                   checking SPIF or TXS may not guarantee transfer completion */
 286                while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
 287                        cpu_relax();
 288                /* discard RX data and clear RXS */
 289                bfin_spi_dummy_read(drv_data);
 290        }
 291}
 292
 293static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data)
 294{
 295        u16 tx_val = drv_data->cur_chip->idle_tx_val;
 296
 297        /* discard old RX data and clear RXS */
 298        bfin_spi_dummy_read(drv_data);
 299
 300        while (drv_data->rx < drv_data->rx_end) {
 301                bfin_write(&drv_data->regs->tdbr, tx_val);
 302                while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
 303                        cpu_relax();
 304                *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
 305                drv_data->rx += 2;
 306        }
 307}
 308
 309static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data)
 310{
 311        /* discard old RX data and clear RXS */
 312        bfin_spi_dummy_read(drv_data);
 313
 314        while (drv_data->rx < drv_data->rx_end) {
 315                bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
 316                drv_data->tx += 2;
 317                while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
 318                        cpu_relax();
 319                *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
 320                drv_data->rx += 2;
 321        }
 322}
 323
 324static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = {
 325        .write  = bfin_spi_u16_writer,
 326        .read   = bfin_spi_u16_reader,
 327        .duplex = bfin_spi_u16_duplex,
 328};
 329
 330/* test if there is more transfer to be done */
 331static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data)
 332{
 333        struct spi_message *msg = drv_data->cur_msg;
 334        struct spi_transfer *trans = drv_data->cur_transfer;
 335
 336        /* Move to next transfer */
 337        if (trans->transfer_list.next != &msg->transfers) {
 338                drv_data->cur_transfer =
 339                    list_entry(trans->transfer_list.next,
 340                               struct spi_transfer, transfer_list);
 341                return RUNNING_STATE;
 342        } else
 343                return DONE_STATE;
 344}
 345
 346/*
 347 * caller already set message->status;
 348 * dma and pio irqs are blocked give finished message back
 349 */
 350static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data)
 351{
 352        struct bfin_spi_slave_data *chip = drv_data->cur_chip;
 353        struct spi_transfer *last_transfer;
 354        unsigned long flags;
 355        struct spi_message *msg;
 356
 357        spin_lock_irqsave(&drv_data->lock, flags);
 358        msg = drv_data->cur_msg;
 359        drv_data->cur_msg = NULL;
 360        drv_data->cur_transfer = NULL;
 361        drv_data->cur_chip = NULL;
 362        queue_work(drv_data->workqueue, &drv_data->pump_messages);
 363        spin_unlock_irqrestore(&drv_data->lock, flags);
 364
 365        last_transfer = list_entry(msg->transfers.prev,
 366                                   struct spi_transfer, transfer_list);
 367
 368        msg->state = NULL;
 369
 370        if (!drv_data->cs_change)
 371                bfin_spi_cs_deactive(drv_data, chip);
 372
 373        /* Not stop spi in autobuffer mode */
 374        if (drv_data->tx_dma != 0xFFFF)
 375                bfin_spi_disable(drv_data);
 376
 377        if (msg->complete)
 378                msg->complete(msg->context);
 379}
 380
 381/* spi data irq handler */
 382static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
 383{
 384        struct bfin_spi_master_data *drv_data = dev_id;
 385        struct bfin_spi_slave_data *chip = drv_data->cur_chip;
 386        struct spi_message *msg = drv_data->cur_msg;
 387        int n_bytes = drv_data->n_bytes;
 388        int loop = 0;
 389
 390        /* wait until transfer finished. */
 391        while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
 392                cpu_relax();
 393
 394        if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
 395                (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
 396                /* last read */
 397                if (drv_data->rx) {
 398                        dev_dbg(&drv_data->pdev->dev, "last read\n");
 399                        if (!(n_bytes % 2)) {
 400                                u16 *buf = (u16 *)drv_data->rx;
 401                                for (loop = 0; loop < n_bytes / 2; loop++)
 402                                        *buf++ = bfin_read(&drv_data->regs->rdbr);
 403                        } else {
 404                                u8 *buf = (u8 *)drv_data->rx;
 405                                for (loop = 0; loop < n_bytes; loop++)
 406                                        *buf++ = bfin_read(&drv_data->regs->rdbr);
 407                        }
 408                        drv_data->rx += n_bytes;
 409                }
 410
 411                msg->actual_length += drv_data->len_in_bytes;
 412                if (drv_data->cs_change)
 413                        bfin_spi_cs_deactive(drv_data, chip);
 414                /* Move to next transfer */
 415                msg->state = bfin_spi_next_transfer(drv_data);
 416
 417                disable_irq_nosync(drv_data->spi_irq);
 418
 419                /* Schedule transfer tasklet */
 420                tasklet_schedule(&drv_data->pump_transfers);
 421                return IRQ_HANDLED;
 422        }
 423
 424        if (drv_data->rx && drv_data->tx) {
 425                /* duplex */
 426                dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
 427                if (!(n_bytes % 2)) {
 428                        u16 *buf = (u16 *)drv_data->rx;
 429                        u16 *buf2 = (u16 *)drv_data->tx;
 430                        for (loop = 0; loop < n_bytes / 2; loop++) {
 431                                *buf++ = bfin_read(&drv_data->regs->rdbr);
 432                                bfin_write(&drv_data->regs->tdbr, *buf2++);
 433                        }
 434                } else {
 435                        u8 *buf = (u8 *)drv_data->rx;
 436                        u8 *buf2 = (u8 *)drv_data->tx;
 437                        for (loop = 0; loop < n_bytes; loop++) {
 438                                *buf++ = bfin_read(&drv_data->regs->rdbr);
 439                                bfin_write(&drv_data->regs->tdbr, *buf2++);
 440                        }
 441                }
 442        } else if (drv_data->rx) {
 443                /* read */
 444                dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
 445                if (!(n_bytes % 2)) {
 446                        u16 *buf = (u16 *)drv_data->rx;
 447                        for (loop = 0; loop < n_bytes / 2; loop++) {
 448                                *buf++ = bfin_read(&drv_data->regs->rdbr);
 449                                bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
 450                        }
 451                } else {
 452                        u8 *buf = (u8 *)drv_data->rx;
 453                        for (loop = 0; loop < n_bytes; loop++) {
 454                                *buf++ = bfin_read(&drv_data->regs->rdbr);
 455                                bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
 456                        }
 457                }
 458        } else if (drv_data->tx) {
 459                /* write */
 460                dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
 461                if (!(n_bytes % 2)) {
 462                        u16 *buf = (u16 *)drv_data->tx;
 463                        for (loop = 0; loop < n_bytes / 2; loop++) {
 464                                bfin_read(&drv_data->regs->rdbr);
 465                                bfin_write(&drv_data->regs->tdbr, *buf++);
 466                        }
 467                } else {
 468                        u8 *buf = (u8 *)drv_data->tx;
 469                        for (loop = 0; loop < n_bytes; loop++) {
 470                                bfin_read(&drv_data->regs->rdbr);
 471                                bfin_write(&drv_data->regs->tdbr, *buf++);
 472                        }
 473                }
 474        }
 475
 476        if (drv_data->tx)
 477                drv_data->tx += n_bytes;
 478        if (drv_data->rx)
 479                drv_data->rx += n_bytes;
 480
 481        return IRQ_HANDLED;
 482}
 483
 484static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
 485{
 486        struct bfin_spi_master_data *drv_data = dev_id;
 487        struct bfin_spi_slave_data *chip = drv_data->cur_chip;
 488        struct spi_message *msg = drv_data->cur_msg;
 489        unsigned long timeout;
 490        unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
 491        u16 spistat = bfin_read(&drv_data->regs->stat);
 492
 493        dev_dbg(&drv_data->pdev->dev,
 494                "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
 495                dmastat, spistat);
 496
 497        if (drv_data->rx != NULL) {
 498                u16 cr = bfin_read(&drv_data->regs->ctl);
 499                /* discard old RX data and clear RXS */
 500                bfin_spi_dummy_read(drv_data);
 501                bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_ENABLE); /* Disable SPI */
 502                bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_TIMOD); /* Restore State */
 503                bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); /* Clear Status */
 504        }
 505
 506        clear_dma_irqstat(drv_data->dma_channel);
 507
 508        /*
 509         * wait for the last transaction shifted out.  HRM states:
 510         * at this point there may still be data in the SPI DMA FIFO waiting
 511         * to be transmitted ... software needs to poll TXS in the SPI_STAT
 512         * register until it goes low for 2 successive reads
 513         */
 514        if (drv_data->tx != NULL) {
 515                while ((bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS) ||
 516                       (bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS))
 517                        cpu_relax();
 518        }
 519
 520        dev_dbg(&drv_data->pdev->dev,
 521                "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
 522                dmastat, bfin_read(&drv_data->regs->stat));
 523
 524        timeout = jiffies + HZ;
 525        while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
 526                if (!time_before(jiffies, timeout)) {
 527                        dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
 528                        break;
 529                } else
 530                        cpu_relax();
 531
 532        if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
 533                msg->state = ERROR_STATE;
 534                dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
 535        } else {
 536                msg->actual_length += drv_data->len_in_bytes;
 537
 538                if (drv_data->cs_change)
 539                        bfin_spi_cs_deactive(drv_data, chip);
 540
 541                /* Move to next transfer */
 542                msg->state = bfin_spi_next_transfer(drv_data);
 543        }
 544
 545        /* Schedule transfer tasklet */
 546        tasklet_schedule(&drv_data->pump_transfers);
 547
 548        /* free the irq handler before next transfer */
 549        dev_dbg(&drv_data->pdev->dev,
 550                "disable dma channel irq%d\n",
 551                drv_data->dma_channel);
 552        dma_disable_irq_nosync(drv_data->dma_channel);
 553
 554        return IRQ_HANDLED;
 555}
 556
 557static void bfin_spi_pump_transfers(unsigned long data)
 558{
 559        struct bfin_spi_master_data *drv_data = (struct bfin_spi_master_data *)data;
 560        struct spi_message *message = NULL;
 561        struct spi_transfer *transfer = NULL;
 562        struct spi_transfer *previous = NULL;
 563        struct bfin_spi_slave_data *chip = NULL;
 564        unsigned int bits_per_word;
 565        u16 cr, cr_width, dma_width, dma_config;
 566        u32 tranf_success = 1;
 567        u8 full_duplex = 0;
 568
 569        /* Get current state information */
 570        message = drv_data->cur_msg;
 571        transfer = drv_data->cur_transfer;
 572        chip = drv_data->cur_chip;
 573
 574        /*
 575         * if msg is error or done, report it back using complete() callback
 576         */
 577
 578         /* Handle for abort */
 579        if (message->state == ERROR_STATE) {
 580                dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
 581                message->status = -EIO;
 582                bfin_spi_giveback(drv_data);
 583                return;
 584        }
 585
 586        /* Handle end of message */
 587        if (message->state == DONE_STATE) {
 588                dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
 589                message->status = 0;
 590                bfin_spi_flush(drv_data);
 591                bfin_spi_giveback(drv_data);
 592                return;
 593        }
 594
 595        /* Delay if requested at end of transfer */
 596        if (message->state == RUNNING_STATE) {
 597                dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
 598                previous = list_entry(transfer->transfer_list.prev,
 599                                      struct spi_transfer, transfer_list);
 600                if (previous->delay_usecs)
 601                        udelay(previous->delay_usecs);
 602        }
 603
 604        /* Flush any existing transfers that may be sitting in the hardware */
 605        if (bfin_spi_flush(drv_data) == 0) {
 606                dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
 607                message->status = -EIO;
 608                bfin_spi_giveback(drv_data);
 609                return;
 610        }
 611
 612        if (transfer->len == 0) {
 613                /* Move to next transfer of this msg */
 614                message->state = bfin_spi_next_transfer(drv_data);
 615                /* Schedule next transfer tasklet */
 616                tasklet_schedule(&drv_data->pump_transfers);
 617                return;
 618        }
 619
 620        if (transfer->tx_buf != NULL) {
 621                drv_data->tx = (void *)transfer->tx_buf;
 622                drv_data->tx_end = drv_data->tx + transfer->len;
 623                dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
 624                        transfer->tx_buf, drv_data->tx_end);
 625        } else {
 626                drv_data->tx = NULL;
 627        }
 628
 629        if (transfer->rx_buf != NULL) {
 630                full_duplex = transfer->tx_buf != NULL;
 631                drv_data->rx = transfer->rx_buf;
 632                drv_data->rx_end = drv_data->rx + transfer->len;
 633                dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
 634                        transfer->rx_buf, drv_data->rx_end);
 635        } else {
 636                drv_data->rx = NULL;
 637        }
 638
 639        drv_data->rx_dma = transfer->rx_dma;
 640        drv_data->tx_dma = transfer->tx_dma;
 641        drv_data->len_in_bytes = transfer->len;
 642        drv_data->cs_change = transfer->cs_change;
 643
 644        /* Bits per word setup */
 645        bits_per_word = transfer->bits_per_word;
 646        if (bits_per_word == 16) {
 647                drv_data->n_bytes = bits_per_word/8;
 648                drv_data->len = (transfer->len) >> 1;
 649                cr_width = BIT_CTL_WORDSIZE;
 650                drv_data->ops = &bfin_bfin_spi_transfer_ops_u16;
 651        } else if (bits_per_word == 8) {
 652                drv_data->n_bytes = bits_per_word/8;
 653                drv_data->len = transfer->len;
 654                cr_width = 0;
 655                drv_data->ops = &bfin_bfin_spi_transfer_ops_u8;
 656        }
 657        cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
 658        cr |= cr_width;
 659        bfin_write(&drv_data->regs->ctl, cr);
 660
 661        dev_dbg(&drv_data->pdev->dev,
 662                "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
 663                drv_data->ops, chip->ops, &bfin_bfin_spi_transfer_ops_u8);
 664
 665        message->state = RUNNING_STATE;
 666        dma_config = 0;
 667
 668        /* Speed setup (surely valid because already checked) */
 669        if (transfer->speed_hz)
 670                bfin_write(&drv_data->regs->baud, hz_to_spi_baud(transfer->speed_hz));
 671        else
 672                bfin_write(&drv_data->regs->baud, chip->baud);
 673
 674        bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
 675        bfin_spi_cs_active(drv_data, chip);
 676
 677        dev_dbg(&drv_data->pdev->dev,
 678                "now pumping a transfer: width is %d, len is %d\n",
 679                cr_width, transfer->len);
 680
 681        /*
 682         * Try to map dma buffer and do a dma transfer.  If successful use,
 683         * different way to r/w according to the enable_dma settings and if
 684         * we are not doing a full duplex transfer (since the hardware does
 685         * not support full duplex DMA transfers).
 686         */
 687        if (!full_duplex && drv_data->cur_chip->enable_dma
 688                                && drv_data->len > 6) {
 689
 690                unsigned long dma_start_addr, flags;
 691
 692                disable_dma(drv_data->dma_channel);
 693                clear_dma_irqstat(drv_data->dma_channel);
 694
 695                /* config dma channel */
 696                dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
 697                set_dma_x_count(drv_data->dma_channel, drv_data->len);
 698                if (cr_width == BIT_CTL_WORDSIZE) {
 699                        set_dma_x_modify(drv_data->dma_channel, 2);
 700                        dma_width = WDSIZE_16;
 701                } else {
 702                        set_dma_x_modify(drv_data->dma_channel, 1);
 703                        dma_width = WDSIZE_8;
 704                }
 705
 706                /* poll for SPI completion before start */
 707                while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
 708                        cpu_relax();
 709
 710                /* dirty hack for autobuffer DMA mode */
 711                if (drv_data->tx_dma == 0xFFFF) {
 712                        dev_dbg(&drv_data->pdev->dev,
 713                                "doing autobuffer DMA out.\n");
 714
 715                        /* no irq in autobuffer mode */
 716                        dma_config =
 717                            (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
 718                        set_dma_config(drv_data->dma_channel, dma_config);
 719                        set_dma_start_addr(drv_data->dma_channel,
 720                                        (unsigned long)drv_data->tx);
 721                        enable_dma(drv_data->dma_channel);
 722
 723                        /* start SPI transfer */
 724                        bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TIMOD_DMA_TX);
 725
 726                        /* just return here, there can only be one transfer
 727                         * in this mode
 728                         */
 729                        message->status = 0;
 730                        bfin_spi_giveback(drv_data);
 731                        return;
 732                }
 733
 734                /* In dma mode, rx or tx must be NULL in one transfer */
 735                dma_config = (RESTART | dma_width | DI_EN);
 736                if (drv_data->rx != NULL) {
 737                        /* set transfer mode, and enable SPI */
 738                        dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
 739                                drv_data->rx, drv_data->len_in_bytes);
 740
 741                        /* invalidate caches, if needed */
 742                        if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
 743                                invalidate_dcache_range((unsigned long) drv_data->rx,
 744                                                        (unsigned long) (drv_data->rx +
 745                                                        drv_data->len_in_bytes));
 746
 747                        dma_config |= WNR;
 748                        dma_start_addr = (unsigned long)drv_data->rx;
 749                        cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
 750
 751                } else if (drv_data->tx != NULL) {
 752                        dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
 753
 754                        /* flush caches, if needed */
 755                        if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
 756                                flush_dcache_range((unsigned long) drv_data->tx,
 757                                                (unsigned long) (drv_data->tx +
 758                                                drv_data->len_in_bytes));
 759
 760                        dma_start_addr = (unsigned long)drv_data->tx;
 761                        cr |= BIT_CTL_TIMOD_DMA_TX;
 762
 763                } else
 764                        BUG();
 765
 766                /* oh man, here there be monsters ... and i dont mean the
 767                 * fluffy cute ones from pixar, i mean the kind that'll eat
 768                 * your data, kick your dog, and love it all.  do *not* try
 769                 * and change these lines unless you (1) heavily test DMA
 770                 * with SPI flashes on a loaded system (e.g. ping floods),
 771                 * (2) know just how broken the DMA engine interaction with
 772                 * the SPI peripheral is, and (3) have someone else to blame
 773                 * when you screw it all up anyways.
 774                 */
 775                set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
 776                set_dma_config(drv_data->dma_channel, dma_config);
 777                local_irq_save(flags);
 778                SSYNC();
 779                bfin_write(&drv_data->regs->ctl, cr);
 780                enable_dma(drv_data->dma_channel);
 781                dma_enable_irq(drv_data->dma_channel);
 782                local_irq_restore(flags);
 783
 784                return;
 785        }
 786
 787        /*
 788         * We always use SPI_WRITE mode (transfer starts with TDBR write).
 789         * SPI_READ mode (transfer starts with RDBR read) seems to have
 790         * problems with setting up the output value in TDBR prior to the
 791         * start of the transfer.
 792         */
 793        bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TXMOD);
 794
 795        if (chip->pio_interrupt) {
 796                /* SPI irq should have been disabled by now */
 797
 798                /* discard old RX data and clear RXS */
 799                bfin_spi_dummy_read(drv_data);
 800
 801                /* start transfer */
 802                if (drv_data->tx == NULL)
 803                        bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
 804                else {
 805                        int loop;
 806                        if (bits_per_word == 16) {
 807                                u16 *buf = (u16 *)drv_data->tx;
 808                                for (loop = 0; loop < bits_per_word / 16;
 809                                                loop++) {
 810                                        bfin_write(&drv_data->regs->tdbr, *buf++);
 811                                }
 812                        } else if (bits_per_word == 8) {
 813                                u8 *buf = (u8 *)drv_data->tx;
 814                                for (loop = 0; loop < bits_per_word / 8; loop++)
 815                                        bfin_write(&drv_data->regs->tdbr, *buf++);
 816                        }
 817
 818                        drv_data->tx += drv_data->n_bytes;
 819                }
 820
 821                /* once TDBR is empty, interrupt is triggered */
 822                enable_irq(drv_data->spi_irq);
 823                return;
 824        }
 825
 826        /* IO mode */
 827        dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
 828
 829        if (full_duplex) {
 830                /* full duplex mode */
 831                BUG_ON((drv_data->tx_end - drv_data->tx) !=
 832                       (drv_data->rx_end - drv_data->rx));
 833                dev_dbg(&drv_data->pdev->dev,
 834                        "IO duplex: cr is 0x%x\n", cr);
 835
 836                drv_data->ops->duplex(drv_data);
 837
 838                if (drv_data->tx != drv_data->tx_end)
 839                        tranf_success = 0;
 840        } else if (drv_data->tx != NULL) {
 841                /* write only half duplex */
 842                dev_dbg(&drv_data->pdev->dev,
 843                        "IO write: cr is 0x%x\n", cr);
 844
 845                drv_data->ops->write(drv_data);
 846
 847                if (drv_data->tx != drv_data->tx_end)
 848                        tranf_success = 0;
 849        } else if (drv_data->rx != NULL) {
 850                /* read only half duplex */
 851                dev_dbg(&drv_data->pdev->dev,
 852                        "IO read: cr is 0x%x\n", cr);
 853
 854                drv_data->ops->read(drv_data);
 855                if (drv_data->rx != drv_data->rx_end)
 856                        tranf_success = 0;
 857        }
 858
 859        if (!tranf_success) {
 860                dev_dbg(&drv_data->pdev->dev,
 861                        "IO write error!\n");
 862                message->state = ERROR_STATE;
 863        } else {
 864                /* Update total byte transferred */
 865                message->actual_length += drv_data->len_in_bytes;
 866                /* Move to next transfer of this msg */
 867                message->state = bfin_spi_next_transfer(drv_data);
 868                if (drv_data->cs_change && message->state != DONE_STATE) {
 869                        bfin_spi_flush(drv_data);
 870                        bfin_spi_cs_deactive(drv_data, chip);
 871                }
 872        }
 873
 874        /* Schedule next transfer tasklet */
 875        tasklet_schedule(&drv_data->pump_transfers);
 876}
 877
 878/* pop a msg from queue and kick off real transfer */
 879static void bfin_spi_pump_messages(struct work_struct *work)
 880{
 881        struct bfin_spi_master_data *drv_data;
 882        unsigned long flags;
 883
 884        drv_data = container_of(work, struct bfin_spi_master_data, pump_messages);
 885
 886        /* Lock queue and check for queue work */
 887        spin_lock_irqsave(&drv_data->lock, flags);
 888        if (list_empty(&drv_data->queue) || !drv_data->running) {
 889                /* pumper kicked off but no work to do */
 890                drv_data->busy = 0;
 891                spin_unlock_irqrestore(&drv_data->lock, flags);
 892                return;
 893        }
 894
 895        /* Make sure we are not already running a message */
 896        if (drv_data->cur_msg) {
 897                spin_unlock_irqrestore(&drv_data->lock, flags);
 898                return;
 899        }
 900
 901        /* Extract head of queue */
 902        drv_data->cur_msg = list_entry(drv_data->queue.next,
 903                                       struct spi_message, queue);
 904
 905        /* Setup the SSP using the per chip configuration */
 906        drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
 907        bfin_spi_restore_state(drv_data);
 908
 909        list_del_init(&drv_data->cur_msg->queue);
 910
 911        /* Initial message state */
 912        drv_data->cur_msg->state = START_STATE;
 913        drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
 914                                            struct spi_transfer, transfer_list);
 915
 916        dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
 917                "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
 918                drv_data->cur_chip->baud, drv_data->cur_chip->flag,
 919                drv_data->cur_chip->ctl_reg);
 920
 921        dev_dbg(&drv_data->pdev->dev,
 922                "the first transfer len is %d\n",
 923                drv_data->cur_transfer->len);
 924
 925        /* Mark as busy and launch transfers */
 926        tasklet_schedule(&drv_data->pump_transfers);
 927
 928        drv_data->busy = 1;
 929        spin_unlock_irqrestore(&drv_data->lock, flags);
 930}
 931
 932/*
 933 * got a msg to transfer, queue it in drv_data->queue.
 934 * And kick off message pumper
 935 */
 936static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 937{
 938        struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
 939        unsigned long flags;
 940
 941        spin_lock_irqsave(&drv_data->lock, flags);
 942
 943        if (!drv_data->running) {
 944                spin_unlock_irqrestore(&drv_data->lock, flags);
 945                return -ESHUTDOWN;
 946        }
 947
 948        msg->actual_length = 0;
 949        msg->status = -EINPROGRESS;
 950        msg->state = START_STATE;
 951
 952        dev_dbg(&spi->dev, "adding an msg in transfer() \n");
 953        list_add_tail(&msg->queue, &drv_data->queue);
 954
 955        if (drv_data->running && !drv_data->busy)
 956                queue_work(drv_data->workqueue, &drv_data->pump_messages);
 957
 958        spin_unlock_irqrestore(&drv_data->lock, flags);
 959
 960        return 0;
 961}
 962
 963#define MAX_SPI_SSEL    7
 964
 965static const u16 ssel[][MAX_SPI_SSEL] = {
 966        {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
 967        P_SPI0_SSEL4, P_SPI0_SSEL5,
 968        P_SPI0_SSEL6, P_SPI0_SSEL7},
 969
 970        {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
 971        P_SPI1_SSEL4, P_SPI1_SSEL5,
 972        P_SPI1_SSEL6, P_SPI1_SSEL7},
 973
 974        {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
 975        P_SPI2_SSEL4, P_SPI2_SSEL5,
 976        P_SPI2_SSEL6, P_SPI2_SSEL7},
 977};
 978
 979/* setup for devices (may be called multiple times -- not just first setup) */
 980static int bfin_spi_setup(struct spi_device *spi)
 981{
 982        struct bfin5xx_spi_chip *chip_info;
 983        struct bfin_spi_slave_data *chip = NULL;
 984        struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
 985        u16 bfin_ctl_reg;
 986        int ret = -EINVAL;
 987
 988        /* Only alloc (or use chip_info) on first setup */
 989        chip_info = NULL;
 990        chip = spi_get_ctldata(spi);
 991        if (chip == NULL) {
 992                chip = kzalloc(sizeof(*chip), GFP_KERNEL);
 993                if (!chip) {
 994                        dev_err(&spi->dev, "cannot allocate chip data\n");
 995                        ret = -ENOMEM;
 996                        goto error;
 997                }
 998
 999                chip->enable_dma = 0;
1000                chip_info = spi->controller_data;
1001        }
1002
1003        /* Let people set non-standard bits directly */
1004        bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO |
1005                BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ;
1006
1007        /* chip_info isn't always needed */
1008        if (chip_info) {
1009                /* Make sure people stop trying to set fields via ctl_reg
1010                 * when they should actually be using common SPI framework.
1011                 * Currently we let through: WOM EMISO PSSE GM SZ.
1012                 * Not sure if a user actually needs/uses any of these,
1013                 * but let's assume (for now) they do.
1014                 */
1015                if (chip_info->ctl_reg & ~bfin_ctl_reg) {
1016                        dev_err(&spi->dev, "do not set bits in ctl_reg "
1017                                "that the SPI framework manages\n");
1018                        goto error;
1019                }
1020                chip->enable_dma = chip_info->enable_dma != 0
1021                    && drv_data->master_info->enable_dma;
1022                chip->ctl_reg = chip_info->ctl_reg;
1023                chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1024                chip->idle_tx_val = chip_info->idle_tx_val;
1025                chip->pio_interrupt = chip_info->pio_interrupt;
1026        } else {
1027                /* force a default base state */
1028                chip->ctl_reg &= bfin_ctl_reg;
1029        }
1030
1031        /* translate common spi framework into our register */
1032        if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1033                dev_err(&spi->dev, "unsupported spi modes detected\n");
1034                goto error;
1035        }
1036        if (spi->mode & SPI_CPOL)
1037                chip->ctl_reg |= BIT_CTL_CPOL;
1038        if (spi->mode & SPI_CPHA)
1039                chip->ctl_reg |= BIT_CTL_CPHA;
1040        if (spi->mode & SPI_LSB_FIRST)
1041                chip->ctl_reg |= BIT_CTL_LSBF;
1042        /* we dont support running in slave mode (yet?) */
1043        chip->ctl_reg |= BIT_CTL_MASTER;
1044
1045        /*
1046         * Notice: for blackfin, the speed_hz is the value of register
1047         * SPI_BAUD, not the real baudrate
1048         */
1049        chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1050        chip->chip_select_num = spi->chip_select;
1051        if (chip->chip_select_num < MAX_CTRL_CS) {
1052                if (!(spi->mode & SPI_CPHA))
1053                        dev_warn(&spi->dev, "Warning: SPI CPHA not set:"
1054                                " Slave Select not under software control!\n"
1055                                " See Documentation/blackfin/bfin-spi-notes.txt");
1056
1057                chip->flag = (1 << spi->chip_select) << 8;
1058        } else
1059                chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS;
1060
1061        if (chip->enable_dma && chip->pio_interrupt) {
1062                dev_err(&spi->dev, "enable_dma is set, "
1063                                "do not set pio_interrupt\n");
1064                goto error;
1065        }
1066        /*
1067         * if any one SPI chip is registered and wants DMA, request the
1068         * DMA channel for it
1069         */
1070        if (chip->enable_dma && !drv_data->dma_requested) {
1071                /* register dma irq handler */
1072                ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1073                if (ret) {
1074                        dev_err(&spi->dev,
1075                                "Unable to request BlackFin SPI DMA channel\n");
1076                        goto error;
1077                }
1078                drv_data->dma_requested = 1;
1079
1080                ret = set_dma_callback(drv_data->dma_channel,
1081                        bfin_spi_dma_irq_handler, drv_data);
1082                if (ret) {
1083                        dev_err(&spi->dev, "Unable to set dma callback\n");
1084                        goto error;
1085                }
1086                dma_disable_irq(drv_data->dma_channel);
1087        }
1088
1089        if (chip->pio_interrupt && !drv_data->irq_requested) {
1090                ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1091                        0, "BFIN_SPI", drv_data);
1092                if (ret) {
1093                        dev_err(&spi->dev, "Unable to register spi IRQ\n");
1094                        goto error;
1095                }
1096                drv_data->irq_requested = 1;
1097                /* we use write mode, spi irq has to be disabled here */
1098                disable_irq(drv_data->spi_irq);
1099        }
1100
1101        if (chip->chip_select_num >= MAX_CTRL_CS) {
1102                /* Only request on first setup */
1103                if (spi_get_ctldata(spi) == NULL) {
1104                        ret = gpio_request(chip->cs_gpio, spi->modalias);
1105                        if (ret) {
1106                                dev_err(&spi->dev, "gpio_request() error\n");
1107                                goto pin_error;
1108                        }
1109                        gpio_direction_output(chip->cs_gpio, 1);
1110                }
1111        }
1112
1113        dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1114                        spi->modalias, spi->bits_per_word, chip->enable_dma);
1115        dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1116                        chip->ctl_reg, chip->flag);
1117
1118        spi_set_ctldata(spi, chip);
1119
1120        dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1121        if (chip->chip_select_num < MAX_CTRL_CS) {
1122                ret = peripheral_request(ssel[spi->master->bus_num]
1123                                         [chip->chip_select_num-1], spi->modalias);
1124                if (ret) {
1125                        dev_err(&spi->dev, "peripheral_request() error\n");
1126                        goto pin_error;
1127                }
1128        }
1129
1130        bfin_spi_cs_enable(drv_data, chip);
1131        bfin_spi_cs_deactive(drv_data, chip);
1132
1133        return 0;
1134
1135 pin_error:
1136        if (chip->chip_select_num >= MAX_CTRL_CS)
1137                gpio_free(chip->cs_gpio);
1138        else
1139                peripheral_free(ssel[spi->master->bus_num]
1140                        [chip->chip_select_num - 1]);
1141 error:
1142        if (chip) {
1143                if (drv_data->dma_requested)
1144                        free_dma(drv_data->dma_channel);
1145                drv_data->dma_requested = 0;
1146
1147                kfree(chip);
1148                /* prevent free 'chip' twice */
1149                spi_set_ctldata(spi, NULL);
1150        }
1151
1152        return ret;
1153}
1154
1155/*
1156 * callback for spi framework.
1157 * clean driver specific data
1158 */
1159static void bfin_spi_cleanup(struct spi_device *spi)
1160{
1161        struct bfin_spi_slave_data *chip = spi_get_ctldata(spi);
1162        struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
1163
1164        if (!chip)
1165                return;
1166
1167        if (chip->chip_select_num < MAX_CTRL_CS) {
1168                peripheral_free(ssel[spi->master->bus_num]
1169                                        [chip->chip_select_num-1]);
1170                bfin_spi_cs_disable(drv_data, chip);
1171        } else
1172                gpio_free(chip->cs_gpio);
1173
1174        kfree(chip);
1175        /* prevent free 'chip' twice */
1176        spi_set_ctldata(spi, NULL);
1177}
1178
1179static int bfin_spi_init_queue(struct bfin_spi_master_data *drv_data)
1180{
1181        INIT_LIST_HEAD(&drv_data->queue);
1182        spin_lock_init(&drv_data->lock);
1183
1184        drv_data->running = false;
1185        drv_data->busy = 0;
1186
1187        /* init transfer tasklet */
1188        tasklet_init(&drv_data->pump_transfers,
1189                     bfin_spi_pump_transfers, (unsigned long)drv_data);
1190
1191        /* init messages workqueue */
1192        INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1193        drv_data->workqueue = create_singlethread_workqueue(
1194                                dev_name(drv_data->master->dev.parent));
1195        if (drv_data->workqueue == NULL)
1196                return -EBUSY;
1197
1198        return 0;
1199}
1200
1201static int bfin_spi_start_queue(struct bfin_spi_master_data *drv_data)
1202{
1203        unsigned long flags;
1204
1205        spin_lock_irqsave(&drv_data->lock, flags);
1206
1207        if (drv_data->running || drv_data->busy) {
1208                spin_unlock_irqrestore(&drv_data->lock, flags);
1209                return -EBUSY;
1210        }
1211
1212        drv_data->running = true;
1213        drv_data->cur_msg = NULL;
1214        drv_data->cur_transfer = NULL;
1215        drv_data->cur_chip = NULL;
1216        spin_unlock_irqrestore(&drv_data->lock, flags);
1217
1218        queue_work(drv_data->workqueue, &drv_data->pump_messages);
1219
1220        return 0;
1221}
1222
1223static int bfin_spi_stop_queue(struct bfin_spi_master_data *drv_data)
1224{
1225        unsigned long flags;
1226        unsigned limit = 500;
1227        int status = 0;
1228
1229        spin_lock_irqsave(&drv_data->lock, flags);
1230
1231        /*
1232         * This is a bit lame, but is optimized for the common execution path.
1233         * A wait_queue on the drv_data->busy could be used, but then the common
1234         * execution path (pump_messages) would be required to call wake_up or
1235         * friends on every SPI message. Do this instead
1236         */
1237        drv_data->running = false;
1238        while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) {
1239                spin_unlock_irqrestore(&drv_data->lock, flags);
1240                msleep(10);
1241                spin_lock_irqsave(&drv_data->lock, flags);
1242        }
1243
1244        if (!list_empty(&drv_data->queue) || drv_data->busy)
1245                status = -EBUSY;
1246
1247        spin_unlock_irqrestore(&drv_data->lock, flags);
1248
1249        return status;
1250}
1251
1252static int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data)
1253{
1254        int status;
1255
1256        status = bfin_spi_stop_queue(drv_data);
1257        if (status != 0)
1258                return status;
1259
1260        destroy_workqueue(drv_data->workqueue);
1261
1262        return 0;
1263}
1264
1265static int bfin_spi_probe(struct platform_device *pdev)
1266{
1267        struct device *dev = &pdev->dev;
1268        struct bfin5xx_spi_master *platform_info;
1269        struct spi_master *master;
1270        struct bfin_spi_master_data *drv_data;
1271        struct resource *res;
1272        int status = 0;
1273
1274        platform_info = dev->platform_data;
1275
1276        /* Allocate master with space for drv_data */
1277        master = spi_alloc_master(dev, sizeof(*drv_data));
1278        if (!master) {
1279                dev_err(&pdev->dev, "can not alloc spi_master\n");
1280                return -ENOMEM;
1281        }
1282
1283        drv_data = spi_master_get_devdata(master);
1284        drv_data->master = master;
1285        drv_data->master_info = platform_info;
1286        drv_data->pdev = pdev;
1287        drv_data->pin_req = platform_info->pin_req;
1288
1289        /* the spi->mode bits supported by this driver: */
1290        master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1291        master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1292        master->bus_num = pdev->id;
1293        master->num_chipselect = platform_info->num_chipselect;
1294        master->cleanup = bfin_spi_cleanup;
1295        master->setup = bfin_spi_setup;
1296        master->transfer = bfin_spi_transfer;
1297
1298        /* Find and map our resources */
1299        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1300        if (res == NULL) {
1301                dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1302                status = -ENOENT;
1303                goto out_error_get_res;
1304        }
1305
1306        drv_data->regs = ioremap(res->start, resource_size(res));
1307        if (drv_data->regs == NULL) {
1308                dev_err(dev, "Cannot map IO\n");
1309                status = -ENXIO;
1310                goto out_error_ioremap;
1311        }
1312
1313        res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1314        if (res == NULL) {
1315                dev_err(dev, "No DMA channel specified\n");
1316                status = -ENOENT;
1317                goto out_error_free_io;
1318        }
1319        drv_data->dma_channel = res->start;
1320
1321        drv_data->spi_irq = platform_get_irq(pdev, 0);
1322        if (drv_data->spi_irq < 0) {
1323                dev_err(dev, "No spi pio irq specified\n");
1324                status = -ENOENT;
1325                goto out_error_free_io;
1326        }
1327
1328        /* Initial and start queue */
1329        status = bfin_spi_init_queue(drv_data);
1330        if (status != 0) {
1331                dev_err(dev, "problem initializing queue\n");
1332                goto out_error_queue_alloc;
1333        }
1334
1335        status = bfin_spi_start_queue(drv_data);
1336        if (status != 0) {
1337                dev_err(dev, "problem starting queue\n");
1338                goto out_error_queue_alloc;
1339        }
1340
1341        status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1342        if (status != 0) {
1343                dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1344                goto out_error_queue_alloc;
1345        }
1346
1347        /* Reset SPI registers. If these registers were used by the boot loader,
1348         * the sky may fall on your head if you enable the dma controller.
1349         */
1350        bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
1351        bfin_write(&drv_data->regs->flg, 0xFF00);
1352
1353        /* Register with the SPI framework */
1354        platform_set_drvdata(pdev, drv_data);
1355        status = spi_register_master(master);
1356        if (status != 0) {
1357                dev_err(dev, "problem registering spi master\n");
1358                goto out_error_queue_alloc;
1359        }
1360
1361        dev_info(dev, "%s, Version %s, regs@%p, dma channel@%d\n",
1362                DRV_DESC, DRV_VERSION, drv_data->regs,
1363                drv_data->dma_channel);
1364        return status;
1365
1366out_error_queue_alloc:
1367        bfin_spi_destroy_queue(drv_data);
1368out_error_free_io:
1369        iounmap(drv_data->regs);
1370out_error_ioremap:
1371out_error_get_res:
1372        spi_master_put(master);
1373
1374        return status;
1375}
1376
1377/* stop hardware and remove the driver */
1378static int bfin_spi_remove(struct platform_device *pdev)
1379{
1380        struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1381        int status = 0;
1382
1383        if (!drv_data)
1384                return 0;
1385
1386        /* Remove the queue */
1387        status = bfin_spi_destroy_queue(drv_data);
1388        if (status != 0)
1389                return status;
1390
1391        /* Disable the SSP at the peripheral and SOC level */
1392        bfin_spi_disable(drv_data);
1393
1394        /* Release DMA */
1395        if (drv_data->master_info->enable_dma) {
1396                if (dma_channel_active(drv_data->dma_channel))
1397                        free_dma(drv_data->dma_channel);
1398        }
1399
1400        if (drv_data->irq_requested) {
1401                free_irq(drv_data->spi_irq, drv_data);
1402                drv_data->irq_requested = 0;
1403        }
1404
1405        /* Disconnect from the SPI framework */
1406        spi_unregister_master(drv_data->master);
1407
1408        peripheral_free_list(drv_data->pin_req);
1409
1410        return 0;
1411}
1412
1413#ifdef CONFIG_PM
1414static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1415{
1416        struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1417        int status = 0;
1418
1419        status = bfin_spi_stop_queue(drv_data);
1420        if (status != 0)
1421                return status;
1422
1423        drv_data->ctrl_reg = bfin_read(&drv_data->regs->ctl);
1424        drv_data->flag_reg = bfin_read(&drv_data->regs->flg);
1425
1426        /*
1427         * reset SPI_CTL and SPI_FLG registers
1428         */
1429        bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
1430        bfin_write(&drv_data->regs->flg, 0xFF00);
1431
1432        return 0;
1433}
1434
1435static int bfin_spi_resume(struct platform_device *pdev)
1436{
1437        struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1438        int status = 0;
1439
1440        bfin_write(&drv_data->regs->ctl, drv_data->ctrl_reg);
1441        bfin_write(&drv_data->regs->flg, drv_data->flag_reg);
1442
1443        /* Start the queue running */
1444        status = bfin_spi_start_queue(drv_data);
1445        if (status != 0) {
1446                dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1447                return status;
1448        }
1449
1450        return 0;
1451}
1452#else
1453#define bfin_spi_suspend NULL
1454#define bfin_spi_resume NULL
1455#endif                          /* CONFIG_PM */
1456
1457MODULE_ALIAS("platform:bfin-spi");
1458static struct platform_driver bfin_spi_driver = {
1459        .driver = {
1460                .name   = DRV_NAME,
1461                .owner  = THIS_MODULE,
1462        },
1463        .suspend        = bfin_spi_suspend,
1464        .resume         = bfin_spi_resume,
1465        .remove         = bfin_spi_remove,
1466};
1467
1468static int __init bfin_spi_init(void)
1469{
1470        return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1471}
1472subsys_initcall(bfin_spi_init);
1473
1474static void __exit bfin_spi_exit(void)
1475{
1476        platform_driver_unregister(&bfin_spi_driver);
1477}
1478module_exit(bfin_spi_exit);
1479
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