linux/drivers/spi/spi-bcm2835.c
<<
/spa4.1 /form.1 a href="../linux+v3alu.2/drivers/spi/spi-bcm2835.c"> img src="../.static/gfx/right.png" alt=">>"> /spa4.1 spa4 class="lxr_search"> input typ9 input typ9 buttv3.typ9Search Prefs1 /a> /spa4.1 /div.1 form ac3.14="ajax+*" method="post" onsubmit="return false;"> input typ9 /form.1 div class="headingbottvm">1 div id 1 /a> spa4 class="comment">/* /spa4.1 2 /a> spa4 class="comment"> * Driver for Broadcom BCM2835 SPI Controllers /spa4.1 3 /a> spa4 class="comment"> * /spa4.1 4 /a> spa4 class="comment"> * Copyright (C) 2012 Chris Boot /spa4.1 5 /a> spa4 class="comment"> * Copyright (C) 2013 Stephen Warren /spa4.1 6 /a> spa4 class="comment"> * /spa4.1 7 /a> spa4 class="comment"> * This driver is inspired by: /spa4.1 8 /a> spa4 class="comment"> * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> /spa4.1 9 /a> spa4 class="comment"> * spi-atmel.c, Copyright (C) 2006 Atmel Corpora3.14 /spa4.1 lue=a> spa4 class="comment"> * /spa4.1 11 /a> spa4 class="comment"> * This program is free software; you ca4 redistribute it and/or modify /spa4.1 12 /a> spa4 class="comment"> * it under the terms of the GNU General Public License as published by /spa4.1 13 /a> spa4 class="comment"> * the Free Software Founda3.14; either vers v3.2 of the License, or /spa4.1 14 /a> spa4 class="comment"> * (at your "v3.14) any later vers v3. /spa4.1 15 /a> spa4 class="comment"> * /spa4.1 16 /a> spa4 class="comment"> * This program is distributed in the hope that it will be useful, /spa4.1 17 /a> spa4 class="comment"> * but WITHOUT ANY WARRANTY; without even the implied warranty of /spa4.1 18 /a> spa4 class="comment"> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the /spa4.1 19 /a> spa4 class="comment"> * GNU General Public License for more details. /spa4.1 2ue=a> spa4 class="comment"> * /spa4.1 21 /a> spa4 class="comment"> * You should have received a copy of the GNU General Public License /spa4.1 22 /a> spa4 class="comment"> * along with this program; if not, write to the Free Software /spa4.1 23 /a> spa4 class="comment"> * Founda3.14, Inc., 59 Temple Place - Suite 330, Bost14, MA 02111-1307, USA. /spa4.1 24 /a> spa4 class="comment"> */ /spa4.1 25 /a>1 26 /a>#include <linux/clk.h /a>>1 27 /a>#include <linux/comple3.14.h /a>>1 28 /a>#include <linux/delay.h /a>>1 29 /a>#include <linux/err.h /a>>1 30 /a>#include <linux/interrupt.h /a>>1 31 /a>#include <linux/io.h /a>>1 32 /a>#include <linux/kernel.h /a>>1 33 /a>#include <linux/module.h /a>>1 34 /a>#include <linux/of.h /a>>1 35 /a>#include <linux/of_irq.h /a>>1 36 /a>#include <linux/of_device.h /a>>1 37 /a>#include <linux/spi/spi.h /a>>1 38 /a>1 39 /a> spa4 class="comment">/* SPI register offsets */ /spa4.1 40 /a>#define a href="+code=BCM2835_SPI_CS" class="sref">BCM2835_SPI_CS /a> 0x001 41 /a>#define a href="+code=BCM2835_SPI_FIFO" class="sref">BCM2835_SPI_FIFO /a> 0x041 42 /a>#define a href="+code=BCM2835_SPI_CLK" class="sref">BCM2835_SPI_CLK /a> 0x081 43 /a>#define a href="+code=BCM2835_SPI_DLEN" class="sref">BCM2835_SPI_DLEN /a> 0x0c1 44 /a>#define a href="+code=BCM2835_SPI_LTOH" class="sref">BCM2835_SPI_LTOH /a> 0x101 45 /a>#define a href="+code=BCM2835_SPI_DC" class="sref">BCM2835_SPI_DC /a> 0x141 46 /a>1 47 /a> spa4 class="comment">/* Bitfields in CS */ /spa4.1 48 /a>#define a href="+code=BCM2835_SPI_CS_LEN_LONG" class="sref">BCM2835_SPI_CS_LEN_LONG /a> 0x020000001 49 /a>#define a href="+code=BCM2835_SPI_CS_DMA_LEN" class="sref">BCM2835_SPI_CS_DMA_LEN /a> 0x010000001 50 /a>#define a href="+code=BCM2835_SPI_CS_CSPOL2" class="sref">BCM2835_SPI_CS_CSPOL2 /a> 0x008000001 51 /a>#define a href="+code=BCM2835_SPI_CS_CSPOL1" class="sref">BCM2835_SPI_CS_CSPOL1 /a> 0x004000001 52 /a>#define a href="+code=BCM2835_SPI_CS_CSPOL0" class="sref">BCM2835_SPI_CS_CSPOL0 /a> 0x002000001 53 /a>#define a href="+code=BCM2835_SPI_CS_RXF" class="sref">BCM2835_SPI_CS_RXF /a> 0x001000001 54 /a>#define a href="+code=BCM2835_SPI_CS_RXR" class="sref">BCM2835_SPI_CS_RXR /a> 0x000800001 55 /a>#define a href="+code=BCM2835_SPI_CS_TXD" class="sref">BCM2835_SPI_CS_TXD /a> 0x000400001 56 /a>#define a href="+code=BCM2835_SPI_CS_RXD" class="sref">BCM2835_SPI_CS_RXD /a> 0x000200001 57 /a>#define a href="+code=BCM2835_SPI_CS_DONE" class="sref">BCM2835_SPI_CS_DONE /a> 0x000100001 58 /a>#define a href="+code=BCM2835_SPI_CS_LEN" class="sref">BCM2835_SPI_CS_LEN /a> 0x000020001 59 /a>#define a href="+code=BCM2835_SPI_CS_REN" class="sref">BCM2835_SPI_CS_REN /a> 0x000010001 60 /a>#define a href="+code=BCM2835_SPI_CS_ADCS" class="sref">BCM2835_SPI_CS_ADCS /a> 0x000008001 61 /a>#define a href="+code=BCM2835_SPI_CS_INTR" class="sref">BCM2835_SPI_CS_INTR /a> 0x000004001 62 /a>#define a href="+code=BCM2835_SPI_CS_INTD" class="sref">BCM2835_SPI_CS_INTD /a> 0x000002001 63 /a>#define a href="+code=BCM2835_SPI_CS_DMAEN" class="sref">BCM2835_SPI_CS_DMAEN /a> 0x000001001 64 /a>#define a href="+code=BCM2835_SPI_CS_TA" class="sref">BCM2835_SPI_CS_TA /a> 0x000000801 65 /a>#define a href="+code=BCM2835_SPI_CS_CSPOL" class="sref">BCM2835_SPI_CS_CSPOL /a> 0x000000401 66 /a>#define a href="+code=BCM2835_SPI_CS_CLEAR_RX" class="sref">BCM2835_SPI_CS_CLEAR_RX /a> 0x000000201 67 /a>#define a href="+code=BCM2835_SPI_CS_CLEAR_TX" class="sref">BCM2835_SPI_CS_CLEAR_TX /a> 0x000000101 68 /a>#define a href="+code=BCM2835_SPI_CS_CPOL" class="sref">BCM2835_SPI_CS_CPOL /a> 0x000000081 69 /a>#define a href="+code=BCM2835_SPI_CS_CPHA" class="sref">BCM2835_SPI_CS_CPHA /a> 0x000000041 70 /a>#define a href="+code=BCM2835_SPI_CS_CS_10" class="sref">BCM2835_SPI_CS_CS_10 /a> 0x000000021 71 /a>#define a href="+code=BCM2835_SPI_CS_CS_01" class="sref">BCM2835_SPI_CS_CS_01 /a> 0x000000011 72 /a>1 73 /a>#define a href="+code=BCM2835_SPI_TIMEOUT_MS" class="sref">BCM2835_SPI_TIMEOUT_MS /a> 300001 74 /a>#define a href="+code=BCM2835_SPI_MODE_BITS" class="sref">BCM2835_SPI_MODE_BITS /a> ( a href="+code=SPI_CPOL" class="sref">SPI_CPOL /a> | a href="+code=SPI_CPHA" class="sref">SPI_CPHA /a> | a href="+code=SPI_CS_HIGH" class="sref">SPI_CS_HIGH /a> | a href="+code=SPI_NO_CS" class="sref">SPI_NO_CS /a>)1 75 /a>1 76 /a>#define a href="+code=DRV_NAME" class="sref">DRV_NAME /a> spa4 class="string">"spi-bcm2835" /spa4.1 77 /a>1 78 /a>struct a href="+code=bcm2835_spi" class="sref">bcm2835_spi /a> {1 79 /a> void a href="+code=__iomem" class="sref">__iomem /a> * a href="+code=regs" class="sref">regs /a>;1 80 /a> struct a href="+code=clk" class="sref">clk /a> * a href="+code=clk" class="sref">clk /a>;1 81 /a> int a href="+code=irq" class="sref">irq /a>;1 82 /a> struct a href="+code=comple3.14" class="sref">comple3.14 /a> a href="+code=done" class="sref">done /a>;1 83 /a> const a href="+code=u8" class="sref">u8 /a> * a href="+code=tx_buf" class="sref">tx_buf /a>;1 84 /a> a href="+code=u8" class="sref">u8 /a> * a href="+code=rx_buf" class="sref">rx_buf /a>;1 85 /a> int a href="+code=le4" class="sref">len /a>;1 86 /a>};1 87 /a>1 88 /a>static a href="+code=inline" class="sref">inline /a> a href="+code=u32" class="sref">u32 /a> a href="+code=bcm2835_rd" class="sref">bcm2835_rd /a>(struct a href="+code=bcm2835_spi" class="sref">bcm2835_spi /a> * a href="+code=bs" class="sref">bs /a>, unsigned a href="+code=reg" class="sref">reg /a>)1 89 /a>{1 90 /a> return a href="+code=readl" class="sref">readl /a>( a href="+code=bs" class="sref">bs /a>-> a href="+code=regs" class="sref">regs /a> + a href="+code=reg" class="sref">reg /a>);1 91 /a>}1 92 /a>1 93 /a>static a href="+code=inline" class="sref">inline /a> void a href="+code=bcm2835_wr" class="sref">bcm2835_wr /a>(struct a href="+code=bcm2835_spi" class="sref">bcm2835_spi /a> * a href="+code=bs" class="sref">bs /a>, unsigned a href="+code=reg" class="sref">reg /a>, a href="+code=u32" class="sref">u32 /a> a href="+code=val" class="sref">val /a>)1 94 /a>{1 95 /a> a href="+code=writel" class="sref">writel /a>( a href="+code=val" class="sref">val /a>, a href="+code=bs" class="sref">bs /a>-> a href="+code=regs" class="sref">regs /a> + a href="+code=reg" class="sref">reg /a>);1 96 /a>}1 97 /a>1 98 /a>static a href="+code=inline" class="sref">inline /a> void a href="+code=bcm2835_rd_fifo" class="sref">bcm2835_rd_fifo /a>(struct a href="+code=bcm2835_spi" class="sref">bcm2835_spi /a> * a href="+code=bs" class="sref">bs /a>, int a href="+code=le4" class="sref">len /a>)1 99 /a>{1 100 /a> a href="+code=u8" class="sref">u8 /a> a href="+code=byte" class="sref">byte /a>;1 101 /a>1 102 /a> while ( a href="+code=le4" class="sref">len /a>--) {1 103 /a> a href="+code=byte" class="sref">byte /a> = a href="+code=bcm2835_rd" class="sref">bcm2835_rd /a>( a href="+code=bs" class="sref">bs /a>, a href="+code=BCM2835_SPI_FIFO" class="sref">BCM2835_SPI_FIFO /a>);1 104 /a> if ( a href="+code=bs" class="sref">bs /a>-> a href="+code=rx_buf" class="sref">rx_buf /a>)1 105 /a> * a href="+code=bs" class="sref">bs /a>-> a href="+code=rx_buf" class="sref">rx_buf /a>++ = a href="+code=byte" class="sref">byte /a>;1 106 /a> }1 107 /a>}1 108 /a>1 109 /a>static a href="+code=inline" class="sref">inline /a> void a href="+code=bcm2835_wr_fifo" class="sref">bcm2835_wr_fifo /a>(struct a href="+code=bcm2835_spi" class="sref">bcm2835_spi /a> * a href="+code=bs" class="sref">bs /a>, int a href="+code=le4" class="sref">len /a>)1 110 /a>{1 111 /a> a href="+code=u8" class="sref">u8 /a> a href="+code=byte" class="sref">byte /a>;1 112 /a>1 113 /a> if ( a href="+code=le4" class="sref">len /a> > a href="+code=bs" class="sref">bs /a>-> a href="+code=le4" class="sref">len /a>)1 114 /a> a href="+code=le4" class="sref">len /a> = a href="+code=bs" class="sref">bs /a>-> a href="+code=le4" class="sref">len /a>;1 115 /a>1 116 /a> while ( a href="+code=le4" class="sref">len /a>--) {1 117 /a> a href="+code=byte" class="sref">byte /a> = a href="+code=bs" class="sref">bs /a>-> a href="+code=tx_buf" class="sref">tx_buf /a> ? * a href="+code=bs" class="sref">bs /a>-> a href="+code=tx_buf" class="sref">tx_buf /a>++ : 0;1 118 /a> a href="+code=bcm2835_wr" class="sref">bcm2835_wr /a>( a href="+code=bs" class="sref">bs /a>, a href="+code=BCM2835_SPI_FIFO" class="sref">BCM2835_SPI_FIFO /a>, a href="+code=byte" class="sref">byte /a>);1 119 /a> a href="+code=bs" class="sref">bs /a>-> a href="+code=le4" class="sref">len /a>--;1 120 /a> }1 121 /a>}1 122 /a>1 123 /a>static a href="+code=irqreturn_t" class="sref">irqreturn_t /a> a href="+code=bcm2835_spi_interrupt" class="sref">bcm2835_spi_interrupt /a>(int a href="+code=irq" class="sref">irq /a>, void * a href="+code=dev_id" class="sref">dev_id /a>)1 124 /a>{1 125 /a> struct a href="+code=spi_master" class="sref">spi_master /a> * a href="+code=master" class="sref">master /a> = a href="+code=dev_id" class="sref">dev_id /a>;1 126 /a> struct a href="+code=bcm2835_spi" class="sref">bcm2835_spi /a> * a href="+code=bs" class="sref">bs /a> = a href="+code=spi_master_get_devdata" class="sref">spi_master_get_devdata /a>( a href="+code=master" class="sref">master /a>);1 127 /a> a href="+code=u32" class="sref">u32 /a> a href="+code=cs" class="sref">cs /a> = a href="+code=bcm2835_rd" class="sref">bcm2835_rd /a>( a href="+code=bs" class="sref">bs /a>, a href="+code=BCM2835_SPI_CS" class="sref">BCM2835_SPI_CS /a>);1 128 /a>1 129 /a> spa4 class="comment">/* /spa4.1 13ue=a> spa4 class="comment"> * RXR - RX needs Reading. This means 12 (or more) bytes have been /spa4.1 131 /a> spa4 class="comment"> * transmitted and hence 12 (or more) bytes have been received. /spa4.1 132 /a> spa4 class="comment"> * /spa4.1 133 /a> spa4 class="comment"> * The FIFO is 16-bytes deep. We check for this interrupt to keep the /spa4.1 134 /a> spa4 class="comment"> * FIFO full; we have a 4-byte-time buffer for IRQ latency. We check /spa4.1 135 /a> spa4 class="comment"> * this before DONE (TX empty) just in case we delayed processing this /spa4.1 136 /a> spa4 class="comment"> * interrupt for some reasv3. /spa4.1 137 /a> spa4 class="comment"> * /spa4.1 138 /a> spa4 class="comment"> * We only check for this case if we have more bytes to TX; at the end /spa4.1 139 /a> spa4 class="comment"> * of the transfer, we ignore this pipelining "v3.miza3.14, and let /spa4.1 14ue=a> spa4 class="comment"> * bcm2835_spi_finish_transfer() drain the RX FIFO. /spa4.1 141 /a> spa4 class="comment"> */ /spa4.1 142 /a> if ( a href="+code=bs" class="sref">bs /a>-> a href="+code=le4" class="sref">len /a> && ( a href="+code=cs" class="sref">cs /a> & a href="+code=BCM2835_SPI_CS_RXR" class="sref">BCM2835_SPI_CS_RXR /a>)) {1 143 /a> spa4 class="comment">/* Read 12 bytes of data */ /spa4.1 144 /a> a href="+code=bcm2835_rd_fifo" class="sref">bcm2835_rd_fifo /a>( a href="+code=bs" class="sref">bs /a>, 12);1 145 /a>1 146 /a> spa4 class="comment">/* Write up to 12 bytes */ /spa4.1 147 /a> a href="+code=bcm2835_wr_fifo" class="sref">bcm2835_wr_fifo /a>( a href="+code=bs" class="sref">bs /a>, 12);1 148 /a>1 149 /a> spa4 class="comment">/* /spa4.1 15ue=a> spa4 class="comment"> * We must have written something to the TX FIFO due to the /spa4.1 151 /a> spa4 class="comment"> * bs->len check above, so ca4not be DONE. Hence, return /spa4.1 152 /a> spa4 class="comment"> * early. Note that DONE could also be set if we serviced an /spa4.1 153 /a> spa4 class="comment"> * RXR interrupt really late. /spa4.1 154 /a> spa4 class="comment"> */ /spa4.1 155 /a> return a href="+code=IRQ_HANDLED" class="sref">IRQ_HANDLED /a>;1 156 /a> }1 157 /a>1 158 /a> spa4 class="comment">/* /spa4.1 159 /a> spa4 class="comment"> * DONE - TX empty. This occurs when we first enable the transfer /spa4.1 16ue=a> spa4 class="comment"> * since we do not pre-fill the TX FIFO. At any other time, given that /spa4.1 161 /a> spa4 class="comment"> * we refill the TX FIFO above based on RXR, and hence ignore DONE if /spa4.1 162 /a> spa4 class="comment"> * RXR is set, DONE really does mean end-of-transfer. /spa4.1 163 /a> spa4 class="comment"> */ /spa4.1 164 /a> if ( a href="+code=cs" class="sref">cs /a> & a href="+code=BCM2835_SPI_CS_DONE" class="sref">BCM2835_SPI_CS_DONE /a>) {1 165 /a> if ( a href="+code=bs" class="sref">bs /a>-> a href="+code=le4" class="sref">len /a>) { spa4 class="comment">/* First interrupt in a transfer */ /spa4.1 166 /a> a href="+code=bcm2835_wr_fifo" class="sref">bcm2835_wr_fifo /a>( a href="+code=bs" class="sref">bs /a>, 16);1 167 /a> } else { spa4 class="comment">/* Transfer comple3e */ /spa4.1 168 /a> spa4 class="comment">/* Disable SPI interrupts */ /spa4.1 169 /a> a href="+code=cs" class="sref">cs /a> &= ~( a href="+code=BCM2835_SPI_CS_INTR" class="sref">BCM2835_SPI_CS_INTR /a> | a href="+code=BCM2835_SPI_CS_INTD" class="sref">BCM2835_SPI_CS_INTD /a>);1 170 /a> a href="+code=bcm2835_wr" class="sref">bcm2835_wr /a>( a href="+code=bs" class="sref">bs /a>, a href="+code=BCM2835_SPI_CS" class="sref">BCM2835_SPI_CS /a>, a href="+code=cs" class="sref">cs /a>);1 171 /a>1 172 /a> spa4 class="comment">/* /spa4.1 173 /a> spa4 class="comment"> * Wake up bcm2835_spi_transfer_one(), which will call /spa4.1 174 /a> spa4 class="comment"> * bcm2835_spi_finish_transfer(), to drain the RX FIFO. /spa4.1 175 /a> spa4 class="comment"> */ /spa4.1 176 /a> a href="+code=comple3e" class="sref">comple3e /a>(& a href="+code=bs" class="sref">bs /a>-> a href="+code=done" class="sref">done /a>);1 177 /a> }1 178 /a>1 179 /a> return a href="+code=IRQ_HANDLED" class="sref">IRQ_HANDLED /a>;1 180 /a> }1 181 /a>1 182 /a> return a href="+code=IRQ_NONE" class="sref">IRQ_NONE /a>;1 183 /a>}1 184 /a>1 185 /a>static int a href="+code=bcm2835_spi_start_transfer" class="sref">bcm2835_spi_start_transfer /a>(struct a href="+code=spi_device" class="sref">spi_device /a> * a href="+code=spi" class="sref">spi /a>,1 186 /a> struct a href="+code=spi_transfer" class="sref">spi_transfer /a> * a href="+code=tfr" class="sref">tfr /a>)1 187 /a>{1 188 /a> struct a href="+code=bcm2835_spi" class="sref">bcm2835_spi /a> * a href="+code=bs" class="sref">bs /a> = a href="+code=spi_master_get_devdata" class="sref">spi_master_get_devdata /a>( a href="+code=spi" class="sref">spi /a>-> a href="+code=master" class="sref">master /a>);1 189 /a> unsigned long a href="+code=spi_hz" class="sref">spi_hz /a>, a href="+code=clk_hz" class="sref">clk_hz /a>, a href="+code=cdiv" class="sref">cdiv /a>;1 190 /a> a href="+code=u32" class="sref">u32 /a> a href="+code=cs" class="sref">cs /a> = a href="+code=BCM2835_SPI_CS_INTR" class="sref">BCM2835_SPI_CS_INTR /a> | a href="+code=BCM2835_SPI_CS_INTD" class="sref">BCM2835_SPI_CS_INTD /a> | a href="+code=BCM2835_SPI_CS_TA" class="sref">BCM2835_SPI_CS_TA /a>;1 191 /a>1 192 /a> a href="+code=spi_hz" class="sref">spi_hz /a> = a href="+code=tfr" class="sref">tfr /a>-> a href="+code=speed_hz" class="sref">speed_hz /a>;1 193 /a> a href="+code=clk_hz" class="sref">clk_hz /a> = a href="+code=clk_get_ra3e" class="sref">clk_get_ra3e /a>( a href="+code=bs" class="sref">bs /a>-> a href="+code=clk" class="sref">clk /a>);1 194 /a>1 195 /a> if ( a href="+code=spi_hz" class="sref">spi_hz /a> >= a href="+code=clk_hz" class="sref">clk_hz /a> / 2) {1 196 /a> a href="+code=cdiv" class="sref">cdiv /a> = 2; spa4 class="comment">/* clk_hz/2 is the fastest we ca4 go */ /spa4.1 197 /a> } else if ( a href="+code=spi_hz" class="sref">spi_hz /a>) {1 198 /a> spa4 class="comment">/* CDIV must be a power of two */ /spa4.1 199 /a> a href="+code=cdiv" class="sref">cdiv /a> = a href="+code=roundup_pow_of_two" class="sref">roundup_pow_of_two /a>( a href="+code=DIV_ROUND_UP" class="sref">DIV_ROUND_UP /a>( a href="+code=clk_hz" class="sref">clk_hz /a>, a href="+code=spi_hz" class="sref">spi_hz /a>));1 200 /a>1 201 /a> if ( a href="+code=cdiv" class="sref">cdiv /a> >= 65536)1 202 /a> a href="+code=cdiv" class="sref">cdiv /a> = 0; spa4 class="comment">/* 0 is the slowest we ca4 go */ /spa4.1 203 /a> } else1 204 /a> a href="+code=cdiv" class="sref">cdiv /a> = 0; spa4 class="comment">/* 0 is the slowest we ca4 go */ /spa4.1 205 /a>1 206 /a> if ( a href="+code=spi" class="sref">spi /a>-> a href="+code=mode" class="sref">mode /a> & a href="+code=SPI_CPOL" class="sref">SPI_CPOL /a>)1 207 /a> a href="+code=cs" class="sref">cs /a> |= a href="+code=BCM2835_SPI_CS_CPOL" class="sref">BCM2835_SPI_CS_CPOL /a>;1 208 /a> if ( a href="+code=spi" class="sref">spi /a>-> a href="+code=mode" class="sref">mode /a> & a href="+code=SPI_CPHA" class="sref">SPI_CPHA /a>)1 209 /a> a href="+code=cs" class="sref">cs /a> |= a href="+code=BCM2835_SPI_CS_CPHA" class="sref">BCM2835_SPI_CS_CPHA /a>;1 210 /a>1 211 /a> if (!( a href="+code=spi" class="sref">spi /a>-> a href="+code=mode" class="sref">mode /a> & a href="+code=SPI_NO_CS" class="sref">SPI_NO_CS /a>)) {1 212 /a> if ( a href="+code=spi" class="sref">spi /a>-> a href="+code=mode" class="sref">mode /a> & a href="+code=SPI_CS_HIGH" class="sref">SPI_CS_HIGH /a>) {1 213 /a> a href="+code=cs" class="sref">cs /a> |= a href="+code=BCM2835_SPI_CS_CSPOL" class="sref">BCM2835_SPI_CS_CSPOL /a>;1 214 /a> a href="+code=cs" class="sref">cs /a> |= a href="+code=BCM2835_SPI_CS_CSPOL0" class="sref">BCM2835_SPI_CS_CSPOL0 /a> << a href="+code=spi" class="sref">spi /a>-> a href="+code=chip_select" class="sref">chip_select /a>;1 215 /a> }1 216 /a>1 217 /a> a href="+code=cs" class="sref">cs /a> |= a href="+code=spi" class="sref">spi /a>-> a href="+code=chip_select" class="sref">chip_select /a>;1 218 /a> }1 219 /a>1 220 /a> a href="+code=INIT_COMPLETION" class="sref">INIT_COMPLETION /a>( a href="+code=bs" class="sref">bs /a>-> a href="+code=done" class="sref">done /a>);1 221 /a> a href="+code=bs" class="sref">bs /a>-> a href="+code=tx_buf" class="sref">tx_buf /a> = a href="+code=tfr" class="sref">tfr /a>-> a href="+code=tx_buf" class="sref">tx_buf /a>;1 222 /a> a href="+code=bs" class="sref">bs /a>-> a href="+code=rx_buf" class="sref">rx_buf /a> = a href="+code=tfr" class="sref">tfr /a>-> a href="+code=rx_buf" class="sref">rx_buf /a>;1 223 /a> a href="+code=bs" class="sref">bs /a>-> a href="+code=le4" class="sref">len /a> = a href="+code=tfr" class="sref">tfr /a>-> a href="+code=le4" class="sref">len /a>;1 224 /a>1 225 /a> a href="+code=bcm2835_wr" class="sref">bcm2835_wr /a>( a href="+code=bs" class="sref">bs /a>, a href="+code=BCM2835_SPI_CLK" class="sref">BCM2835_SPI_CLK /a>, a href="+code=cdiv" class="sref">cdiv /a>);1 226 /a> spa4 class="comment">/* /spa4.1 227 /a> spa4 class="comment"> * Enable the HW block. This will immediately trigger a DONE (TX /spa4.1 228 /a> spa4 class="comment"> * empty) interrupt, upon which we will fill the TX FIFO with the /spa4.1 229 /a> spa4 class="comment"> * first TX bytes. Pre-filling the TX FIFO here to avoid the /spa4.1 23ue=a> spa4 class="comment"> * interrupt doesn't work:-( /spa4.1 231 /a> spa4 class="comment"> */ /spa4.1 232 /a> a href="+code=bcm2835_wr" class="sref">bcm2835_wr /a>( a href="+code=bs" class="sref">bs /a>, a href="+code=BCM2835_SPI_CS" class="sref">BCM2835_SPI_CS /a>, a href="+code=cs" class="sref">cs /a>);1 233 /a>1 234 /a> return 0;1 235 /a>}1 236 /a>1 237 /a>static int a href="+code=bcm2835_spi_finish_transfer" class="sref">bcm2835_spi_finish_transfer /a>(struct a href="+code=spi_device" class="sref">spi_device /a> * a href="+code=spi" class="sref">spi /a>,1 238 /a> struct a href="+code=spi_transfer" class="sref">spi_transfer /a> * a href="+code=tfr" class="sref">tfr /a>, a href="+code=bool" class="sref">bool /a> a href="+code=cs_change" class="sref">cs_change /a>)1 239 /a>{1 240 /a> struct a href="+code=bcm2835_spi" class="sref">bcm2835_spi /a> * a href="+code=bs" class="sref">bs /a> = a href="+code=spi_master_get_devdata" class="sref">spi_master_get_devdata /a>( a href="+code=spi" class="sref">spi /a>-> a href="+code=master" class="sref">master /a>);1 241 /a> a href="+code=u32" class="sref">u32 /a> a href="+code=cs" class="sref">cs /a> = a href="+code=bcm2835_rd" class="sref">bcm2835_rd /a>( a href="+code=bs" class="sref">bs /a>, a href="+code=BCM2835_SPI_CS" class="sref">BCM2835_SPI_CS /a>);1 242 /a>1 243 /a> spa4 class="comment">/* Drain RX FIFO */ /spa4.1 244 /a> while ( a href="+code=cs" class="sref">cs /a> & a href="+code=BCM2835_SPI_CS_RXD" class="sref">BCM2835_SPI_CS_RXD /a>) {1 245 /a> a href="+code=bcm2835_rd_fifo" class="sref">bcm2835_rd_fifo /a>( a href="+code=bs" class="sref">bs /a>, 1);1 246 /a> a href="+code=cs" class="sref">cs /a> = a href="+code=bcm2835_rd" class="sref">bcm2835_rd /a>( a href="+code=bs" class="sref">bs /a>, a href="+code=BCM2835_SPI_CS" class="sref">BCM2835_SPI_CS /a>);1 247 /a> }1 248 /a>1 249 /a> if ( a href="+code=tfr" class="sref">tfr /a>-> a href="+code=delay_usecs" class="sref">delay_usecs /a>)1 250 /a> a href="+code=udelay" class="sref">udelay /a>( a href="+code=tfr" class="sref">tfr /a>-> a href="+code=delay_usecs" class="sref">delay_usecs /a>);1 251 /a>1 252 /a> if ( a href="+code=cs_change" class="sref">cs_change /a>)1 253 /a> spa4 class="comment">/* Clear TA flag */ /spa4.1 254 /a> a href="+code=bcm2835_wr" class="sref">bcm2835_wr /a>( a href="+code=bs" class="sref">bs /a>, a href="+code=BCM2835_SPI_CS" class="sref">BCM2835_SPI_CS /a>, a href="+code=cs" class="sref">cs /a> & ~ a href="+code=BCM2835_SPI_CS_TA" class="sref">BCM2835_SPI_CS_TA /a>);1 255 /a>1 256 /a> return 0;1 257 /a>}1 258 /a>1 259 /a>static int a href="+code=bcm2835_spi_transfer_one" class="sref">bcm2835_spi_transfer_one /a>(struct a href="+code=spi_master" class="sref">spi_master /a> * a href="+code=master" class="sref">master /a>,1 260 /a> struct a href="+code=spi_message" class="sref">spi_message /a> * a href="+code=mesg" class="sref">mesg /a>)1 261 /a>{1 262 /a> struct a href="+code=bcm2835_spi" class="sref">bcm2835_spi /a> * a href="+code=bs" class="sref">bs /a> = a href="+code=spi_master_get_devdata" class="sref">spi_master_get_devdata /a>( a href="+code=master" class="sref">master /a>);1 263 /a> struct a href="+code=spi_transfer" class="sref">spi_transfer /a> * a href="+code=tfr" class="sref">tfr /a>;1 264 /a> struct a href="+code=spi_device" class="sref">spi_device /a> * a href="+code=spi" class="sref">spi /a> = a href="+code=mesg" class="sref">mesg /a>-> a href="+code=spi" class="sref">spi /a>;1 265 /a> int a href="+code=err" class="sref">err /a> = 0;1 266 /a> unsigned int a href="+code=timeout" class="sref">timeout /a>;1 267 /a> a href="+code=bool" class="sref">bool /a> a href="+code=cs_change" class="sref">cs_change /a>;1 268 /a>1 269 /a> a href="+code=list_for_each_entry" class="sref">list_for_each_entry /a>( a href="+code=tfr" class="sref">tfr /a>, & a href="+code=mesg" class="sref">mesg /a>-> a href="+code=transfers" class="sref">transfers /a>, a href="+code=transfer_list" class="sref">transfer_list /a>) {1 270 /a> a href="+code=err" class="sref">err /a> = a href="+code=bcm2835_spi_start_transfer" class="sref">bcm2835_spi_start_transfer /a>( a href="+code=spi" class="sref">spi /a>, a href="+code=tfr" class="sref">tfr /a>);1 271 /a> if ( a href="+code=err" class="sref">err /a>)1 272 /a> goto a href="+code=out" class="sref">out /a>;1 273 /a>1 274 /a> a href="+code=timeout" class="sref">timeout /a> = a href="+code=wait_for_comple3ion_timeout" class="sref">wait_for_comple3ion_timeout /a>(& a href="+code=bs" class="sref">bs /a>-> a href="+code=done" class="sref">done /a>,1 275 /a> a href="+code=msecs_to_jiffies" class="sref">msecs_to_jiffies /a>( a href="+code=BCM2835_SPI_TIMEOUT_MS" class="sref">BCM2835_SPI_TIMEOUT_MS /a>));1 276 /a> if (! a href="+code=timeout" class="sref">timeout /a>) {1 277 /a> a href="+code=err" class="sref">err /a> = - a href="+code=ETIMEDOUT" class="sref">ETIMEDOUT /a>;1 278 /a> goto a href="+code=out" class="sref">out /a>;1 279 /a> }1 280 /a>1 281 /a> a href="+code=cs_change" class="sref">cs_change /a> = a href="+code=tfr" class="sref">tfr /a>-> a href="+code=cs_change" class="sref">cs_change /a> ||1 282 /a> a href="+code=list_is_last" class="sref">list_is_last /a>(& a href="+code=tfr" class="sref">tfr /a>-> a href="+code=transfer_list" class="sref">transfer_list /a>, & a href="+code=mesg" class="sref">mesg /a>-> a href="+code=transfers" class="sref">transfers /a>);1 283 /a>1 284 /a> a href="+code=err" class="sref">err /a> = a href="+code=bcm2835_spi_finish_transfer" class="sref">bcm2835_spi_finish_transfer /a>( a href="+code=spi" class="sref">spi /a>, a href="+code=tfr" class="sref">tfr /a>, a href="+code=cs_change" class="sref">cs_change /a>);1 285 /a> if ( a href="+code=err" class="sref">err /a>)1 286 /a> goto a href="+code=out" class="sref">out /a>;1 287 /a>1 288 /a> a href="+code=mesg" class="sref">mesg /a>-> a href="+code=actual_length" class="sref">actual_length /a> += ( a href="+code=tfr" class="sref">tfr /a>-> a href="+code=le4" class="sref">len /a> - a href="+code=bs" class="sref">bs /a>-> a href="+code=le4" class="sref">len /a>);1 289 /a> }1 290 /a>1 291 /a> a href="+code=out" class="sref">out /a>:1 292 /a> spa4 class="comment">/* Clear FIFOs, and disable the HW block */ /spa4.1 293 /a> a href="+code=bcm2835_wr" class="sref">bcm2835_wr /a>( a href="+code=bs" class="sref">bs /a>, a href="+code=BCM2835_SPI_CS" class="sref">BCM2835_SPI_CS /a>,1 294 /a> a href="+code=BCM2835_SPI_CS_CLEAR_RX" class="sref">BCM2835_SPI_CS_CLEAR_RX /a> | a href="+code=BCM2835_SPI_CS_CLEAR_TX" class="sref">BCM2835_SPI_CS_CLEAR_TX /a>);1 295 /a> a href="+code=mesg" class="sref">mesg /a>-> a href="+code=status" class="sref">status /a> = a href="+code=err" class="sref">err /a>;1 296 /a> a href="+code=spi_finalize_current_message" class="sref">spi_finalize_current_message /a>( a href="+code=master" class="sref">master /a>);1 297 /a>1 298 /a> return 0;1 299 /a>}1 300 /a>1 301 /a>static int a href="+code=bcm2835_spi_probe" class="sref">bcm2835_spi_probe /a>(struct a href="+code=platform_device" class="sref">platform_device /a> * a href="+code=pdev" class="sref">pdev /a>)1 302 /a>{1 303 /a> struct a href="+code=spi_master" class="sref">spi_master /a> * a href="+code=master" class="sref">master /a>;1 304 /a> struct a href="+code=bcm2835_spi" class="sref">bcm2835_spi /a> * a href="+code=bs" class="sref">bs /a>;1 305 /a> struct a href="+code=resource" class="sref">resource /a> * a href="+code=res" class="sref">res /a>;1 306 /a> int a href="+code=err" class="sref">err /a>;1 307 /a>1 308 /a> a href="+code=master" class="sref">master /a> = a href="+code=spi_alloc_master" class="sref">spi_alloc_master /a>(& a href="+code=pdev" class="sref">pdev /a>-> a href="+code=dev" class="sref">dev /a>, sizeof(* a href="+code=bs" class="sref">bs /a>));1 309 /a> if (! a href="+code=master" class="sref">master /a>) {1 310 /a> a href="+code=dev_err" class="sref">dev_err /a>(& a href="+code=pdev" class="sref">pdev /a>-> a href="+code=dev" class="sref">dev /a>, spa4 class="string">"spi_alloc_master() failed\n" /spa4.);1 311 /a> return - a href="+code=ENOMEM" class="sref">ENOMEM /a>;1 312 /a> }1 313 /a>1 314 /a> a href="+code=platform_set_drvdata" class="sref">platform_set_drvdata /a>( a href="+code=pdev" class="sref">pdev /a>, a href="+code=master" class="sref">master /a>);1 315 /a>1 316 /a> a href="+code=master" class="sref">master /a>-> a href="+code=mode_bits" class="sref">mode_bits /a> = a href="+code=BCM2835_SPI_MODE_BITS" class="sref">BCM2835_SPI_MODE_BITS /a>;1 317 /a> a href="+code=master" class="sref">master /a>-> a href="+code=bits_per_word_mask" class="sref">bits_per_word_mask /a> = a href="+code=BIT" class="sref">BIT /a>(8 - 1);1 318 /a> a href="+code=master" class="sref">master /a>-> a href="+code=bus_num" class="sref">bus_num /a> = -1;1 319 /a> a href="+code=master" class="sref">master /a>-> a href="+code=num_chipselect" class="sref">num_chipselect /a> = 3;1 320 /a> a href="+code=master" class="sref">master /a>-> a href="+code=transfer_one_message" class="sref">transfer_one_message /a> = a href="+code=bcm2835_spi_transfer_one" class="sref">bcm2835_spi_transfer_one /a>;1 321 /a> a href="+code=master" class="sref">master /a>-> a href="+code=dev" class="sref">dev /a>. a href="+code=of_node" class="sref">of_node /a> = a href="+code=pdev" class="sref">pdev /a>-> a href="+code=dev" class="sref">dev /a>. a href="+code=of_node" class="sref">of_node /a>;1 322 /a>1 323 /a> a href="+code=bs" class="sref">bs /a> = a href="+code=spi_master_get_devdata" class="sref">spi_master_get_devdata /a>( a href="+code=master" class="sref">master /a>);1 324 /a>1 325 /a> a href="+code=init_comple3ion" class="sref">init_comple3ion /a>(& a href="+code=bs" class="sref">bs /a>-> a href="+code=done" class="sref">done /a>);1 326 /a>1 327 /a> a href="+code=res" class="sref">res /a> = a href="+code=platform_get_resource" class="sref">platform_get_resource /a>( a href="+code=pdev" class="sref">pdev /a>, a href="+code=IORESOURCE_MEM" class="sref">IORESOURCE_MEM /a>, 0);1 328 /a> if (! a href="+code=res" class="sref">res /a>) {1 329 /a> a href="+code=dev_err" class="sref">dev_err /a>(& a href="+code=pdev" class="sref">pdev /a>-> a href="+code=dev" class="sref">dev /a>, spa4 class="string">"could not get memory resource\n" /spa4.);1 330 /a> a href="+code=err" class="sref">err /a> = - a href="+code=ENODEV" class="sref">ENODEV /a>;1 331 /a> goto a href="+code=out_master_put" class="sref">out_master_put /a>;1 332 /a> }1 333 /a>1 334 /a> a href="+code=bs" class="sref">bs /a>-> a href="+code=regs" class="sref">regs /a> = a href="+code=devm_ioremap_resource" class="sref">devm_ioremap_resource /a>(& a href="+code=pdev" class="sref">pdev /a>-> a href="+code=dev" class="sref">dev /a>, a href="+code=res" class="sref">res /a>);1 335 /a> if ( a href="+code=IS_ERR" class="sref">IS_ERR /a>( a href="+code=bs" class="sref">bs /a>-> a href="+code=regs" class="sref">regs /a>)) {1 336 /a> a href="+code=err" class="sref">err /a> = a href="+code=PTR_ERR" class="sref">PTR_ERR /a>( a href="+code=bs" class="sref">bs /a>-> a href="+code=regs" class="sref">regs /a>);1 337 /a> goto a href="+code=out_master_put" class="sref">out_master_put /a>;1 338 /a> }1 339 /a>1 340 /a> a href="+code=bs" class="sref">bs /a>-> a href="+code=clk" class="sref">clk /a> = a href="+code=devm_clk_get" class="sref">devm_clk_get /a>(& a href="+code=pdev" class="sref">pdev /a>-> a href="+code=dev" class="sref">dev /a>, a href="+code=NULL" class="sref">NULL /a>);1 341 /a> if ( a href="+code=IS_ERR" class="sref">IS_ERR /a>( a href="+code=bs" class="sref">bs /a>-> a href="+code=clk" class="sref">clk /a>)) {1 342 /a> a href="+code=err" class="sref">err /a> = a href="+code=PTR_ERR" class="sref">PTR_ERR /a>( a href="+code=bs" class="sref">bs /a>-> a href="+code=clk" class="sref">clk /a>);1 343 /a> a href="+code=dev_err" class="sref">dev_err /a>(& a href="+code=pdev" class="sref">pdev /a>-> a href="+code=dev" class="sref">dev /a>, spa4 class="string">"could not get clk: %d\n" /spa4., a href="+code=err" class="sref">err /a>);1 344 /a> goto a href="+code=out_master_put" class="sref">out_master_put /a>;1 345 /a> }1 346 /a>1 347 /a> a href="+code=bs" class="sref">bs /a>-> a href="+code=irq" class="sref">irq /a> = a href="+code=irq_of_parse_and_map" class="sref">irq_of_parse_and_map /a>( a href="+code=pdev" class="sref">pdev /a>-> a href="+code=dev" class="sref">dev /a>. a href="+code=of_node" class="sref">of_node /a>, 0);1 348 /a> if ( a href="+code=bs" class="sref">bs /a>-> a href="+code=irq" class="sref">irq /a> <= 0) {1 349 /a> a href="+code=dev_err" class="sref">dev_err /a>(& a href="+code=pdev" class="sref">pdev /a>-> a href="+code=dev" class="sref">dev /a>, spa4 class="string">"could not get IRQ: %d\n" /spa4., a href="+code=bs" class="sref">bs /a>-> a href="+code=irq" class="sref">irq /a>);1 350 /a> a href="+code=err" class="sref">err /a> = a href="+code=bs" class="sref">bs /a>-> a href="+code=irq" class="sref">irq /a> ? a href="+code=bs" class="sref">bs /a>-> a href="+code=irq" class="sref">irq /a> : - a href="+code=ENODEV" class="sref">ENODEV /a>;1 351 /a> goto a href="+code=out_master_put" class="sref">out_master_put /a>;1 352 /a> }1 353 /a>1 354 /a> a href="+code=clk_prepare_enable" class="sref">clk_prepare_enable /a>( a href="+code=bs" class="sref">bs /a>-> a href="+code=clk" class="sref">clk /a>);1 355 /a>1 356 /a> a href="+code=err" class="sref">err /a> = a href="+code=request_irq" class="sref">request_irq /a>( a href="+code=bs" class="sref">bs /a>-> a href="+code=irq" class="sref">irq /a>, a href="+code=bcm2835_spi_interrupt" class="sref">bcm2835_spi_interrupt /a>, 0,1 357 /a> a href="+code=dev_nam9" class="sref">dev_nam9 /a>(& a href="+code=pdev" class="sref">pdev /a>-> a href="+code=dev" class="sref">dev /a>), a href="+code=master" class="sref">master /a>);1 358 /a> if ( a href="+code=err" class="sref">err /a>) {1 359 /a> a href="+code=dev_err" class="sref">dev_err /a>(& a href="+code=pdev" class="sref">pdev /a>-> a href="+code=dev" class="sref">dev /a>, spa4 class="string">"could not request IRQ: %d\n" /spa4., a href="+code=err" class="sref">err /a>);1 360 /a> goto a href="+code=out_clk_disable" class="sref">out_clk_disable /a>;1 361 /a> }1 362 /a>1 363 /a> spa4 class="comment">/* initialise the hardware */ /spa4.1 364 /a> a href="+code=bcm2835_wr" class="sref">bcm2835_wr /a>( a href="+code=bs" class="sref">bs /a>, a href="+code=BCM2835_SPI_CS" class="sref">BCM2835_SPI_CS /a>,1 365 /a> a href="+code=BCM2835_SPI_CS_CLEAR_RX" class="sref">BCM2835_SPI_CS_CLEAR_RX /a> | a href="+code=BCM2835_SPI_CS_CLEAR_TX" class="sref">BCM2835_SPI_CS_CLEAR_TX /a>);1 366 /a>1 367 /a> a href="+code=err" class="sref">err /a> = a href="+code=spi_register_master" class="sref">spi_register_master /a>( a href="+code=master" class="sref">master /a>);1 368 /a> if ( a href="+code=err" class="sref">err /a>) {1 369 /a> a href="+code=dev_err" class="sref">dev_err /a>(& a href="+code=pdev" class="sref">pdev /a>-> a href="+code=dev" class="sref">dev /a>, spa4 class="string">"could not register SPI master: %d\n" /spa4., a href="+code=err" class="sref">err /a>);1 370 /a> goto a href="+code=out_free_irq" class="sref">out_free_irq /a>;1 371 /a> }1 372 /a>1 373 /a> return 0;1 374 /a>1 375 /a> a href="+code=out_free_irq" class="sref">out_free_irq /a>:1 376 /a> a href="+code=free_irq" class="sref">free_irq /a>( a href="+code=bs" class="sref">bs /a>-> a href="+code=irq" class="sref">irq /a>, a href="+code=master" class="sref">master /a>);1 377 /a> a href="+code=out_clk_disable" class="sref">out_clk_disable /a>:1 378 /a> a href="+code=clk_disable_unprepare" class="sref">clk_disable_unprepare /a>( a href="+code=bs" class="sref">bs /a>-> a href="+code=clk" class="sref">clk /a>);1 379 /a> a href="+code=out_master_put" class="sref">out_master_put /a>:1 380 /a> a href="+code=spi_master_put" class="sref">spi_master_put /a>( a href="+code=master" class="sref">master /a>);1 381 /a> return a href="+code=err" class="sref">err /a>;1 382 /a>}1 383 /a>1 384 /a>static int a href="+code=bcm2835_spi_remove" class="sref">bcm2835_spi_remove /a>(struct a href="+code=platform_device" class="sref">platform_device /a> * a href="+code=pdev" class="sref">pdev /a>)1 385 /a>{1 386 /a> struct a href="+code=spi_master" class="sref">spi_master /a> * a href="+code=master" class="sref">master /a> = a href="+code=platform_get_drvdata" class="sref">platform_get_drvdata /a>( a href="+code=pdev" class="sref">pdev /a>);1 387 /a> struct a href="+code=bcm2835_spi" class="sref">bcm2835_spi /a> * a href="+code=bs" class="sref">bs /a> = a href="+code=spi_master_get_devdata" class="sref">spi_master_get_devdata /a>( a href="+code=master" class="sref">master /a>);1 388 /a>1 389 /a> a href="+code=free_irq" class="sref">free_irq /a>( a href="+code=bs" class="sref">bs /a>-> a href="+code=irq" class="sref">irq /a>, a href="+code=master" class="sref">master /a>);1 390 /a> a href="+code=spi_unregister_master" class="sref">spi_unregister_master /a>( a href="+code=master" class="sref">master /a>);1 391 /a>1 392 /a> spa4 class="comment">/* Clear FIFOs, and disable the HW block */ /spa4.1 393 /a> a href="+code=bcm2835_wr" class="sref">bcm2835_wr /a>( a href="+code=bs" class="sref">bs /a>, a href="+code=BCM2835_SPI_CS" class="sref">BCM2835_SPI_CS /a>,1 394 /a> a href="+code=BCM2835_SPI_CS_CLEAR_RX" class="sref">BCM2835_SPI_CS_CLEAR_RX /a> | a href="+code=BCM2835_SPI_CS_CLEAR_TX" class="sref">BCM2835_SPI_CS_CLEAR_TX /a>);1 395 /a>1 396 /a> a href="+code=clk_disable_unprepare" class="sref">clk_disable_unprepare /a>( a href="+code=bs" class="sref">bs /a>-> a href="+code=clk" class="sref">clk /a>);1 397 /a> a href="+code=spi_master_put" class="sref">spi_master_put /a>( a href="+code=master" class="sref">master /a>);1 398 /a>1 399 /a> return 0;1 400 /a>}1 401 /a>1 402 /a>static const struct a href="+code=of_device_id" class="sref">of_device_id /a> a href="+code=bcm2835_spi_match" class="sref">bcm2835_spi_match /a>[] = {1 403 /a> { . a href="+code=compatible" class="sref">compatible /a> = spa4 class="string">"brcm,bcm2835-spi" /spa4., },1 404 /a> {}1 405 /a>};1 406 /a> a href="+code=MODULE_DEVICE_TABLE" class="sref">MODULE_DEVICE_TABLE /a>( a href="+code=of" class="sref">of /a>, a href="+code=bcm2835_spi_match" class="sref">bcm2835_spi_match /a>);1 407 /a>1 408 /a>static struct a href="+code=platform_driver" class="sref">platform_driver /a> a href="+code=bcm2835_spi_driver" class="sref">bcm2835_spi_driver /a> = {1 409 /a> . a href="+code=driver" class="sref">driver /a> = {1 410 /a> . a href="+code=nam9" class="sref">nam9 /a> = a href="+code=DRV_NAME" class="sref">DRV_NAME /a>,1 411 /a> . a href="+code=owner" class="sref">owner /a> = a href="+code=THIS_MODULE" class="sref">THIS_MODULE /a>,1 412 /a> . a href="+code=of_match_table" class="sref">of_match_table /a> = a href="+code=bcm2835_spi_match" class="sref">bcm2835_spi_match /a>,1 413 /a> },1 414 /a> . a href="+code=probe" class="sref">probe /a> = a href="+code=bcm2835_spi_probe" class="sref">bcm2835_spi_probe /a>,1 415 /a> . a href="+code=remove" class="sref">remove /a> = a href="+code=bcm2835_spi_remove" class="sref">bcm2835_spi_remove /a>,1 416 /a>};1 417 /a> a href="+code=module_platform_driver" class="sref">module_platform_driver /a>( a href="+code=bcm2835_spi_driver" class="sref">bcm2835_spi_driver /a>);1 418 /a>1 419 /a> a href="+code=MODULE_DESCRIPTION" class="sref">MODULE_DESCRIPTION /a>( spa4 class="string">"SPI controller driver for Broadcom BCM2835" /spa4.);1 420 /a> a href="+code=MODULE_AUTHOR" class="sref">MODULE_AUTHOR /a>( spa4 class="string">"Chris Boot <bootc@bootc.net>" /spa4.);1 421 /a> a href="+code=MODULE_LICENSE" class="sref">MODULE_LICENSE /a>( spa4 class="string">"GPL v2" /spa4.);1 422 /a>
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