linux/drivers/scsi/wd33c93.h
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   1/*
   2 *    wd33c93.h -  Linux device driver definitions for the
   3 *                 Commodore Amiga A2091/590 SCSI controller card
   4 *
   5 *    IMPORTANT: This file is for version 1.25 - 09/Jul/1997
   6 *
   7 * Copyright (c) 1996 John Shifflett, GeoLog Consulting
   8 *    john@geolog.com
   9 *    jshiffle@netcom.com
  10 *
  11 * This program is free software; you can redistribute it and/or modify
  12 * it under the terms of the GNU General Public License as published by
  13 * the Free Software Foundation; either version 2, or (at your option)
  14 * any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 */
  22#ifndef WD33C93_H
  23#define WD33C93_H
  24
  25
  26#define PROC_INTERFACE     /* add code for /proc/scsi/wd33c93/xxx interface */
  27#ifdef  PROC_INTERFACE
  28#define PROC_STATISTICS    /* add code for keeping various real time stats */
  29#endif
  30
  31#define SYNC_DEBUG         /* extra info on sync negotiation printed */
  32#define DEBUGGING_ON       /* enable command-line debugging bitmask */
  33#define DEBUG_DEFAULTS 0   /* default debugging bitmask */
  34
  35
  36#ifdef DEBUGGING_ON
  37#define DB(f,a) if (hostdata->args & (f)) a;
  38#else
  39#define DB(f,a)
  40#endif
  41
  42#define uchar unsigned char
  43
  44
  45/* wd register names */
  46#define WD_OWN_ID    0x00
  47#define WD_CONTROL      0x01
  48#define WD_TIMEOUT_PERIOD  0x02
  49#define WD_CDB_1     0x03
  50#define WD_CDB_2     0x04
  51#define WD_CDB_3     0x05
  52#define WD_CDB_4     0x06
  53#define WD_CDB_5     0x07
  54#define WD_CDB_6     0x08
  55#define WD_CDB_7     0x09
  56#define WD_CDB_8     0x0a
  57#define WD_CDB_9     0x0b
  58#define WD_CDB_10    0x0c
  59#define WD_CDB_11    0x0d
  60#define WD_CDB_12    0x0e
  61#define WD_TARGET_LUN      0x0f
  62#define WD_COMMAND_PHASE   0x10
  63#define WD_SYNCHRONOUS_TRANSFER 0x11
  64#define WD_TRANSFER_COUNT_MSB 0x12
  65#define WD_TRANSFER_COUNT  0x13
  66#define WD_TRANSFER_COUNT_LSB 0x14
  67#define WD_DESTINATION_ID  0x15
  68#define WD_SOURCE_ID    0x16
  69#define WD_SCSI_STATUS     0x17
  70#define WD_COMMAND      0x18
  71#define WD_DATA      0x19
  72#define WD_QUEUE_TAG    0x1a
  73#define WD_AUXILIARY_STATUS   0x1f
  74
  75/* WD commands */
  76#define WD_CMD_RESET    0x00
  77#define WD_CMD_ABORT    0x01
  78#define WD_CMD_ASSERT_ATN  0x02
  79#define WD_CMD_NEGATE_ACK  0x03
  80#define WD_CMD_DISCONNECT  0x04
  81#define WD_CMD_RESELECT    0x05
  82#define WD_CMD_SEL_ATN     0x06
  83#define WD_CMD_SEL      0x07
  84#define WD_CMD_SEL_ATN_XFER   0x08
  85#define WD_CMD_SEL_XFER    0x09
  86#define WD_CMD_RESEL_RECEIVE  0x0a
  87#define WD_CMD_RESEL_SEND  0x0b
  88#define WD_CMD_WAIT_SEL_RECEIVE 0x0c
  89#define WD_CMD_TRANS_ADDR  0x18
  90#define WD_CMD_TRANS_INFO  0x20
  91#define WD_CMD_TRANSFER_PAD   0x21
  92#define WD_CMD_SBT_MODE    0x80
  93
  94/* ASR register */
  95#define ASR_INT         (0x80)
  96#define ASR_LCI         (0x40)
  97#define ASR_BSY         (0x20)
  98#define ASR_CIP         (0x10)
  99#define ASR_PE          (0x02)
 100#define ASR_DBR         (0x01)
 101
 102/* SCSI Bus Phases */
 103#define PHS_DATA_OUT    0x00
 104#define PHS_DATA_IN     0x01
 105#define PHS_COMMAND     0x02
 106#define PHS_STATUS      0x03
 107#define PHS_MESS_OUT    0x06
 108#define PHS_MESS_IN     0x07
 109
 110/* Command Status Register definitions */
 111
 112  /* reset state interrupts */
 113#define CSR_RESET    0x00
 114#define CSR_RESET_AF    0x01
 115
 116  /* successful completion interrupts */
 117#define CSR_RESELECT    0x10
 118#define CSR_SELECT      0x11
 119#define CSR_SEL_XFER_DONE  0x16
 120#define CSR_XFER_DONE      0x18
 121
 122  /* paused or aborted interrupts */
 123#define CSR_MSGIN    0x20
 124#define CSR_SDP         0x21
 125#define CSR_SEL_ABORT      0x22
 126#define CSR_RESEL_ABORT    0x25
 127#define CSR_RESEL_ABORT_AM 0x27
 128#define CSR_ABORT    0x28
 129
 130  /* terminated interrupts */
 131#define CSR_INVALID     0x40
 132#define CSR_UNEXP_DISC     0x41
 133#define CSR_TIMEOUT     0x42
 134#define CSR_PARITY      0x43
 135#define CSR_PARITY_ATN     0x44
 136#define CSR_BAD_STATUS     0x45
 137#define CSR_UNEXP    0x48
 138
 139  /* service required interrupts */
 140#define CSR_RESEL    0x80
 141#define CSR_RESEL_AM    0x81
 142#define CSR_DISC     0x85
 143#define CSR_SRV_REQ     0x88
 144
 145   /* Own ID/CDB Size register */
 146#define OWNID_EAF    0x08
 147#define OWNID_EHP    0x10
 148#define OWNID_RAF    0x20
 149#define OWNID_FS_8   0x00
 150#define OWNID_FS_12  0x40
 151#define OWNID_FS_16  0x80
 152
 153   /* define these so we don't have to change a2091.c, etc. */
 154#define WD33C93_FS_8_10  OWNID_FS_8
 155#define WD33C93_FS_12_15 OWNID_FS_12
 156#define WD33C93_FS_16_20 OWNID_FS_16
 157
 158   /* pass input-clock explicitly. accepted mhz values are 8-10,12-20 */
 159#define WD33C93_FS_MHZ(mhz) (mhz)
 160
 161   /* Control register */
 162#define CTRL_HSP     0x01
 163#define CTRL_HA      0x02
 164#define CTRL_IDI     0x04
 165#define CTRL_EDI     0x08
 166#define CTRL_HHP     0x10
 167#define CTRL_POLLED  0x00
 168#define CTRL_BURST   0x20
 169#define CTRL_BUS     0x40
 170#define CTRL_DMA     0x80
 171
 172   /* Timeout Period register */
 173#define TIMEOUT_PERIOD_VALUE  20    /* 20 = 200 ms */
 174
 175   /* Synchronous Transfer Register */
 176#define STR_FSS      0x80
 177
 178   /* Destination ID register */
 179#define DSTID_DPD    0x40
 180#define DATA_OUT_DIR 0
 181#define DATA_IN_DIR  1
 182#define DSTID_SCC    0x80
 183
 184   /* Source ID register */
 185#define SRCID_MASK   0x07
 186#define SRCID_SIV    0x08
 187#define SRCID_DSP    0x20
 188#define SRCID_ES     0x40
 189#define SRCID_ER     0x80
 190
 191   /* This is what the 3393 chip looks like to us */
 192typedef struct {
 193#ifdef CONFIG_WD33C93_PIO
 194   unsigned int   SASR;
 195   unsigned int   SCMD;
 196#else
 197   volatile unsigned char  *SASR;
 198   volatile unsigned char  *SCMD;
 199#endif
 200} wd33c93_regs;
 201
 202
 203typedef int (*dma_setup_t) (struct scsi_cmnd *SCpnt, int dir_in);
 204typedef void (*dma_stop_t) (struct Scsi_Host *instance,
 205                struct scsi_cmnd *SCpnt, int status);
 206
 207
 208#define ILLEGAL_STATUS_BYTE   0xff
 209
 210#define DEFAULT_SX_PER   376     /* (ns) fairly safe */
 211#define DEFAULT_SX_OFF   0       /* aka async */
 212
 213#define OPTIMUM_SX_PER   252     /* (ns) best we can do (mult-of-4) */
 214#define OPTIMUM_SX_OFF   12      /* size of wd3393 fifo */
 215
 216struct sx_period {
 217   unsigned int   period_ns;
 218   uchar          reg_value;
 219   };
 220
 221/* FEF: defines for hostdata->dma_buffer_pool */
 222
 223#define BUF_CHIP_ALLOCED 0
 224#define BUF_SCSI_ALLOCED 1
 225
 226struct WD33C93_hostdata {
 227    struct Scsi_Host *next;
 228    wd33c93_regs     regs;
 229    spinlock_t       lock;
 230    uchar            clock_freq;
 231    uchar            chip;             /* what kind of wd33c93? */
 232    uchar            microcode;        /* microcode rev */
 233    uchar            dma_buffer_pool;  /* FEF: buffer from chip_ram? */
 234    int              dma_dir;          /* data transfer dir. */
 235    dma_setup_t      dma_setup;
 236    dma_stop_t       dma_stop;
 237    unsigned int     dma_xfer_mask;
 238    uchar            *dma_bounce_buffer;
 239    unsigned int     dma_bounce_len;
 240    volatile uchar   busy[8];          /* index = target, bit = lun */
 241    volatile struct scsi_cmnd *input_Q;       /* commands waiting to be started */
 242    volatile struct scsi_cmnd *selecting;     /* trying to select this command */
 243    volatile struct scsi_cmnd *connected;     /* currently connected command */
 244    volatile struct scsi_cmnd *disconnected_Q;/* commands waiting for reconnect */
 245    uchar            state;            /* what we are currently doing */
 246    uchar            dma;              /* current state of DMA (on/off) */
 247    uchar            level2;           /* extent to which Level-2 commands are used */
 248    uchar            disconnect;       /* disconnect/reselect policy */
 249    unsigned int     args;             /* set from command-line argument */
 250    uchar            incoming_msg[8];  /* filled during message_in phase */
 251    int              incoming_ptr;     /* mainly used with EXTENDED messages */
 252    uchar            outgoing_msg[8];  /* send this during next message_out */
 253    int              outgoing_len;     /* length of outgoing message */
 254    unsigned int     default_sx_per;   /* default transfer period for SCSI bus */
 255    uchar            sync_xfer[8];     /* sync_xfer reg settings per target */
 256    uchar            sync_stat[8];     /* status of sync negotiation per target */
 257    uchar            no_sync;          /* bitmask: don't do sync on these targets */
 258    uchar            no_dma;           /* set this flag to disable DMA */
 259    uchar            dma_mode;         /* DMA Burst Mode or Single Byte DMA */
 260    uchar            fast;             /* set this flag to enable Fast SCSI */
 261    struct sx_period sx_table[9];      /* transfer periods for actual DTC-setting */
 262#ifdef PROC_INTERFACE
 263    uchar            proc;             /* bitmask: what's in proc output */
 264#ifdef PROC_STATISTICS
 265    unsigned long    cmd_cnt[8];       /* # of commands issued per target */
 266    unsigned long    int_cnt;          /* # of interrupts serviced */
 267    unsigned long    pio_cnt;          /* # of pio data transfers */
 268    unsigned long    dma_cnt;          /* # of DMA data transfers */
 269    unsigned long    disc_allowed_cnt[8]; /* # of disconnects allowed per target */
 270    unsigned long    disc_done_cnt[8]; /* # of disconnects done per target*/
 271#endif
 272#endif
 273    };
 274
 275
 276/* defines for hostdata->chip */
 277
 278#define C_WD33C93       0
 279#define C_WD33C93A      1
 280#define C_WD33C93B      2
 281#define C_UNKNOWN_CHIP  100
 282
 283/* defines for hostdata->state */
 284
 285#define S_UNCONNECTED         0
 286#define S_SELECTING           1
 287#define S_RUNNING_LEVEL2      2
 288#define S_CONNECTED           3
 289#define S_PRE_TMP_DISC        4
 290#define S_PRE_CMP_DISC        5
 291
 292/* defines for hostdata->dma */
 293
 294#define D_DMA_OFF          0
 295#define D_DMA_RUNNING      1
 296
 297/* defines for hostdata->level2 */
 298/* NOTE: only the first 3 are implemented so far */
 299
 300#define L2_NONE      1  /* no combination commands - we get lots of ints */
 301#define L2_SELECT    2  /* start with SEL_ATN_XFER, but never resume it */
 302#define L2_BASIC     3  /* resume after STATUS ints & RDP messages */
 303#define L2_DATA      4  /* resume after DATA_IN/OUT ints */
 304#define L2_MOST      5  /* resume after anything except a RESELECT int */
 305#define L2_RESELECT  6  /* resume after everything, including RESELECT ints */
 306#define L2_ALL       7  /* always resume */
 307
 308/* defines for hostdata->disconnect */
 309
 310#define DIS_NEVER    0
 311#define DIS_ADAPTIVE 1
 312#define DIS_ALWAYS   2
 313
 314/* defines for hostdata->args */
 315
 316#define DB_TEST1              1<<0
 317#define DB_TEST2              1<<1
 318#define DB_QUEUE_COMMAND      1<<2
 319#define DB_EXECUTE            1<<3
 320#define DB_INTR               1<<4
 321#define DB_TRANSFER           1<<5
 322#define DB_MASK               0x3f
 323
 324/* defines for hostdata->sync_stat[] */
 325
 326#define SS_UNSET     0
 327#define SS_FIRST     1
 328#define SS_WAITING   2
 329#define SS_SET       3
 330
 331/* defines for hostdata->proc */
 332
 333#define PR_VERSION   1<<0
 334#define PR_INFO      1<<1
 335#define PR_STATISTICS 1<<2
 336#define PR_CONNECTED 1<<3
 337#define PR_INPUTQ    1<<4
 338#define PR_DISCQ     1<<5
 339#define PR_TEST      1<<6
 340#define PR_STOP      1<<7
 341
 342
 343void wd33c93_init (struct Scsi_Host *instance, const wd33c93_regs regs,
 344         dma_setup_t setup, dma_stop_t stop, int clock_freq);
 345int wd33c93_abort (struct scsi_cmnd *cmd);
 346int wd33c93_queuecommand (struct Scsi_Host *h, struct scsi_cmnd *cmd);
 347void wd33c93_intr (struct Scsi_Host *instance);
 348int wd33c93_show_info(struct seq_file *, struct Scsi_Host *);
 349int wd33c93_write_info(struct Scsi_Host *, char *, int);
 350int wd33c93_host_reset (struct scsi_cmnd *);
 351
 352#endif /* WD33C93_H */
 353
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