linux/drivers/scsi/scsi_tgt_if.c
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10..14/spaue= .14/forme= .14a 10..1 href="../linux+v 10..14img src="../.static/gfx/right.png" alt=">>"> 14/spaue= 14spau class="lxr_search"> 10. 10..14input typ > hidden" nam > navtarget" o2 > "> 10..14input typ > text" nam > search" id> search"> 10..14butt/3/typ > submit">Search 10..1Prefs= .14/a> 14/spaue=0..1 14/dive=0..1 14form acvalu="ajax+*" method="post" onsubmit="return false;"> 14input typ > hidden" nam > ajax_lookup" id> ajax_lookup" o2 > "> 0..1 14/forme= 0..1 14div class="headingbott/m"> search_results" class="search_results"= .e=0..1 14/dive= 4div id> content">= 4div id> file_contents"e
a4/d7/46b08074a0877be451a201a40c6e62832dd3_3/0"e
L1" class="line" nam >
L1">1 114/a>4spau class="comment">/*4/spaue=
L2" class="line" nam >
L2">1 124/a>4spau class="comment"> * SCSI target kernel/user interface funcvalus4/spaue=
L3" class="line" nam >
L3">1 134/a>4spau class="comment"> *4/spaue=
L4" class="line" nam >
L4">1 144/a>4spau class="comment"> * Copyright (C) 2005 FUJITA Tomonori <t/mof@acm.org>4/spaue=
L5" class="line" nam >
L5">1 154/a>4spau class="comment"> * Copyright (C) 2005 Mike Christie <michaelc@cs.wisc.edu>4/spaue=
L6" class="line" nam >
L6">1 164/a>4spau class="comment"> *4/spaue=
L7" class="line" nam >
L7">1 174/a>4spau class="comment"> * This program is free software; you cau redistribute it and/or4/spaue=
L8" class="line" nam >
L8">1 184/a>4spau class="comment"> * modify it under the terms of the GNU General Public License as4/spaue=
L9" class="line" nam >
L9">1 194/a>4spau class="comment"> * published by the Free Software Foundavalu; either vers
L10" class="line" nam >
L10">1  
  a>4spau class="comment"> * License, or (at your n valu) any later vers
L11" class="line" nam >
L11">1 114/a>4spau class="comment"> *4/spaue=
L12" class="line" nam >
L12">1 124/a>4spau class="comment"> * This program is distributed in the hope that it will be useful, but4/spaue=
L13" class="line" nam >
L13">1 134/a>4spau class="comment"> * WITHOUT ANY WARRANTY; without even the implied warranty of4/spaue=
L14" class="line" nam >
L14">1 144/a>4spau class="comment"> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU4/spaue=
L15" class="line" nam >
L15">1 154/a>4spau class="comment"> * General Public License for more details.4/spaue=
L16" class="line" nam >
L16">1 164/a>4spau class="comment"> *4/spaue=
L17" class="line" nam >
L17">1 174/a>4spau class="comment"> * You should have received a copy of the GNU General Public License4/spaue=
L18" class="line" nam >
L18">1 184/a>4spau class="comment"> * along with this program; if not, write to the Free Software4/spaue=
L19" class="line" nam >
L19">1 194/a>4spau class="comment"> * Foundavalu, Inc., 51 Franklin St, Fifth Floor, Bostlu, MA4/spaue=
L20" class="line" nam >
L20">1 2
  a>4spau class="comment"> * 02110-1301 USA4/spaue=
L21" class="line" nam >
L21">1 214/a>4spau class="comment"> */4/spaue=
L22" class="line" nam >
L22">1 224/a>#include <linux/miscdevice.h4/a>>=
L23" class="line" nam >
L23">1 234/a>#include <linux/gfp.h4/a>>=
L24" class="line" nam >
L24">1 244/a>#include <linux/file.h4/a>>=
L25" class="line" nam >
L25">1 254/a>#include <linux/export.h4/a>>=
L26" class="line" nam >
L26">1 264/a>#include <net/tcp.h4/a>>=
L27" class="line" nam >
L27">1 274/a>#include <scsi/scsi.h4/a>>=
L28" class="line" nam >
L28">1 284/a>#include <scsi/scsi_cmnd.h4/a>>=
L29" class="line" nam >
L29">1 294/a>#include <scsi/scsi_device.h4/a>>=
L30" class="line" nam >
L30">1 304/a>#include <scsi/scsi_host.h4/a>>=
L31" class="line" nam >
L31">1 314/a>#include <scsi/scsi_tgt.h4/a>>=
L32" class="line" nam >
L32">1 324/a>#include <scsi/scsi_tgt_if.h4/a>>=
L33" class="line" nam >
L33">1 334/a>=
L34" class="line" nam >
L34">1 344/a>#include <asm/cacheflush.h4/a>>=
L35" class="line" nam >
L35">1 354/a>=
L36" class="line" nam >
L36">1 364/a>#include "scsi_tgt_priv.h4/a>"=
L37" class="line" nam >
L37">1 374/a>=
L38" class="line" nam >
L38">1 384/a>#if14a href="+code=TGT_RING_SIZE" class="sref">TGT_RING_SIZE4/a> <14a href="+code=PAGE_SIZE" class="sref">PAGE_SIZE4/a>=
L39" class="line" nam >
L39">1 394/a>#  define14a href="+code=TGT_RING_SIZE" class="sref">TGT_RING_SIZE4/a> 4a href="+code=PAGE_SIZE" class="sref">PAGE_SIZE4/a>=
L40" class="line" nam >
L40">1 404/a>#endif=
L41" class="line" nam >
L41">1 414/a>=
L42" class="line" nam >
L42">1 424/a>#define14a href="+code=TGT_RING_PAGES" class="sref">TGT_RING_PAGES4/a> (4a href="+code=TGT_RING_SIZE" class="sref">TGT_RING_SIZE4/a> >> 4a href="+code=PAGE_SHIFT" class="sref">PAGE_SHIFT4/a>)=
L43" class="line" nam >
L43">1 434/a>#define14a href="+code=TGT_EVENT_PER_PAGE" class="sref">TGT_EVENT_PER_PAGE4/a> (4a href="+code=PAGE_SIZE" class="sref">PAGE_SIZE4/a> / sizeof(struct14a href="+code=tgt_event" class="sref">tgt_event4/a>))=
L44" class="line" nam >
L44">1 444/a>#define14a href="+code=TGT_MAX_EVENTS" class="sref">TGT_MAX_EVENTS4/a> (4a href="+code=TGT_EVENT_PER_PAGE" class="sref">TGT_EVENT_PER_PAGE4/a> *14a href="+code=TGT_RING_PAGES" class="sref">TGT_RING_PAGES4/a>)=
L45" class="line" nam >
L45">1 454/a>=
L46" class="line" nam >
L46">1 464/a>struct14a href="+code=tgt_ring" class="sref">tgt_ring4/a> {=
L47" class="line" nam >
L47">1 474/a>        4a href="+code=u32" class="sref">u324/a>14a href="+code=tr_idx" class="sref">tr_idx4/a>;=
L48" class="line" nam >
L48">1 484/a>        unsigned long 4a href="+code=tr_pages" class="sref">tr_pages4/a>[4a href="+code=TGT_RING_PAGES" class="sref">TGT_RING_PAGES4/a>];=
L49" class="line" nam >
L49">1 494/a>        4a href="+code=spinlock_t" class="sref">spinlock_t4/a>14a href="+code=tr_lock" class="sref">tr_lock4/a>;=
L50" class="line" nam >
L50">1 504/a>};=
L51" class="line" nam >
L51">1 514/a>=
L52" class="line" nam >
L52">1 524/a>4spau class="comment">/* tx_ring : kernel->user, rx_ring : user->kernel */4/spaue=
L53" class="line" nam >
L53">1 534/a>static struct14a href="+code=tgt_ring" class="sref">tgt_ring4/a> 4a href="+code=tx_ring" class="sref">tx_ring4/a>, 4a href="+code=rx_ring" class="sref">rx_ring4/a>;=
L54" class="line" nam >
L54">1 544/a>static 4a href="+code=DECLARE_WAIT_QUEUE_HEAD" class="sref">DECLARE_WAIT_QUEUE_HEAD4/a>(4a href="+code=tgt_poll_wait" class="sref">tgt_poll_wait4/a>);=
L55" class="line" nam >
L55">1 554/a>=
L56" class="line" nam >
L56">1 564/a>static 4a href="+code=inline" class="sref">inline4/a> void14a href="+code=tgt_ring_idx_inc" class="sref">tgt_ring_idx_inc4/a>(struct14a href="+code=tgt_ring" class="sref">tgt_ring4/a> *4a href="+code=ring" class="sref">ring4/a>)=
L57" class="line" nam >
L57">1 574/a>{=
L58" class="line" nam >
L58">1 584/a>        if1(4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_idx" class="sref">tr_idx4/a> ==14a href="+code=TGT_MAX_EVENTS" class="sref">TGT_MAX_EVENTS4/a> - 1)=
L59" class="line" nam >
L59">1 594/a>                4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_idx" class="sref">tr_idx4/a> = 0;=
L60" class="line" nam >
L60">1 604/a>        else=
L61" class="line" nam >
L61">1 614/a>                4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_idx" class="sref">tr_idx4/a>++;=
L62" class="line" nam >
L62">1 624/a>}=
L63" class="line" nam >
L63">1 634/a>=
L64" class="line" nam >
L64">1 644/a>static struct14a href="+code=tgt_event" class="sref">tgt_event4/a> *4a href="+code=tgt_head_event" class="sref">tgt_head_event4/a>(struct14a href="+code=tgt_ring" class="sref">tgt_ring4/a> *4a href="+code=ring" class="sref">ring4/a>, 4a href="+code=u32" class="sref">u324/a>14a href="+code=idx" class="sref">idx4/a>)=
L65" class="line" nam >
L65">1 654/a>{=
L66" class="line" nam >
L66">1 664/a>        4a href="+code=u32" class="sref">u324/a>14a href="+code=pidx" class="sref">pidx4/a>, 4a href="+code=off" class="sref">off4/a>;=
L67" class="line" nam >
L67">1 674/a>=
L68" class="line" nam >
L68">1 684/a>        4a href="+code=pidx" class="sref">pidx4/a> =14a href="+code=idx" class="sref">idx4/a> /14a href="+code=TGT_EVENT_PER_PAGE" class="sref">TGT_EVENT_PER_PAGE4/a>;=
L69" class="line" nam >
L69">1 694/a>        4a href="+code=off" class="sref">off4/a> =14a href="+code=idx" class="sref">idx4/a> % 4a href="+code=TGT_EVENT_PER_PAGE" class="sref">TGT_EVENT_PER_PAGE4/a>;=
L70" class="line" nam >
L70">1 704/a>=
L71" class="line" nam >
L71">1 714/a>        return (struct14a href="+code=tgt_event" class="sref">tgt_event4/a> *)=
L72" class="line" nam >
L72">1 724/a>                (4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_pages" class="sref">tr_pages4/a>[4a href="+code=pidx" class="sref">pidx4/a>] + sizeof(struct14a href="+code=tgt_event" class="sref">tgt_event4/a>) *14a href="+code=off" class="sref">off4/a>);=
L73" class="line" nam >
L73">1 734/a>}=
L74" class="line" nam >
L74">1 744/a>=
L75" class="line" nam >
L75">1 754/a>static int14a href="+code=tgt_uspace_send_event" class="sref">tgt_uspace_send_event4/a>(4a href="+code=u32" class="sref">u324/a>14a href="+code=type" class="sref">type4/a>, struct14a href="+code=tgt_event" class="sref">tgt_event4/a> *4a href="+code=p" class="sref">p4/a>)=
L76" class="line" nam >
L76">1 764/a>{=
L77" class="line" nam >
L77">1 774/a>        struct14a href="+code=tgt_event" class="sref">tgt_event4/a> *4a href="+code=ev" class="sref">ev4/a>;=
L78" class="line" nam >
L78">1 784/a>        struct14a href="+code=tgt_ring" class="sref">tgt_ring4/a> *4a href="+code=ring" class="sref">ring4/a> =1&4a href="+code=tx_ring" class="sref">tx_ring4/a>;=
L79" class="line" nam >
L79">1 794/a>        unsigned long 4a href="+code=flags" class="sref">flags4/a>;=
L80" class="line" nam >
L80">1 804/a>        int14a href="+code=err" class="sref">err4/a> = 0;=
L81" class="line" nam >
L81">1 814/a>=
L82" class="line" nam >
L82">1 824/a>        4a href="+code=spin_lock_irqsave" class="sref">spin_lock_irqsave4/a>(&4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_lock" class="sref">tr_lock4/a>, 4a href="+code=flags" class="sref">flags4/a>);=
L83" class="line" nam >
L83">1 834/a>=
L84" class="line" nam >
L84">1 844/a>        4a href="+code=ev" class="sref">ev4/a> =14a href="+code=tgt_head_event" class="sref">tgt_head_event4/a>(4a href="+code=ring" class="sref">ring4/a>, 4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_idx" class="sref">tr_idx4/a>);=
L85" class="line" nam >
L85">1 854/a>        if1(!4a href="+code=ev" class="sref">ev4/a>->4a href="+code=hdr" class="sref">hdr4/a>.4a href="+code=status" class="sref">status4/a>)=
L86" class="line" nam >
L86">1 864/a>                4a href="+code=tgt_ring_idx_inc" class="sref">tgt_ring_idx_inc4/a>(4a href="+code=ring" class="sref">ring4/a>);=
L87" class="line" nam >
L87">1 874/a>        else=
L88" class="line" nam >
L88">1 884/a>                4a href="+code=err" class="sref">err4/a> = -4a href="+code=BUSY" class="sref">BUSY4/a>;=
L89" class="line" nam >
L89">1 894/a>=
L90" class="line" nam >
L90">1 904/a>        4a href="+code=spin_unlock_irqrestore" class="sref">spin_unlock_irqrestore4/a>(&4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_lock" class="sref">tr_lock4/a>, 4a href="+code=flags" class="sref">flags4/a>);=
L91" class="line" nam >
L91">1 914/a>=
L92" class="line" nam >
L92">1 924/a>        if1(4a href="+code=err" class="sref">err4/a>)=
L93" class="line" nam >
L93">1 934/a>                return 4a href="+code=err" class="sref">err4/a>;=
L94" class="line" nam >
L94">1 944/a>=
L95" class="line" nam >
L95">1 954/a>        4a href="+code=memcpy" class="sref">memcpy4/a>(4a href="+code=ev" class="sref">ev4/a>, 4a href="+code=p" class="sref">p4/a>, sizeof(*4a href="+code=ev" class="sref">ev4/a>));=
L96" class="line" nam >
L96">1 964/a>        4a href="+code=ev" class="sref">ev4/a>->4a href="+code=hdr" class="sref">hdr4/a>.4a href="+code=type" class="sref">type4/a> =14a href="+code=type" class="sref">type4/a>;=
L97" class="line" nam >
L97">1 974/a>        4a href="+code=mb" class="sref">mb4/a>();=
L98" class="line" nam >
L98">1 984/a>        4a href="+code=ev" class="sref">ev4/a>->4a href="+code=hdr" class="sref">hdr4/a>.4a href="+code=status" class="sref">status4/a> =11;=
L99" class="line" nam >
L99">1 994/a>=
L100" class="line" nam >
L100">11004/a>        4a href="+code=flush_dcache_page" class="sref">flush_dcache_page4/a>(4a href="+code=virt_to_page" class="sref">virt_to_page4/a>(4a href="+code=ev" class="sref">ev4/a>));=
L101" class="line" nam >
L101">11014/a>=
L102" class="line" nam >
L102">11024/a>        4a href="+code=wake_up_interruptible" class="sref">wake_up_interruptible4/a>(&4a href="+code=tgt_poll_wait" class="sref">tgt_poll_wait4/a>);=
L103" class="line" nam >
L103">11034/a>=
L104" class="line" nam >
L104">11044/a>        return 0;=
L105" class="line" nam >
L105">11054/a>}=
L106" class="line" nam >
L106">11064/a>=
L107" class="line" nam >
L107">11074/a>int14a href="+code=scsi_tgt_uspace_send_cmd" class="sref">scsi_tgt_uspace_send_cmd4/a>(struct14a href="+code=scsi_cmnd" class="sref">scsi_cmnd4/a> *4a href="+code=cmd" class="sref">cmd4/a>, 4a href="+code=u64" class="sref">u644/a>14a href="+code=itn_id" class="sref">itn_id4/a>,=
L108" class="line" nam >
L108">11084/a>                             struct14a href="+code=scsi_lun" class="sref">scsi_lun4/a> *4a href="+code=lun" class="sref">lun4/a>, 4a href="+code=u64" class="sref">u644/a>14a href="+code=tag" class="sref">tag4/a>)=
L109" class="line" nam >
L109">11094/a>{=
L110" class="line" nam >
L110">11104/a>        struct14a href="+code=Scsi_Host" class="sref">Scsi_Host4/a> *4a href="+code=shost" class="sref">shost4/a> =14a href="+code=scsi_tgt_cmd_to_host" class="sref">scsi_tgt_cmd_to_host4/a>(4a href="+code=cmd" class="sref">cmd4/a>);=
L111" class="line" nam >
L111">11114/a>        struct14a href="+code=tgt_event" class="sref">tgt_event4/a> 4a href="+code=ev" class="sref">ev4/a>;=
L112" class="line" nam >
L112">11124/a>        int14a href="+code=err" class="sref">err4/a>;=
L113" class="line" nam >
L113">11134/a>=
L114" class="line" nam >
L114">11144/a>        4a href="+code=memset" class="sref">memset4/a>(&4a href="+code=ev" class="sref">ev4/a>, 0, sizeof(4a href="+code=ev" class="sref">ev4/a>));=
L115" class="line" nam >
L115">11154/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_req" class="sref">cmd_req4/a>.4a href="+code=host_no" class="sref">host_no4/a> =14a href="+code=shost" class="sref">shost4/a>->4a href="+code=host_no" class="sref">host_no4/a>;=
L116" class="line" nam >
L116">11164/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_req" class="sref">cmd_req4/a>.4a href="+code=itn_id" class="sref">itn_id4/a> =14a href="+code=itn_id" class="sref">itn_id4/a>;=
L117" class="line" nam >
L117">11174/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_req" class="sref">cmd_req4/a>.4a href="+code=data_len" class="sref">data_len4/a> =14a href="+code=scsi_bufflen" class="sref">scsi_bufflen4/a>(4a href="+code=cmd" class="sref">cmd4/a>);=
L118" class="line" nam >
L118">11184/a>        4a href="+code=memcpy" class="sref">memcpy4/a>(4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_req" class="sref">cmd_req4/a>.4a href="+code=scb" class="sref">scb4/a>, 4a href="+code=cmd" class="sref">cmd4/a>->4a href="+code=cmnd" class="sref">cmnd4/a>, sizeof(4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_req" class="sref">cmd_req4/a>.4a href="+code=scb" class="sref">scb4/a>));=
L119" class="line" nam >
L119">11194/a>        4a href="+code=memcpy" class="sref">memcpy4/a>(4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_req" class="sref">cmd_req4/a>.4a href="+code=lun" class="sref">lun4/a>, 4a href="+code=lun" class="sref">lun4/a>, sizeof(4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_req" class="sref">cmd_req4/a>.4a href="+code=lun" class="sref">lun4/a>));=
L120" class="line" nam >
L120">11204/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_req" class="sref">cmd_req4/a>.4a href="+code=attribute" class="sref">attribute4/a> =14a href="+code=cmd" class="sref">cmd4/a>->4a href="+code=tag" class="sref">tag4/a>;=
L121" class="line" nam >
L121">11214/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_req" class="sref">cmd_req4/a>.4a href="+code=tag" class="sref">tag4/a> =14a href="+code=tag" class="sref">tag4/a>;=
L122" class="line" nam >
L122">11224/a>=
L123" class="line" nam >
L123">11234/a>        4a href="+code=dprintk" class="sref">dprintk4/a>(4spau class="string">"%p %d %u %x %llx\n"cmd4/a>, 4a href="+code=shost" class="sref">shost4/a>->4a href="+code=host_no" class="sref">host_no4/a>,=
L124" class="line" nam >
L124">11244/a>                4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_req" class="sref">cmd_req4/a>.4a href="+code=data_len" class="sref">data_len4/a>, 4a href="+code=cmd" class="sref">cmd4/a>->4a href="+code=tag" class="sref">tag4/a>,=
L125" class="line" nam >
L125">11254/a>                (unsigned long long) 4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_req" class="sref">cmd_req4/a>.4a href="+code=tag" class="sref">tag4/a>);=
L126" class="line" nam >
L126">11264/a>=
L127" class="line" nam >
L127">11274/a>        4a href="+code=err" class="sref">err4/a> = 4a href="+code=tgt_uspace_send_event" class="sref">tgt_uspace_send_event4/a>(4a href="+code=TGT_KEVENT_CMD_REQ" class="sref">TGT_KEVENT_CMD_REQ4/a>, &4a href="+code=ev" class="sref">ev4/a>);=
L128" class="line" nam >
L128">11284/a>        if1(4a href="+code=err" class="sref">err4/a>)=
L129" class="line" nam >
L129">11294/a>                4a href="+code=eprintk" class="sref">eprintk4/a>(4spau class="string">"tx buf is full, could not send\n"
L130" class="line" nam >
L130">11304/a>=
L131" class="line" nam >
L131">11314/a>        return 4a href="+code=err" class="sref">err4/a>;=
L132" class="line" nam >
L132">11324/a>}=
L133" class="line" nam >
L133">11334/a>=
L134" class="line" nam >
L134">11344/a>int14a href="+code=scsi_tgt_uspace_send_status" class="sref">scsi_tgt_uspace_send_status4/a>(struct14a href="+code=scsi_cmnd" class="sref">scsi_cmnd4/a> *4a href="+code=cmd" class="sref">cmd4/a>, 4a href="+code=u64" class="sref">u644/a>14a href="+code=itn_id" class="sref">itn_id4/a>, 4a href="+code=u64" class="sref">u644/a>14a href="+code=tag" class="sref">tag4/a>)=
L135" class="line" nam >
L135">11354/a>{=
L136" class="line" nam >
L136">11364/a>        struct14a href="+code=Scsi_Host" class="sref">Scsi_Host4/a> *4a href="+code=shost" class="sref">shost4/a> =14a href="+code=scsi_tgt_cmd_to_host" class="sref">scsi_tgt_cmd_to_host4/a>(4a href="+code=cmd" class="sref">cmd4/a>);=
L137" class="line" nam >
L137">11374/a>        struct14a href="+code=tgt_event" class="sref">tgt_event4/a> 4a href="+code=ev" class="sref">ev4/a>;=
L138" class="line" nam >
L138">11384/a>        int14a href="+code=err" class="sref">err4/a>;=
L139" class="line" nam >
L139">11394/a>=
L140" class="line" nam >
L140">11404/a>        4a href="+code=memset" class="sref">memset4/a>(&4a href="+code=ev" class="sref">ev4/a>, 0, sizeof(4a href="+code=ev" class="sref">ev4/a>));=
L141" class="line" nam >
L141">11414/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_done" class="sref">cmd_done4/a>.4a href="+code=host_no" class="sref">host_no4/a> =14a href="+code=shost" class="sref">shost4/a>->4a href="+code=host_no" class="sref">host_no4/a>;=
L142" class="line" nam >
L142">11424/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_done" class="sref">cmd_done4/a>.4a href="+code=itn_id" class="sref">itn_id4/a> =14a href="+code=itn_id" class="sref">itn_id4/a>;=
L143" class="line" nam >
L143">11434/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_done" class="sref">cmd_done4/a>.4a href="+code=tag" class="sref">tag4/a> =14a href="+code=tag" class="sref">tag4/a>;=
L144" class="line" nam >
L144">11444/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_done" class="sref">cmd_done4/a>.4a href="+code=result" class="sref">result4/a> =14a href="+code=cmd" class="sref">cmd4/a>->4a href="+code=result" class="sref">result4/a>;=
L145" class="line" nam >
L145">11454/a>=
L146" class="line" nam >
L146">11464/a>        4a href="+code=dprintk" class="sref">dprintk4/a>(4spau class="string">"%p %d %llu %u %x\n"cmd4/a>, 4a href="+code=shost" class="sref">shost4/a>->4a href="+code=host_no" class="sref">host_no4/a>,=
L147" class="line" nam >
L147">11474/a>                (unsigned long long) 4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_req" class="sref">cmd_req4/a>.4a href="+code=tag" class="sref">tag4/a>,=
L148" class="line" nam >
L148">11484/a>                4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_req" class="sref">cmd_req4/a>.4a href="+code=data_len" class="sref">data_len4/a>, 4a href="+code=cmd" class="sref">cmd4/a>->4a href="+code=tag" class="sref">tag4/a>);=
L149" class="line" nam >
L149">11494/a>=
L150" class="line" nam >
L150">11504/a>        4a href="+code=err" class="sref">err4/a> = 4a href="+code=tgt_uspace_send_event" class="sref">tgt_uspace_send_event4/a>(4a href="+code=TGT_KEVENT_CMD_DONE" class="sref">TGT_KEVENT_CMD_DONE4/a>, &4a href="+code=ev" class="sref">ev4/a>);=
L151" class="line" nam >
L151">11514/a>        if1(4a href="+code=err" class="sref">err4/a>)=
L152" class="line" nam >
L152">11524/a>                4a href="+code=eprintk" class="sref">eprintk4/a>(4spau class="string">"tx buf is full, could not send\n"
L153" class="line" nam >
L153">11534/a>=
L154" class="line" nam >
L154">11544/a>        return 4a href="+code=err" class="sref">err4/a>;=
L155" class="line" nam >
L155">11554/a>}=
L156" class="line" nam >
L156">11564/a>=
L157" class="line" nam >
L157">11574/a>int14a href="+code=scsi_tgt_uspace_send_tsk_mgmt" class="sref">scsi_tgt_uspace_send_tsk_mgmt4/a>(int14a href="+code=host_no" class="sref">host_no4/a>, 4a href="+code=u64" class="sref">u644/a>14a href="+code=itn_id" class="sref">itn_id4/a>, int14a href="+code=funcvalu" class="sref">funcvalu4/a>,=
L158" class="line" nam >
L158">11584/a>                                  4a href="+code=u64" class="sref">u644/a>14a href="+code=tag" class="sref">tag4/a>, struct14a href="+code=scsi_lun" class="sref">scsi_lun4/a> *4a href="+code=scsilun" class="sref">scsilun4/a>, void1*4a href="+code=data" class="sref">data4/a>)=
L159" class="line" nam >
L159">11594/a>{=
L160" class="line" nam >
L160">11604/a>        struct14a href="+code=tgt_event" class="sref">tgt_event4/a> 4a href="+code=ev" class="sref">ev4/a>;=
L161" class="line" nam >
L161">11614/a>        int14a href="+code=err" class="sref">err4/a>;=
L162" class="line" nam >
L162">11624/a>=
L163" class="line" nam >
L163">11634/a>        4a href="+code=memset" class="sref">memset4/a>(&4a href="+code=ev" class="sref">ev4/a>, 0, sizeof(4a href="+code=ev" class="sref">ev4/a>));=
L164" class="line" nam >
L164">11644/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=tsk_mgmt_req" class="sref">tsk_mgmt_req4/a>.4a href="+code=host_no" class="sref">host_no4/a> =14a href="+code=host_no" class="sref">host_no4/a>;=
L165" class="line" nam >
L165">11654/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=tsk_mgmt_req" class="sref">tsk_mgmt_req4/a>.4a href="+code=itn_id" class="sref">itn_id4/a> =14a href="+code=itn_id" class="sref">itn_id4/a>;=
L166" class="line" nam >
L166">11664/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=tsk_mgmt_req" class="sref">tsk_mgmt_req4/a>.4a href="+code=funcvalu" class="sref">funcvalu4/a> =14a href="+code=funcvalu" class="sref">funcvalu4/a>;=
L167" class="line" nam >
L167">11674/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=tsk_mgmt_req" class="sref">tsk_mgmt_req4/a>.4a href="+code=tag" class="sref">tag4/a> =14a href="+code=tag" class="sref">tag4/a>;=
L168" class="line" nam >
L168">11684/a>        4a href="+code=memcpy" class="sref">memcpy4/a>(4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=tsk_mgmt_req" class="sref">tsk_mgmt_req4/a>.4a href="+code=lun" class="sref">lun4/a>, 4a href="+code=scsilun" class="sref">scsilun4/a>, sizeof(4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=tsk_mgmt_req" class="sref">tsk_mgmt_req4/a>.4a href="+code=lun" class="sref">lun4/a>));=
L169" class="line" nam >
L169">11694/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=tsk_mgmt_req" class="sref">tsk_mgmt_req4/a>.4a href="+code=mid" class="sref">mid4/a> =1(4a href="+code=u64" class="sref">u644/a>) (unsigned long) 4a href="+code=data" class="sref">data4/a>;=
L170" class="line" nam >
L170">11704/a>=
L171" class="line" nam >
L171">11714/a>        4a href="+code=dprintk" class="sref">dprintk4/a>(4spau class="string">"%d %x %llx %llx\n"host_no4/a>, 4a href="+code=funcvalu" class="sref">funcvalu4/a>, (unsigned long long) 4a href="+code=tag" class="sref">tag4/a>,=
L172" class="line" nam >
L172">11724/a>                (unsigned long long) 4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=tsk_mgmt_req" class="sref">tsk_mgmt_req4/a>.4a href="+code=mid" class="sref">mid4/a>);=
L173" class="line" nam >
L173">11734/a>=
L174" class="line" nam >
L174">11744/a>        4a href="+code=err" class="sref">err4/a> = 4a href="+code=tgt_uspace_send_event" class="sref">tgt_uspace_send_event4/a>(4a href="+code=TGT_KEVENT_TSK_MGMT_REQ" class="sref">TGT_KEVENT_TSK_MGMT_REQ4/a>, &4a href="+code=ev" class="sref">ev4/a>);=
L175" class="line" nam >
L175">11754/a>        if1(4a href="+code=err" class="sref">err4/a>)=
L176" class="line" nam >
L176">11764/a>                4a href="+code=eprintk" class="sref">eprintk4/a>(4spau class="string">"tx buf is full, could not send\n"
L177" class="line" nam >
L177">11774/a>=
L178" class="line" nam >
L178">11784/a>        return 4a href="+code=err" class="sref">err4/a>;=
L179" class="line" nam >
L179">11794/a>}=
L180" class="line" nam >
L180">11804/a>=
L181" class="line" nam >
L181">11814/a>int14a href="+code=scsi_tgt_uspace_send_it_nexus_request" class="sref">scsi_tgt_uspace_send_it_nexus_request4/a>(int14a href="+code=host_no" class="sref">host_no4/a>, 4a href="+code=u64" class="sref">u644/a>14a href="+code=itn_id" class="sref">itn_id4/a>,=
L182" class="line" nam >
L182">11824/a>                                          int14a href="+code=funcvalu" class="sref">funcvalu4/a>, char1*4a href="+code=initiator_id" class="sref">initiator_id4/a>)=
L183" class="line" nam >
L183">11834/a>{=
L184" class="line" nam >
L184">11844/a>        struct14a href="+code=tgt_event" class="sref">tgt_event4/a> 4a href="+code=ev" class="sref">ev4/a>;=
L185" class="line" nam >
L185">11854/a>        int14a href="+code=err" class="sref">err4/a>;=
L186" class="line" nam >
L186">11864/a>=
L187" class="line" nam >
L187">11874/a>        4a href="+code=memset" class="sref">memset4/a>(&4a href="+code=ev" class="sref">ev4/a>, 0, sizeof(4a href="+code=ev" class="sref">ev4/a>));=
L188" class="line" nam >
L188">11884/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=it_nexus_req" class="sref">it_nexus_req4/a>.4a href="+code=host_no" class="sref">host_no4/a> =14a href="+code=host_no" class="sref">host_no4/a>;=
L189" class="line" nam >
L189">11894/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=it_nexus_req" class="sref">it_nexus_req4/a>.4a href="+code=funcvalu" class="sref">funcvalu4/a> =14a href="+code=funcvalu" class="sref">funcvalu4/a>;=
L190" class="line" nam >
L190">11904/a>        4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=it_nexus_req" class="sref">it_nexus_req4/a>.4a href="+code=itn_id" class="sref">itn_id4/a> =14a href="+code=itn_id" class="sref">itn_id4/a>;=
L191" class="line" nam >
L191">11914/a>        if1(4a href="+code=initiator_id" class="sref">initiator_id4/a>)=
L192" class="line" nam >
L192">11924/a>                4a href="+code=strncpy" class="sref">strncpy4/a>(4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=it_nexus_req" class="sref">it_nexus_req4/a>.4a href="+code=initiator_id" class="sref">initiator_id4/a>, 4a href="+code=initiator_id" class="sref">initiator_id4/a>,=
L193" class="line" nam >
L193">11934/a>                        sizeof(4a href="+code=ev" class="sref">ev4/a>.4a href="+code=p" class="sref">p4/a>.4a href="+code=it_nexus_req" class="sref">it_nexus_req4/a>.4a href="+code=initiator_id" class="sref">initiator_id4/a>));=
L194" class="line" nam >
L194">11944/a>=
L195" class="line" nam >
L195">11954/a>        4a href="+code=dprintk" class="sref">dprintk4/a>(4spau class="string">"%d %x %llx\n"host_no4/a>, 4a href="+code=funcvalu" class="sref">funcvalu4/a>, (unsigned long long)4a href="+code=itn_id" class="sref">itn_id4/a>);=
L196" class="line" nam >
L196">11964/a>=
L197" class="line" nam >
L197">11974/a>        4a href="+code=err" class="sref">err4/a> = 4a href="+code=tgt_uspace_send_event" class="sref">tgt_uspace_send_event4/a>(4a href="+code=TGT_KEVENT_IT_NEXUS_REQ" class="sref">TGT_KEVENT_IT_NEXUS_REQ4/a>, &4a href="+code=ev" class="sref">ev4/a>);=
L198" class="line" nam >
L198">11984/a>        if1(4a href="+code=err" class="sref">err4/a>)=
L199" class="line" nam >
L199">11994/a>                4a href="+code=eprintk" class="sref">eprintk4/a>(4spau class="string">"tx buf is full, could not send\n"
L200" class="line" nam >
L200">12004/a>=
L201" class="line" nam >
L201">12014/a>        return 4a href="+code=err" class="sref">err4/a>;=
L202" class="line" nam >
L202">12024/a>}=
L203" class="line" nam >
L203">12034/a>=
L204" class="line" nam >
L204">12044/a>static int14a href="+code=event_recv_msg" class="sref">event_recv_msg4/a>(struct14a href="+code=tgt_event" class="sref">tgt_event4/a> *4a href="+code=ev" class="sref">ev4/a>)=
L205" class="line" nam >
L205">12054/a>{=
L206" class="line" nam >
L206">12064/a>        int14a href="+code=err" class="sref">err4/a> = 0;=
L207" class="line" nam >
L207">12074/a>=
L208" class="line" nam >
L208">12084/a>        switch1(4a href="+code=ev" class="sref">ev4/a>->4a href="+code=hdr" class="sref">hdr4/a>.4a href="+code=type" class="sref">type4/a>) {=
L209" class="line" nam >
L209">12094/a>        case14a href="+code=TGT_UEVENT_CMD_RSP" class="sref">TGT_UEVENT_CMD_RSP4/a>:=
L210" class="line" nam >
L210">12104/a>                4a href="+code=err" class="sref">err4/a> = 4a href="+code=scsi_tgt_kspace_exec" class="sref">scsi_tgt_kspace_exec4/a>(4a href="+code=ev" class="sref">ev4/a>->4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_rsp" class="sref">cmd_rsp4/a>.4a href="+code=host_no" class="sref">host_no4/a>,=
L211" class="line" nam >
L211">12114/a>                                           4a href="+code=ev" class="sref">ev4/a>->4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_rsp" class="sref">cmd_rsp4/a>.4a href="+code=itn_id" class="sref">itn_id4/a>,=
L212" class="line" nam >
L212">12124/a>                                           4a href="+code=ev" class="sref">ev4/a>->4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_rsp" class="sref">cmd_rsp4/a>.4a href="+code=result" class="sref">result4/a>,=
L213" class="line" nam >
L213">12134/a>                                           4a href="+code=ev" class="sref">ev4/a>->4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_rsp" class="sref">cmd_rsp4/a>.4a href="+code=tag" class="sref">tag4/a>,=
L214" class="line" nam >
L214">12144/a>                                           4a href="+code=ev" class="sref">ev4/a>->4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_rsp" class="sref">cmd_rsp4/a>.4a href="+code=uaddr" class="sref">uaddr4/a>,=
L215" class="line" nam >
L215">12154/a>                                           4a href="+code=ev" class="sref">ev4/a>->4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_rsp" class="sref">cmd_rsp4/a>.4a href="+code=len" class="sref">len4/a>,=
L216" class="line" nam >
L216">12164/a>                                           4a href="+code=ev" class="sref">ev4/a>->4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_rsp" class="sref">cmd_rsp4/a>.4a href="+code=sense_uaddr" class="sref">sense_uaddr4/a>,=
L217" class="line" nam >
L217">12174/a>                                           4a href="+code=ev" class="sref">ev4/a>->4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_rsp" class="sref">cmd_rsp4/a>.4a href="+code=sense_len" class="sref">sense_len4/a>,=
L218" class="line" nam >
L218">12184/a>                                           4a href="+code=ev" class="sref">ev4/a>->4a href="+code=p" class="sref">p4/a>.4a href="+code=cmd_rsp" class="sref">cmd_rsp4/a>.4a href="+code=rw" class="sref">rw4/a>);=
L219" class="line" nam >
L219">12194/a>                break;=
L220" class="line" nam >
L220">12204/a>        case14a href="+code=TGT_UEVENT_TSK_MGMT_RSP" class="sref">TGT_UEVENT_TSK_MGMT_RSP4/a>:=
L221" class="line" nam >
L221">12214/a>                4a href="+code=err" class="sref">err4/a> = 4a href="+code=scsi_tgt_kspace_tsk_mgmt" class="sref">scsi_tgt_kspace_tsk_mgmt4/a>(4a href="+code=ev" class="sref">ev4/a>->4a href="+code=p" class="sref">p4/a>.4a href="+code=tsk_mgmt_rsp" class="sref">tsk_mgmt_rsp4/a>.4a href="+code=host_no" class="sref">host_no4/a>,=
L222" class="line" nam >
L222">12224/a>                                               4a href="+code=ev" class="sref">ev4/a>->4a href="+code=p" class="sref">p4/a>.4a href="+code=tsk_mgmt_rsp" class="sref">tsk_mgmt_rsp4/a>.4a href="+code=itn_id" class="sref">itn_id4/a>,=
L223" class="line" nam >
L223">12234/a>                                               4a href="+code=ev" class="sref">ev4/a>->4a href="+code=p" class="sref">p4/a>.4a href="+code=tsk_mgmt_rsp" class="sref">tsk_mgmt_rsp4/a>.4a href="+code=mid" class="sref">mid4/a>,=
L224" class="line" nam >
L224">12244/a>                                               4a href="+code=ev" class="sref">ev4/a>->4a href="+code=p" class="sref">p4/a>.4a href="+code=tsk_mgmt_rsp" class="sref">tsk_mgmt_rsp4/a>.4a href="+code=result" class="sref">result4/a>);=
L225" class="line" nam >
L225">12254/a>                break;=
L226" class="line" nam >
L226">12264/a>        case14a href="+code=TGT_UEVENT_IT_NEXUS_RSP" class="sref">TGT_UEVENT_IT_NEXUS_RSP4/a>:=
L227" class="line" nam >
L227">12274/a>                4a href="+code=err" class="sref">err4/a> = 4a href="+code=scsi_tgt_kspace_it_nexus_rsp" class="sref">scsi_tgt_kspace_it_nexus_rsp4/a>(4a href="+code=ev" class="sref">ev4/a>->4a href="+code=p" class="sref">p4/a>.4a href="+code=it_nexus_rsp" class="sref">it_nexus_rsp4/a>.4a href="+code=host_no" class="sref">host_no4/a>,=
L228" class="line" nam >
L228">12284/a>                                                   4a href="+code=ev" class="sref">ev4/a>->4a href="+code=p" class="sref">p4/a>.4a href="+code=it_nexus_rsp" class="sref">it_nexus_rsp4/a>.4a href="+code=itn_id" class="sref">itn_id4/a>,=
L229" class="line" nam >
L229">12294/a>                                                   4a href="+code=ev" class="sref">ev4/a>->4a href="+code=p" class="sref">p4/a>.4a href="+code=it_nexus_rsp" class="sref">it_nexus_rsp4/a>.4a href="+code=result" class="sref">result4/a>);=
L230" class="line" nam >
L230">12304/a>                break;=
L231" class="line" nam >
L231">12314/a>        default:=
L232" class="line" nam >
L232">12324/a>                4a href="+code=eprintk" class="sref">eprintk4/a>(4spau class="string">"unknown type %d\n"ev4/a>->4a href="+code=hdr" class="sref">hdr4/a>.4a href="+code=type" class="sref">type4/a>);=
L233" class="line" nam >
L233">12334/a>                4a href="+code=err" class="sref">err4/a> = -4a href="+code=EINVAL" class="sref">EINVAL4/a>;=
L234" class="line" nam >
L234">12344/a>        }=
L235" class="line" nam >
L235">12354/a>=
L236" class="line" nam >
L236">12364/a>        return 4a href="+code=err" class="sref">err4/a>;=
L237" class="line" nam >
L237">12374/a>}=
L238" class="line" nam >
L238">12384/a>=
L239" class="line" nam >
L239">12394/a>static 4a href="+code=ssize_t" class="sref">ssize_t4/a> 4a href="+code=tgt_write" class="sref">tgt_write4/a>(struct14a href="+code=file" class="sref">file4/a> *4a href="+code=file" class="sref">file4/a>, const char14a href="+code=__user" class="sref">__user4/a> *14a href="+code=buffer" class="sref">buffer4/a>,=
L240" class="line" nam >
L240">12404/a>                         4a href="+code=size_t" class="sref">size_t4/a> 4a href="+code=count" class="sref">count4/a>, 4a href="+code=loff_t" class="sref">loff_t4/a> *14a href="+code=ppos" class="sref">ppos4/a>)=
L241" class="line" nam >
L241">12414/a>{=
L242" class="line" nam >
L242">12424/a>        struct14a href="+code=tgt_event" class="sref">tgt_event4/a> *4a href="+code=ev" class="sref">ev4/a>;=
L243" class="line" nam >
L243">12434/a>        struct14a href="+code=tgt_ring" class="sref">tgt_ring4/a> *4a href="+code=ring" class="sref">ring4/a> = &4a href="+code=rx_ring" class="sref">rx_ring4/a>;=
L244" class="line" nam >
L244">12444/a>=
L245" class="line" nam >
L245">12454/a>        while (1) {=
L246" class="line" nam >
L246">12464/a>                4a href="+code=ev" class="sref">ev4/a> = 4a href="+code=tgt_head_event" class="sref">tgt_head_event4/a>(4a href="+code=ring" class="sref">ring4/a>, 4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_idx" class="sref">tr_idx4/a>);=
L247" class="line" nam >
L247">12474/a>                4spau class="comment">/* do we need this? */
L248" class="line" nam >
L248">12484/a>                4a href="+code=flush_dcache_page" class="sref">flush_dcache_page4/a>(4a href="+code=virt_to_page" class="sref">virt_to_page4/a>(4a href="+code=ev" class="sref">ev4/a>));=
L249" class="line" nam >
L249">12494/a>=
L250" class="line" nam >
L250">12504/a>                if1(!4a href="+code=ev" class="sref">ev4/a>->4a href="+code=hdr" class="sref">hdr4/a>.4a href="+code=status" class="sref">status4/a>)=
L251" class="line" nam >
L251">12514/a>                        break;=
L252" class="line" nam >
L252">12524/a>=
L253" class="line" nam >
L253">12534/a>                4a href="+code=tgt_ring_idx_inc" class="sref">tgt_ring_idx_inc4/a>(4a href="+code=ring" class="sref">ring4/a>);=
L254" class="line" nam >
L254">12544/a>                4a href="+code=event_recv_msg" class="sref">event_recv_msg4/a>(4a href="+code=ev" class="sref">ev4/a>);=
L255" class="line" nam >
L255">12554/a>                4a href="+code=ev" class="sref">ev4/a>->4a href="+code=hdr" class="sref">hdr4/a>.4a href="+code=status" class="sref">status4/a> = 0;=
L256" class="line" nam >
L256">12564/a>        };=
L257" class="line" nam >
L257">12574/a>=
L258" class="line" nam >
L258">12584/a>        return 4a href="+code=count" class="sref">count4/a>;=
L259" class="line" nam >
L259">12594/a>}=
L260" class="line" nam >
L260">12604/a>=
L261" class="line" nam >
L261">12614/a>static unsigned int14a href="+code=tgt_poll" class="sref">tgt_poll4/a>(struct14a href="+code=file" class="sref">file4/a> *14a href="+code=file" class="sref">file4/a>, struct14a href="+code=poll_table_struct" class="sref">poll_table_struct4/a> *4a href="+code=wait" class="sref">wait4/a>)=
L262" class="line" nam >
L262">12624/a>{=
L263" class="line" nam >
L263">12634/a>        struct14a href="+code=tgt_event" class="sref">tgt_event4/a> *4a href="+code=ev" class="sref">ev4/a>;=
L264" class="line" nam >
L264">12644/a>        struct14a href="+code=tgt_ring" class="sref">tgt_ring4/a> *4a href="+code=ring" class="sref">ring4/a> = &4a href="+code=tx_ring" class="sref">tx_ring4/a>;=
L265" class="line" nam >
L265">12654/a>        unsigned long 4a href="+code=flags" class="sref">flags4/a>;=
L266" class="line" nam >
L266">12664/a>        unsigned int14a href="+code=mask" class="sref">mask4/a> = 0;=
L267" class="line" nam >
L267">12674/a>        4a href="+code=u32" class="sref">u324/a> 4a href="+code=idx" class="sref">idx4/a>;=
L268" class="line" nam >
L268">12684/a>=
L269" class="line" nam >
L269">12694/a>        4a href="+code=poll_wait" class="sref">poll_wait4/a>(4a href="+code=file" class="sref">file4/a>, &4a href="+code=tgt_poll_wait" class="sref">tgt_poll_wait4/a>, 4a href="+code=wait" class="sref">wait4/a>);=
L270" class="line" nam >
L270">12704/a>=
L271" class="line" nam >
L271">12714/a>        4a href="+code=spin_lock_irqsave" class="sref">spin_lock_irqsave4/a>(&4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_lock" class="sref">tr_lock4/a>, 4a href="+code=flags" class="sref">flags4/a>);=
L272" class="line" nam >
L272">12724/a>=
L273" class="line" nam >
L273">12734/a>        4a href="+code=idx" class="sref">idx4/a> = 4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_idx" class="sref">tr_idx4/a> ? 4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_idx" class="sref">tr_idx4/a> - 1 :14a href="+code=TGT_MAX_EVENTS" class="sref">TGT_MAX_EVENTS4/a> - 1;=
L274" class="line" nam >
L274">12744/a>        4a href="+code=ev" class="sref">ev4/a> = 4a href="+code=tgt_head_event" class="sref">tgt_head_event4/a>(4a href="+code=ring" class="sref">ring4/a>, 4a href="+code=idx" class="sref">idx4/a>);=
L275" class="line" nam >
L275">12754/a>        if1(4a href="+code=ev" class="sref">ev4/a>->4a href="+code=hdr" class="sref">hdr4/a>.4a href="+code=status" class="sref">status4/a>)=
L276" class="line" nam >
L276">12764/a>                4a href="+code=mask" class="sref">mask4/a> |= 4a href="+code=POLLIN" class="sref">POLLIN4/a> | 4a href="+code=POLLRDNORM" class="sref">POLLRDNORM4/a>;=
L277" class="line" nam >
L277">12774/a>=
L278" class="line" nam >
L278">12784/a>        4a href="+code=spin_unlock_irqrestore" class="sref">spin_unlock_irqrestore4/a>(&4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_lock" class="sref">tr_lock4/a>, 4a href="+code=flags" class="sref">flags4/a>);=
L279" class="line" nam >
L279">12794/a>=
L280" class="line" nam >
L280">12804/a>        return 4a href="+code=mask" class="sref">mask4/a>;=
L281" class="line" nam >
L281">12814/a>}=
L282" class="line" nam >
L282">12824/a>=
L283" class="line" nam >
L283">12834/a>static int14a href="+code=uspace_ring_map" class="sref">uspace_ring_map4/a>(struct14a href="+code=vm_area_struct" class="sref">vm_area_struct4/a> *4a href="+code=vma" class="sref">vma4/a>, unsigned long 4a href="+code=addr" class="sref">addr4/a>,=
L284" class="line" nam >
L284">12844/a>                           struct14a href="+code=tgt_ring" class="sref">tgt_ring4/a> *4a href="+code=ring" class="sref">ring4/a>)=
L285" class="line" nam >
L285">12854/a>{=
L286" class="line" nam >
L286">12864/a>        int14a href="+code=i" class="sref">i4/a>, 4a href="+code=err" class="sref">err4/a>;=
L287" class="line" nam >
L287">12874/a>=
L288" class="line" nam >
L288">12884/a>        for1(4a href="+code=i" class="sref">i4/a> = 0;14a href="+code=i" class="sref">i4/a> <14a href="+code=TGT_RING_PAGES" class="sref">TGT_RING_PAGES4/a>;14a href="+code=i" class="sref">i4/a>++) {=
L289" class="line" nam >
L289">12894/a>                struct14a href="+code=page" class="sref">page4/a> *4a href="+code=page" class="sref">page4/a> = 4a href="+code=virt_to_page" class="sref">virt_to_page4/a>(4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_pages" class="sref">tr_pages4/a>[4a href="+code=i" class="sref">i4/a>]);=
L290" class="line" nam >
L290">12904/a>                4a href="+code=err" class="sref">err4/a> = 4a href="+code=vm_insert_page" class="sref">vm_insert_page4/a>(4a href="+code=vma" class="sref">vma4/a>, 4a href="+code=addr" class="sref">addr4/a>,14a href="+code=page" class="sref">page4/a>);=
L291" class="line" nam >
L291">12914/a>                if1(4a href="+code=err" class="sref">err4/a>)=
L292" class="line" nam >
L292">12924/a>                        return 4a href="+code=err" class="sref">err4/a>;=
L293" class="line" nam >
L293">12934/a>                4a href="+code=addr" class="sref">addr4/a> += 4a href="+code=PAGE_SIZE" class="sref">PAGE_SIZE4/a>;=
L294" class="line" nam >
L294">12944/a>        }=
L295" class="line" nam >
L295">12954/a>=
L296" class="line" nam >
L296">12964/a>        return 0;=
L297" class="line" nam >
L297">12974/a>}=
L298" class="line" nam >
L298">12984/a>=
L299" class="line" nam >
L299">12994/a>static int14a href="+code=tgt_mmap" class="sref">tgt_mmap4/a>(struct14a href="+code=file" class="sref">file4/a> *4a href="+code=filp" class="sref">filp4/a>, struct14a href="+code=vm_area_struct" class="sref">vm_area_struct4/a> *4a href="+code=vma" class="sref">vma4/a>)=
L300" class="line" nam >
L300">13004/a>{=
L301" class="line" nam >
L301">13014/a>        unsigned long 4a href="+code=addr" class="sref">addr4/a>;=
L302" class="line" nam >
L302">13024/a>        int14a href="+code=err" class="sref">err4/a>;=
L303" class="line" nam >
L303">13034/a>=
L304" class="line" nam >
L304">13044/a>        if1(4a href="+code=vma" class="sref">vma4/a>->4a href="+code=vm_pgoff" class="sref">vm_pgoff4/a>)=
L305" class="line" nam >
L305">13054/a>                return -4a href="+code=EINVAL" class="sref">EINVAL4/a>;=
L306" class="line" nam >
L306">13064/a>=
L307" class="line" nam >
L307">13074/a>        if1(4a href="+code=vma" class="sref">vma4/a>->4a href="+code=vm_end" class="sref">vm_end4/a> - 4a href="+code=vma" class="sref">vma4/a>->4a href="+code=vm_start" class="sref">vm_start4/a> != 4a href="+code=TGT_RING_SIZE" class="sref">TGT_RING_SIZE4/a> * 2) {=
L308" class="line" nam >
L308">13084/a>                4a href="+code=eprintk" class="sref">eprintk4/a>(4spau class="string">"mmap size must be %lu, not %lu \n"
L309" class="line" nam >
L309">13094/a>                        4a href="+code=TGT_RING_SIZE" class="sref">TGT_RING_SIZE4/a> * 2,14a href="+code=vma" class="sref">vma4/a>->4a href="+code=vm_end" class="sref">vm_end4/a> - 4a href="+code=vma" class="sref">vma4/a>->4a href="+code=vm_start" class="sref">vm_start4/a>);=
L310" class="line" nam >
L310">13104/a>                return -4a href="+code=EINVAL" class="sref">EINVAL4/a>;=
L311" class="line" nam >
L311">13114/a>        }=
L312" class="line" nam >
L312">13124/a>=
L313" class="line" nam >
L313">13134/a>        4a href="+code=addr" class="sref">addr4/a> = 4a href="+code=vma" class="sref">vma4/a>->4a href="+code=vm_start" class="sref">vm_start4/a>;=
L314" class="line" nam >
L314">13144/a>        4a href="+code=err" class="sref">err4/a> = 4a href="+code=uspace_ring_map" class="sref">uspace_ring_map4/a>(4a href="+code=vma" class="sref">vma4/a>, 4a href="+code=addr" class="sref">addr4/a>,1&4a href="+code=tx_ring" class="sref">tx_ring4/a>);=
L315" class="line" nam >
L315">13154/a>        if1(4a href="+code=err" class="sref">err4/a>)=
L316" class="line" nam >
L316">13164/a>                return 4a href="+code=err" class="sref">err4/a>;=
L317" class="line" nam >
L317">13174/a>        4a href="+code=err" class="sref">err4/a> = 4a href="+code=uspace_ring_map" class="sref">uspace_ring_map4/a>(4a href="+code=vma" class="sref">vma4/a>, 4a href="+code=addr" class="sref">addr4/a> + 4a href="+code=TGT_RING_SIZE" class="sref">TGT_RING_SIZE4/a>,1&4a href="+code=rx_ring" class="sref">rx_ring4/a>);=
L318" class="line" nam >
L318">13184/a>=
L319" class="line" nam >
L319">13194/a>        return 4a href="+code=err" class="sref">err4/a>;=
L320" class="line" nam >
L320">13204/a>}=
L321" class="line" nam >
L321">13214/a>=
L322" class="line" nam >
L322">13224/a>static int14a href="+code=tgt_open" class="sref">tgt_open4/a>(struct14a href="+code=inode" class="sref">inode4/a> *4a href="+code=inode" class="sref">inode4/a>, struct14a href="+code=file" class="sref">file4/a> *4a href="+code=file" class="sref">file4/a>)=
L323" class="line" nam >
L323">13234/a>{=
L324" class="line" nam >
L324">13244/a>        4a href="+code=tx_ring" class="sref">tx_ring4/a>.4a href="+code=tr_idx" class="sref">tr_idx4/a> = 4a href="+code=rx_ring" class="sref">rx_ring4/a>.4a href="+code=tr_idx" class="sref">tr_idx4/a> = 0;=
L325" class="line" nam >
L325">13254/a>=
L326" class="line" nam >
L326">13264/a>        return 0;=
L327" class="line" nam >
L327">13274/a>}=
L328" class="line" nam >
L328">13284/a>=
L329" class="line" nam >
L329">13294/a>static const struct14a href="+code=file_operavalus" class="sref">file_operavalus4/a> 4a href="+code=tgt_fops" class="sref">tgt_fops4/a> = {=
L330" class="line" nam >
L330">13304/a>        .4a href="+code=owner" class="sref">owner4/a>          = 4a href="+code=THIS_MODULE" class="sref">THIS_MODULE4/a>,=
L331" class="line" nam >
L331">13314/a>        .4a href="+code=open" class="sref">open4/a>           = 4a href="+code=tgt_open" class="sref">tgt_open4/a>,=
L332" class="line" nam >
L332">13324/a>        .4a href="+code=poll" class="sref">poll4/a>           = 4a href="+code=tgt_poll" class="sref">tgt_poll4/a>,=
L333" class="line" nam >
L333">13334/a>        .4a href="+code=write" class="sref">write4/a>          = 4a href="+code=tgt_write" class="sref">tgt_write4/a>,=
L334" class="line" nam >
L334">13344/a>        .4a href="+code=mmap" class="sref">mmap4/a>           = 4a href="+code=tgt_mmap" class="sref">tgt_mmap4/a>,=
L335" class="line" nam >
L335">13354/a>        .4a href="+code=llseek" class="sref">llseek4/a>         = 4a href="+code=noop_llseek" class="sref">noop_llseek4/a>,=
L336" class="line" nam >
L336">13364/a>};=
L337" class="line" nam >
L337">13374/a>=
L338" class="line" nam >
L338">13384/a>static struct14a href="+code=miscdevice" class="sref">miscdevice4/a> 4a href="+code=tgt_miscdev" class="sref">tgt_miscdev4/a> = {=
L339" class="line" nam >
L339">13394/a>        .4a href="+code=minor" class="sref">minor4/a> = 4a href="+code=MISC_DYNAMIC_MINOR" class="sref">MISC_DYNAMIC_MINOR4/a>,=
L340" class="line" nam >
L340">13404/a>        .4a href="+code=nam " class="sref">nam 4/a> = 4spau class="string">"tgt"
L341" class="line" nam >
L341">13414/a>        .4a href="+code=fops" class="sref">fops4/a> = &4a href="+code=tgt_fops" class="sref">tgt_fops4/a>,=
L342" class="line" nam >
L342">13424/a>};=
L343" class="line" nam >
L343">13434/a>=
L344" class="line" nam >
L344">13444/a>static void 4a href="+code=tgt_ring_exit" class="sref">tgt_ring_exit4/a>(struct14a href="+code=tgt_ring" class="sref">tgt_ring4/a> *4a href="+code=ring" class="sref">ring4/a>)=
L345" class="line" nam >
L345">13454/a>{=
L346" class="line" nam >
L346">13464/a>        int14a href="+code=i" class="sref">i4/a>;=
L347" class="line" nam >
L347">13474/a>=
L348" class="line" nam >
L348">13484/a>        for1(4a href="+code=i" class="sref">i4/a> = 0;14a href="+code=i" class="sref">i4/a> <14a href="+code=TGT_RING_PAGES" class="sref">TGT_RING_PAGES4/a>;14a href="+code=i" class="sref">i4/a>++)=
L349" class="line" nam >
L349">13494/a>                4a href="+code=free_page" class="sref">free_page4/a>(4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_pages" class="sref">tr_pages4/a>[4a href="+code=i" class="sref">i4/a>]);=
L350" class="line" nam >
L350">13504/a>}=
L351" class="line" nam >
L351">13514/a>=
L352" class="line" nam >
L352">13524/a>static int14a href="+code=tgt_ring_init" class="sref">tgt_ring_init4/a>(struct14a href="+code=tgt_ring" class="sref">tgt_ring4/a> *4a href="+code=ring" class="sref">ring4/a>)=
L353" class="line" nam >
L353">13534/a>{=
L354" class="line" nam >
L354">13544/a>        int14a href="+code=i" class="sref">i4/a>;=
L355" class="line" nam >
L355">13554/a>=
L356" class="line" nam >
L356">13564/a>        4a href="+code=spin_lock_init" class="sref">spin_lock_init4/a>(&4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_lock" class="sref">tr_lock4/a>);=
L357" class="line" nam >
L357">13574/a>=
L358" class="line" nam >
L358">13584/a>        for1(4a href="+code=i" class="sref">i4/a> = 0;14a href="+code=i" class="sref">i4/a> <14a href="+code=TGT_RING_PAGES" class="sref">TGT_RING_PAGES4/a>;14a href="+code=i" class="sref">i4/a>++) {=
L359" class="line" nam >
L359">13594/a>                4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_pages" class="sref">tr_pages4/a>[4a href="+code=i" class="sref">i4/a>] = 4a href="+code=get_zeroed_page" class="sref">get_zeroed_page4/a>(4a href="+code=GFP_KERNEL" class="sref">GFP_KERNEL4/a>);=
L360" class="line" nam >
L360">13604/a>                if1(!4a href="+code=ring" class="sref">ring4/a>->4a href="+code=tr_pages" class="sref">tr_pages4/a>[4a href="+code=i" class="sref">i4/a>]) {=
L361" class="line" nam >
L361">13614/a>                        4a href="+code=eprintk" class="sref">eprintk4/a>(4spau class="string">"out of memory\n"
L362" class="line" nam >
L362">13624/a>                        return -4a href="+code=ENOMEM" class="sref">ENOMEM4/a>;=
L363" class="line" nam >
L363">13634/a>                }=
L364" class="line" nam >
L364">13644/a>        }=
L365" class="line" nam >
L365">13654/a>=
L366" class="line" nam >
L366">13664/a>        return 0;=
L367" class="line" nam >
L367">13674/a>}=
L368" class="line" nam >
L368">13684/a>=
L369" class="line" nam >
L369">13694/a>void 4a href="+code=scsi_tgt_if_exit" class="sref">scsi_tgt_if_exit4/a>(void)=
L370" class="line" nam >
L370">13704/a>{=
L371" class="line" nam >
L371">13714/a>        4a href="+code=tgt_ring_exit" class="sref">tgt_ring_exit4/a>(&4a href="+code=tx_ring" class="sref">tx_ring4/a>);=
L372" class="line" nam >
L372">13724/a>        4a href="+code=tgt_ring_exit" class="sref">tgt_ring_exit4/a>(&4a href="+code=rx_ring" class="sref">rx_ring4/a>);=
L373" class="line" nam >
L373">13734/a>        4a href="+code=misc_deregister" class="sref">misc_deregister4/a>(&4a href="+code=tgt_miscdev" class="sref">tgt_miscdev4/a>);=
L374" class="line" nam >
L374">13744/a>}=
L375" class="line" nam >
L375">13754/a>=
L376" class="line" nam >
L376">13764/a>int14a href="+code=scsi_tgt_if_init" class="sref">scsi_tgt_if_init4/a>(void)=
L377" class="line" nam >
L377">13774/a>{=
L378" class="line" nam >
L378">13784/a>        int14a href="+code=err" class="sref">err4/a>;=
L379" class="line" nam >
L379">13794/a>=
L380" class="line" nam >
L380">13804/a>        4a href="+code=err" class="sref">err4/a> = 4a href="+code=tgt_ring_init" class="sref">tgt_ring_init4/a>(&4a href="+code=tx_ring" class="sref">tx_ring4/a>);=
L381" class="line" nam >
L381">13814/a>        if1(4a href="+code=err" class="sref">err4/a>)=
L382" class="line" nam >
L382">13824/a>                return 4a href="+code=err" class="sref">err4/a>;=
L383" class="line" nam >
L383">13834/a>=
L384" class="line" nam >
L384">13844/a>        4a href="+code=err" class="sref">err4/a> = 4a href="+code=tgt_ring_init" class="sref">tgt_ring_init4/a>(&4a href="+code=rx_ring" class="sref">rx_ring4/a>);=
L385" class="line" nam >
L385">13854/a>        if1(4a href="+code=err" class="sref">err4/a>)=
L386" class="line" nam >
L386">13864/a>                goto 4a href="+code=free_tx_ring" class="sref">free_tx_ring4/a>;=
L387" class="line" nam >
L387">13874/a>=
L388" class="line" nam >
L388">13884/a>        4a href="+code=err" class="sref">err4/a> = 4a href="+code=misc_register" class="sref">misc_register4/a>(&4a href="+code=tgt_miscdev" class="sref">tgt_miscdev4/a>);=
L389" class="line" nam >
L389">13894/a>        if1(4a href="+code=err" class="sref">err4/a>)=
L390" class="line" nam >
L390">13904/a>                goto 4a href="+code=free_rx_ring" class="sref">free_rx_ring4/a>;=
L391" class="line" nam >
L391">13914/a>=
L392" class="line" nam >
L392">13924/a>        return 0;=
L393" class="line" nam >
L393">13934/a>4a href="+code=free_rx_ring" class="sref">free_rx_ring4/a>:=
L394" class="line" nam >
L394">13944/a>        4a href="+code=tgt_ring_exit" class="sref">tgt_ring_exit4/a>(&4a href="+code=rx_ring" class="sref">rx_ring4/a>);=
L395" class="line" nam >
L395">13954/a>4a href="+code=free_tx_ring" class="sref">free_tx_ring4/a>:=
L396" class="line" nam >
L396">13964/a>        4a href="+code=tgt_ring_exit" class="sref">tgt_ring_exit4/a>(&4a href="+code=tx_ring" class="sref">tx_ring4/a>);=
L397" class="line" nam >
L397">13974/a>=
L398" class="line" nam >
L398">13984/a>        return 4a href="+code=err" class="sref">err4/a>;=
L399" class="line" nam >
L399">13994/a>}=
L400" class="line" nam >
L400">14004/a>
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