linux/drivers/scsi/aha152x.h
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   1#ifndef _AHA152X_H
   2#define _AHA152X_H
   3
   4/*
   5 * $Id: aha152x.h,v 2.7 2004/01/24 11:39:03 fischer Exp $
   6 */
   7
   8/* number of queueable commands
   9   (unless we support more than 1 cmd_per_lun this should do) */
  10#define AHA152X_MAXQUEUE 7
  11
  12#define AHA152X_REVID "Adaptec 152x SCSI driver; $Revision: 2.7 $"
  13
  14/* port addresses */
  15#define SCSISEQ      (HOSTIOPORT0+0x00)    /* SCSI sequence control */
  16#define SXFRCTL0     (HOSTIOPORT0+0x01)    /* SCSI transfer control 0 */
  17#define SXFRCTL1     (HOSTIOPORT0+0x02)    /* SCSI transfer control 1 */
  18#define SCSISIG      (HOSTIOPORT0+0x03)    /* SCSI signal in/out */
  19#define SCSIRATE     (HOSTIOPORT0+0x04)    /* SCSI rate control */
  20#define SELID        (HOSTIOPORT0+0x05)    /* selection/reselection ID */
  21#define SCSIID       SELID                 /* SCSI ID */
  22#define SCSIDAT      (HOSTIOPORT0+0x06)    /* SCSI latched data */
  23#define SCSIBUS      (HOSTIOPORT0+0x07)    /* SCSI data bus */
  24#define STCNT0       (HOSTIOPORT0+0x08)    /* SCSI transfer count 0 */
  25#define STCNT1       (HOSTIOPORT0+0x09)    /* SCSI transfer count 1 */
  26#define STCNT2       (HOSTIOPORT0+0x0a)    /* SCSI transfer count 2 */
  27#define SSTAT0       (HOSTIOPORT0+0x0b)    /* SCSI interrupt status 0 */
  28#define SSTAT1       (HOSTIOPORT0+0x0c)    /* SCSI interrupt status 1 */
  29#define SSTAT2       (HOSTIOPORT0+0x0d)    /* SCSI interrupt status 2 */
  30#define SCSITEST     (HOSTIOPORT0+0x0e)    /* SCSI test control */
  31#define SSTAT3       SCSITEST              /* SCSI interrupt status 3 */
  32#define SSTAT4       (HOSTIOPORT0+0x0f)    /* SCSI status 4 */
  33#define SIMODE0      (HOSTIOPORT1+0x10)    /* SCSI interrupt mode 0 */
  34#define SIMODE1      (HOSTIOPORT1+0x11)    /* SCSI interrupt mode 1 */
  35#define DMACNTRL0    (HOSTIOPORT1+0x12)    /* DMA control 0 */
  36#define DMACNTRL1    (HOSTIOPORT1+0x13)    /* DMA control 1 */
  37#define DMASTAT      (HOSTIOPORT1+0x14)    /* DMA status */
  38#define FIFOSTAT     (HOSTIOPORT1+0x15)    /* FIFO status */
  39#define DATAPORT     (HOSTIOPORT1+0x16)    /* DATA port */
  40#define BRSTCNTRL    (HOSTIOPORT1+0x18)    /* burst control */
  41#define PORTA        (HOSTIOPORT1+0x1a)    /* PORT A */
  42#define PORTB        (HOSTIOPORT1+0x1b)    /* PORT B */
  43#define REV          (HOSTIOPORT1+0x1c)    /* revision */
  44#define STACK        (HOSTIOPORT1+0x1d)    /* stack */
  45#define TEST         (HOSTIOPORT1+0x1e)    /* test register */
  46
  47#define IO_RANGE        0x20
  48
  49/* used in aha152x_porttest */
  50#define O_PORTA         0x1a               /* PORT A */
  51#define O_PORTB         0x1b               /* PORT B */
  52#define O_DMACNTRL1     0x13               /* DMA control 1 */
  53#define O_STACK         0x1d               /* stack */
  54
  55/* used in tc1550_porttest */
  56#define O_TC_PORTA      0x0a               /* PORT A */
  57#define O_TC_PORTB      0x0b               /* PORT B */
  58#define O_TC_DMACNTRL1  0x03               /* DMA control 1 */
  59#define O_TC_STACK      0x0d               /* stack */
  60
  61/* bits and bitmasks to ports */
  62
  63/* SCSI sequence control */
  64#define TEMODEO      0x80
  65#define ENSELO       0x40
  66#define ENSELI       0x20
  67#define ENRESELI     0x10
  68#define ENAUTOATNO   0x08
  69#define ENAUTOATNI   0x04
  70#define ENAUTOATNP   0x02
  71#define SCSIRSTO     0x01
  72
  73/* SCSI transfer control 0 */
  74#define SCSIEN       0x80
  75#define DMAEN        0x40
  76#define CH1          0x20
  77#define CLRSTCNT     0x10
  78#define SPIOEN       0x08
  79#define CLRCH1       0x02
  80
  81/* SCSI transfer control 1 */
  82#define BITBUCKET    0x80
  83#define SWRAPEN      0x40
  84#define ENSPCHK      0x20
  85#define STIMESEL     0x18    /* mask */
  86#define STIMESEL_    3
  87#define ENSTIMER     0x04
  88#define BYTEALIGN    0x02
  89
  90/* SCSI signal IN */
  91#define SIG_CDI          0x80
  92#define SIG_IOI          0x40
  93#define SIG_MSGI         0x20
  94#define SIG_ATNI         0x10
  95#define SIG_SELI         0x08
  96#define SIG_BSYI         0x04
  97#define SIG_REQI         0x02
  98#define SIG_ACKI         0x01
  99
 100/* SCSI Phases */
 101#define P_MASK       (SIG_MSGI|SIG_CDI|SIG_IOI)
 102#define P_DATAO      (0)
 103#define P_DATAI      (SIG_IOI)
 104#define P_CMD        (SIG_CDI)
 105#define P_STATUS     (SIG_CDI|SIG_IOI)
 106#define P_MSGO       (SIG_MSGI|SIG_CDI)
 107#define P_MSGI       (SIG_MSGI|SIG_CDI|SIG_IOI)
 108
 109/* SCSI signal OUT */
 110#define SIG_CDO          0x80
 111#define SIG_IOO          0x40
 112#define SIG_MSGO         0x20
 113#define SIG_ATNO         0x10
 114#define SIG_SELO         0x08
 115#define SIG_BSYO         0x04
 116#define SIG_REQO         0x02
 117#define SIG_ACKO         0x01
 118
 119/* SCSI rate control */
 120#define SXFR         0x70    /* mask */
 121#define SXFR_        4
 122#define SOFS         0x0f    /* mask */
 123
 124/* SCSI ID */
 125#define OID          0x70
 126#define OID_         4
 127#define TID          0x07
 128
 129/* SCSI transfer count */
 130#define GETSTCNT() ( (GETPORT(STCNT2)<<16) \
 131                   + (GETPORT(STCNT1)<< 8) \
 132                   + GETPORT(STCNT0) )
 133
 134#define SETSTCNT(X) { SETPORT(STCNT2, ((X) & 0xFF0000) >> 16); \
 135                      SETPORT(STCNT1, ((X) & 0x00FF00) >>  8); \
 136                      SETPORT(STCNT0, ((X) & 0x0000FF) ); }
 137
 138/* SCSI interrupt status */
 139#define TARGET       0x80
 140#define SELDO        0x40
 141#define SELDI        0x20
 142#define SELINGO      0x10
 143#define SWRAP        0x08
 144#define SDONE        0x04
 145#define SPIORDY      0x02
 146#define DMADONE      0x01
 147
 148#define SETSDONE     0x80
 149#define CLRSELDO     0x40
 150#define CLRSELDI     0x20
 151#define CLRSELINGO   0x10
 152#define CLRSWRAP     0x08
 153#define CLRSDONE     0x04
 154#define CLRSPIORDY   0x02
 155#define CLRDMADONE   0x01
 156
 157/* SCSI status 1 */
 158#define SELTO        0x80
 159#define ATNTARG      0x40
 160#define SCSIRSTI     0x20
 161#define PHASEMIS     0x10
 162#define BUSFREE      0x08
 163#define SCSIPERR     0x04
 164#define PHASECHG     0x02
 165#define REQINIT      0x01
 166
 167#define CLRSELTIMO   0x80
 168#define CLRATNO      0x40
 169#define CLRSCSIRSTI  0x20
 170#define CLRBUSFREE   0x08
 171#define CLRSCSIPERR  0x04
 172#define CLRPHASECHG  0x02
 173#define CLRREQINIT   0x01
 174
 175/* SCSI status 2 */
 176#define SOFFSET      0x20
 177#define SEMPTY       0x10
 178#define SFULL        0x08
 179#define SFCNT        0x07    /* mask */
 180
 181/* SCSI status 3 */
 182#define SCSICNT      0xf0    /* mask */
 183#define SCSICNT_     4
 184#define OFFCNT       0x0f    /* mask */
 185
 186/* SCSI TEST control */
 187#define SCTESTU      0x08
 188#define SCTESTD      0x04
 189#define STCTEST      0x01
 190
 191/* SCSI status 4 */
 192#define SYNCERR      0x04
 193#define FWERR        0x02
 194#define FRERR        0x01
 195
 196#define CLRSYNCERR   0x04
 197#define CLRFWERR     0x02
 198#define CLRFRERR     0x01
 199
 200/* SCSI interrupt mode 0 */
 201#define ENSELDO      0x40
 202#define ENSELDI      0x20
 203#define  104#define  105#define  106#define  107#define  108
 109/* SCSI interrupt mode 1 */
 110#define  111#define  112#define CLRSELTIMO" class="x.h">CLRS              0x20
 113#define  114#define  115#define CLRSCSIPERR" class="x.h">CLRSCYNCERR   0x04
 116#define  117#define  118
 119/* DMA control 0 */
 120#define  121#d_8BITTO        0x40
 122#define   23#define   24#define  125#define /EQINIT" class="sRSt">/YNCERR      0x02
  26#define  147
 138/* DMA control 1 */
  29#define   30#define /* mask */
 1/span>
 14)    /* DMA status */
  33#define  134#define   35#define   36#define /code=SFULL" class="+t">/code          0x10
  37#define /EMLRSWRAP" class="+t">/EMLRFRERR     0x08
 118
 119  40#define  141#define   72
  73 144#define  145#define  146#define        0x10
  47#define        0x08
 148#define        0x04
 149#define CBLe=STACK" class="s">CBLeYNCERR      0x02
 150#define BLe=STACK" class="t">BLeOFFCNT       0x01
 1/span>
 14)    /A* bit>O_TCI TESainrol */
  73 1type0
 135structv{/span>
 136 1:2;  0x07     136 1:1;  0xx07     136 1:1;  0xx07     136 1:2;  07    l */
 200l */
  61l */
 14)    l */
  63l */
 124 136 1:1;  0xx   07     136 1:1;  0xx   x07    /ntrol */
 136 1:3;  0xx   xx07    C-idontrol */
 136 1:2;  0x   xx07     136 1:2;  0x 4)    -Channel: 0=0, 1=5, 2=6, 3=7trol 1 */
 136 1:1;  0xx 07    C-parity: 1=enabledo0=disabledtrol 1 */
 131}define  1;/span>
 132un SCSeddshortdefine  1;/span>
 1}define  13;/span>
 174
  75#define  1.efine  174
 176#define  1.efine  174
 177#define  1.efine  174
 178#define  1.efine  174
 179#define  1.efine  174
 150#define  1.efine  174
 141#define SELTefine  1.efine  174
 182#define  1.efine  174
 183#define  1.efine  174
 184#define  174
 185
 186 147
 188#define SETPORT(SETPO,define SETPOT0) )
 189#define GETPORT(SETPOT0  0xx   xx0fine SETPO0) )
 140#define SETPO,define SETPOT0|     + (SETPOT0) )
  91#define SETPO,define SETPOT0) ~    + (SETPOT0) )
 192#define SETPO,define SETPOT0)     + ( 193#define SETPO,define SETPOT0)     + ( 174
  95#define SETPORT(CLATDMADONE" class="+">CLATDETPO,RT( 166
 19ifdefine  1enumv{/span>
 136efine  136= &1,/span>
 136efine  136efine  136efine  236efine  23= &10,/span>
 136efine  136efine  236efine  236efine  236efine  136efine  136efine  136efine  136efine SELTO
 1};/span>
 11endi 10
 185
 186 1structvefine  1;/span>
 1;/span>
 1;/span>
 1;/span>
 1;/span>
 1;/span>
 1;/span>
 1;/span>
 19ifdefine  1;/span>
  2endi 10
 1;/span>
 1};/span>
  72
  structvefine  1voiddefine   intx0fine  166
  3endi  07     13/pre13/div>


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