linux/drivers/pinctrl/pinctrl-sunxi.h
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   1/*
   2 * Allwinner A1X SoCs pinctrl driver.
   3 *
   4 * Copyright (C) 2012 Maxime Ripard
   5 *
   6 * Maxime Ripard <maxime.ripard@free-electrons.com>
   7 *
   8 * This file is licensed under the terms of the GNU General Public
   9 * License version 2.  This program is licensed "as is" without any
  10 * warranty of any kind, whether express or implied.
  11 */
  12
  13#ifndef __PINCTRL_SUNXI_H
  14#define __PINCTRL_SUNXI_H
  15
  16#include <linux/kernel.h>
  17#include <linux/spinlock.h>
  18
  19#define PA_BASE 0
  20#define PB_BASE 32
  21#define PC_BASE 64
  22#define PD_BASE 96
  23#define PE_BASE 128
  24#define PF_BASE 160
  25#define PG_BASE 192
  26#define PH_BASE 224
  27#define PI_BASE 256
  28
  29#define SUNXI_PINCTRL_PIN_PA0   PINCTRL_PIN(PA_BASE + 0, "PA0")
  30#define SUNXI_PINCTRL_PIN_PA1   PINCTRL_PIN(PA_BASE + 1, "PA1")
  31#define SUNXI_PINCTRL_PIN_PA2   PINCTRL_PIN(PA_BASE + 2, "PA2")
  32#define SUNXI_PINCTRL_PIN_PA3   PINCTRL_PIN(PA_BASE + 3, "PA3")
  33#define SUNXI_PINCTRL_PIN_PA4   PINCTRL_PIN(PA_BASE + 4, "PA4")
  34#define SUNXI_PINCTRL_PIN_PA5   PINCTRL_PIN(PA_BASE + 5, "PA5")
  35#define SUNXI_PINCTRL_PIN_PA6   PINCTRL_PIN(PA_BASE + 6, "PA6")
  36#define SUNXI_PINCTRL_PIN_PA7   PINCTRL_PIN(PA_BASE + 7, "PA7")
  37#define SUNXI_PINCTRL_PIN_PA8   PINCTRL_PIN(PA_BASE + 8, "PA8")
  38#define SUNXI_PINCTRL_PIN_PA9   PINCTRL_PIN(PA_BASE + 9, "PA9")
  39#define SUNXI_PINCTRL_PIN_PA10  PINCTRL_PIN(PA_BASE + 10, "PA10")
  40#define SUNXI_PINCTRL_PIN_PA11  PINCTRL_PIN(PA_BASE + 11, "PA11")
  41#define SUNXI_PINCTRL_PIN_PA12  PINCTRL_PIN(PA_BASE + 12, "PA12")
  42#define SUNXI_PINCTRL_PIN_PA13  PINCTRL_PIN(PA_BASE + 13, "PA13")
  43#define SUNXI_PINCTRL_PIN_PA14  PINCTRL_PIN(PA_BASE + 14, "PA14")
  44#define SUNXI_PINCTRL_PIN_PA15  PINCTRL_PIN(PA_BASE + 15, "PA15")
  45#define SUNXI_PINCTRL_PIN_PA16  PINCTRL_PIN(PA_BASE + 16, "PA16")
  46#define SUNXI_PINCTRL_PIN_PA17  PINCTRL_PIN(PA_BASE + 17, "PA17")
  47#define SUNXI_PINCTRL_PIN_PA18  PINCTRL_PIN(PA_BASE + 18, "PA18")
  48#define SUNXI_PINCTRL_PIN_PA19  PINCTRL_PIN(PA_BASE + 19, "PA19")
  49#define SUNXI_PINCTRL_PIN_PA20  PINCTRL_PIN(PA_BASE + 20, "PA20")
  50#define SUNXI_PINCTRL_PIN_PA21  PINCTRL_PIN(PA_BASE + 21, "PA21")
  51#define SUNXI_PINCTRL_PIN_PA22  PINCTRL_PIN(PA_BASE + 22, "PA22")
  52#define SUNXI_PINCTRL_PIN_PA23  PINCTRL_PIN(PA_BASE + 23, "PA23")
  53#define SUNXI_PINCTRL_PIN_PA24  PINCTRL_PIN(PA_BASE + 24, "PA24")
  54#define SUNXI_PINCTRL_PIN_PA25  PINCTRL_PIN(PA_BASE + 25, "PA25")
  55#define SUNXI_PINCTRL_PIN_PA26  PINCTRL_PIN(PA_BASE + 26, "PA26")
  56#define SUNXI_PINCTRL_PIN_PA27  PINCTRL_PIN(PA_BASE + 27, "PA27")
  57#define SUNXI_PINCTRL_PIN_PA28  PINCTRL_PIN(PA_BASE + 28, "PA28")
  58#define SUNXI_PINCTRL_PIN_PA29  PINCTRL_PIN(PA_BASE + 29, "PA29")
  59#define SUNXI_PINCTRL_PIN_PA30  PINCTRL_PIN(PA_BASE + 30, "PA30")
  60#define SUNXI_PINCTRL_PIN_PA31  PINCTRL_PIN(PA_BASE + 31, "PA31")
  61
  62#define SUNXI_PINCTRL_PIN_PB0   PINCTRL_PIN(PB_BASE + 0, "PB0")
  63#define SUNXI_PINCTRL_PIN_PB1   PINCTRL_PIN(PB_BASE + 1, "PB1")
  64#define SUNXI_PINCTRL_PIN_PB2   PINCTRL_PIN(PB_BASE + 2, "PB2")
  65#define SUNXI_PINCTRL_PIN_PB3   PINCTRL_PIN(PB_BASE + 3, "PB3")
  66#define SUNXI_PINCTRL_PIN_PB4   PINCTRL_PIN(PB_BASE + 4, "PB4")
  67#define SUNXI_PINCTRL_PIN_PB5   PINCTRL_PIN(PB_BASE + 5, "PB5")
  68#define SUNXI_PINCTRL_PIN_PB6   PINCTRL_PIN(PB_BASE + 6, "PB6")
  69#define SUNXI_PINCTRL_PIN_PB7   PINCTRL_PIN(PB_BASE + 7, "PB7")
  70#define SUNXI_PINCTRL_PIN_PB8   PINCTRL_PIN(PB_BASE + 8, "PB8")
  71#define SUNXI_PINCTRL_PIN_PB9   PINCTRL_PIN(PB_BASE + 9, "PB9")
  72#define SUNXI_PINCTRL_PIN_PB10  PINCTRL_PIN(PB_BASE + 10, "PB10")
  73#define SUNXI_PINCTRL_PIN_PB11  PINCTRL_PIN(PB_BASE + 11, "PB11")
  74#define SUNXI_PINCTRL_PIN_PB12  PINCTRL_PIN(PB_BASE + 12, "PB12")
  75#define SUNXI_PINCTRL_PIN_PB13  PINCTRL_PIN(PB_BASE + 13, "PB13")
  76#define SUNXI_PINCTRL_PIN_PB14  PINCTRL_PIN(PB_BASE + 14, "PB14")
  77#define SUNXI_PINCTRL_PIN_PB15  PINCTRL_PIN(PB_BASE + 15, "PB15")
  78#define SUNXI_PINCTRL_PIN_PB16  PINCTRL_PIN(PB_BASE + 16, "PB16")
  79#define SUNXI_PINCTRL_PIN_PB17  PINCTRL_PIN(PB_BASE + 17, "PB17")
  80#define SUNXI_PINCTRL_PIN_PB18  PINCTRL_PIN(PB_BASE + 18, "PB18")
  81#define SUNXI_PINCTRL_PIN_PB19  PINCTRL_PIN(PB_BASE + 19, "PB19")
  82#define SUNXI_PINCTRL_PIN_PB20  PINCTRL_PIN(PB_BASE + 20, "PB20")
  83#define SUNXI_PINCTRL_PIN_PB21  PINCTRL_PIN(PB_BASE + 21, "PB21")
  84#define SUNXI_PINCTRL_PIN_PB22  PINCTRL_PIN(PB_BASE + 22, "PB22")
  85#define SUNXI_PINCTRL_PIN_PB23  PINCTRL_PIN(PB_BASE + 23, "PB23")
  86#define SUNXI_PINCTRL_PIN_PB24  PINCTRL_PIN(PB_BASE + 24, "PB24")
  87#define SUNXI_PINCTRL_PIN_PB25  PINCTRL_PIN(PB_BASE + 25, "PB25")
  88#define SUNXI_PINCTRL_PIN_PB26  PINCTRL_PIN(PB_BASE + 26, "PB26")
  89#define SUNXI_PINCTRL_PIN_PB27  PINCTRL_PIN(PB_BASE + 27, "PB27")
  90#define SUNXI_PINCTRL_PIN_PB28  PINCTRL_PIN(PB_BASE + 28, "PB28")
  91#define SUNXI_PINCTRL_PIN_PB29  PINCTRL_PIN(PB_BASE + 29, "PB29")
  92#define SUNXI_PINCTRL_PIN_PB30  PINCTRL_PIN(PB_BASE + 30, "PB30")
  93#define SUNXI_PINCTRL_PIN_PB31  PINCTRL_PIN(PB_BASE + 31, "PB31")
  94
  95#define SUNXI_PINCTRL_PIN_PC0   PINCTRL_PIN(PC_BASE + 0, "PC0")
  96#define SUNXI_PINCTRL_PIN_PC1   PINCTRL_PIN(PC_BASE + 1, "PC1")
  97#define SUNXI_PINCTRL_PIN_PC2   PINCTRL_PIN(PC_BASE + 2, "PC2")
  98#define SUNXI_PINCTRL_PIN_PC3   PINCTRL_PIN(PC_BASE + 3, "PC3")
  99#define SUNXI_PINCTRL_PIN_PC4   PINCTRL_PIN(PC_BASE + 4, "PC4")
 100#define SUNXI_PINCTRL_PIN_PC5   PINCTRL_PIN(PC_BASE + 5, "PC5")
 101#define SUNXI_PINCTRL_PIN_PC6   PINCTRL_PIN(PC_BASE + 6, "PC6")
 102#define SUNXI_PINCTRL_PIN_PC7   PINCTRL_PIN(PC_BASE + 7, "PC7")
 103#define SUNXI_PINCTRL_PIN_PC8   PINCTRL_PIN(PC_BASE + 8, "PC8")
 104#define SUNXI_PINCTRL_PIN_PC9   PINCTRL_PIN(PC_BASE + 9, "PC9")
 105#define SUNXI_PINCTRL_PIN_PC10  PINCTRL_PIN(PC_BASE + 10, "PC10")
 106#define SUNXI_PINCTRL_PIN_PC11  PINCTRL_PIN(PC_BASE + 11, "PC11")
 107#define SUNXI_PINCTRL_PIN_PC12  PINCTRL_PIN(PC_BASE + 12, "PC12")
 108#define SUNXI_PINCTRL_PIN_PC13  PINCTRL_PIN(PC_BASE + 13, "PC13")
 109#define SUNXI_PINCTRL_PIN_PC14  PINCTRL_PIN(PC_BASE + 14, "PC14")
 110#define SUNXI_PINCTRL_PIN_PC15  PINCTRL_PIN(PC_BASE + 15, "PC15")
 111#define SUNXI_PINCTRL_PIN_PC16  PINCTRL_PIN(PC_BASE + 16, "PC16")
 112#define SUNXI_PINCTRL_PIN_PC17  PINCTRL_PIN(PC_BASE + 17, "PC17")
 113#define SUNXI_PINCTRL_PIN_PC18  PINCTRL_PIN(PC_BASE + 18, "PC18")
 114#define SUNXI_PINCTRL_PIN_PC19  PINCTRL_PIN(PC_BASE + 19, "PC19")
 115#define SUNXI_PINCTRL_PIN_PC20  PINCTRL_PIN(PC_BASE + 20, "PC20")
 116#define SUNXI_PINCTRL_PIN_PC21  PINCTRL_PIN(PC_BASE + 21, "PC21")
 117#define SUNXI_PINCTRL_PIN_PC22  PINCTRL_PIN(PC_BASE + 22, "PC22")
 118#define SUNXI_PINCTRL_PIN_PC23  PINCTRL_PIN(PC_BASE + 23, "PC23")
 119#define SUNXI_PINCTRL_PIN_PC24  PINCTRL_PIN(PC_BASE + 24, "PC24")
 120#define SUNXI_PINCTRL_PIN_PC25  PINCTRL_PIN(PC_BASE + 25, "PC25")
 121#define SUNXI_PINCTRL_PIN_PC26  PINCTRL_PIN(PC_BASE + 26, "PC26")
 122#define SUNXI_PINCTRL_PIN_PC27  PINCTRL_PIN(PC_BASE + 27, "PC27")
 123#define SUNXI_PINCTRL_PIN_PC28  PINCTRL_PIN(PC_BASE + 28, "PC28")
 124#define SUNXI_PINCTRL_PIN_PC29  PINCTRL_PIN(PC_BASE + 29, "PC29")
 125#define SUNXI_PINCTRL_PIN_PC30  PINCTRL_PIN(PC_BASE + 30, "PC30")
 126#define SUNXI_PINCTRL_PIN_PC31  PINCTRL_PIN(PC_BASE + 31, "PC31")
 127
 128#define SUNXI_PINCTRL_PIN_PD0   PINCTRL_PIN(PD_BASE + 0, "PD0")
 129#define SUNXI_PINCTRL_PIN_PD1   PINCTRL_PIN(PD_BASE + 1, "PD1")
 130#define SUNXI_PINCTRL_PIN_PD2   PINCTRL_PIN(PD_BASE + 2, "PD2")
 131#define SUNXI_PINCTRL_PIN_PD3   PINCTRL_PIN(PD_BASE + 3, "PD3")
 132#define SUNXI_PINCTRL_PIN_PD4   PINCTRL_PIN(PD_BASE + 4, "PD4")
 133#define SUNXI_PINCTRL_PIN_PD5   PINCTRL_PIN(PD_BASE + 5, "PD5")
 134#define SUNXI_PINCTRL_PIN_PD6   PINCTRL_PIN(PD_BASE + 6, "PD6")
 135#define SUNXI_PINCTRL_PIN_PD7   PINCTRL_PIN(PD_BASE + 7, "PD7")
 136#define SUNXI_PINCTRL_PIN_PD8   PINCTRL_PIN(PD_BASE + 8, "PD8")
 137#define SUNXI_PINCTRL_PIN_PD9   PINCTRL_PIN(PD_BASE + 9, "PD9")
 138#define SUNXI_PINCTRL_PIN_PD10  PINCTRL_PIN(PD_BASE + 10, "PD10")
 139#define SUNXI_PINCTRL_PIN_PD11  PINCTRL_PIN(PD_BASE + 11, "PD11")
 140#define SUNXI_PINCTRL_PIN_PD12  PINCTRL_PIN(PD_BASE + 12, "PD12")
 141#define SUNXI_PINCTRL_PIN_PD13  PINCTRL_PIN(PD_BASE + 13, "PD13")
 142#define SUNXI_PINCTRL_PIN_PD14  PINCTRL_PIN(PD_BASE + 14, "PD14")
 143#define SUNXI_PINCTRL_PIN_PD15  PINCTRL_PIN(PD_BASE + 15, "PD15")
 144#define SUNXI_PINCTRL_PIN_PD16  PINCTRL_PIN(PD_BASE + 16, "PD16")
 145#define SUNXI_PINCTRL_PIN_PD17  PINCTRL_PIN(PD_BASE + 17, "PD17")
 146#define SUNXI_PINCTRL_PIN_PD18  PINCTRL_PIN(PD_BASE + 18, "PD18")
 147#define SUNXI_PINCTRL_PIN_PD19  PINCTRL_PIN(PD_BASE + 19, "PD19")
 148#define SUNXI_PINCTRL_PIN_PD20  PINCTRL_PIN(PD_BASE + 20, "PD20")
 149#define SUNXI_PINCTRL_PIN_PD21  PINCTRL_PIN(PD_BASE + 21, "PD21")
 150#define SUNXI_PINCTRL_PIN_PD22  PINCTRL_PIN(PD_BASE + 22, "PD22")
 151#define SUNXI_PINCTRL_PIN_PD23  PINCTRL_PIN(PD_BASE + 23, "PD23")
 152#define SUNXI_PINCTRL_PIN_PD24  PINCTRL_PIN(PD_BASE + 24, "PD24")
 153#define SUNXI_PINCTRL_PIN_PD25  PINCTRL_PIN(PD_BASE + 25, "PD25")
 154#define SUNXI_PINCTRL_PIN_PD26  PINCTRL_PIN(PD_BASE + 26, "PD26")
 155#define SUNXI_PINCTRL_PIN_PD27  PINCTRL_PIN(PD_BASE + 27, "PD27")
 156#define SUNXI_PINCTRL_PIN_PD28  PINCTRL_PIN(PD_BASE + 28, "PD28")
 157#define SUNXI_PINCTRL_PIN_PD29  PINCTRL_PIN(PD_BASE + 29, "PD29")
 158#define SUNXI_PINCTRL_PIN_PD30  PINCTRL_PIN(PD_BASE + 30, "PD30")
 159#define SUNXI_PINCTRL_PIN_PD31  PINCTRL_PIN(PD_BASE + 31, "PD31")
 160
 161#define SUNXI_PINCTRL_PIN_PE0   PINCTRL_PIN(PE_BASE + 0, "PE0")
 162#define SUNXI_PINCTRL_PIN_PE1   PINCTRL_PIN(PE_BASE + 1, "PE1")
 163#define SUNXI_PINCTRL_PIN_PE2   PINCTRL_PIN(PE_BASE + 2, "PE2")
 164#define SUNXI_PINCTRL_PIN_PE3   PINCTRL_PIN(PE_BASE + 3, "PE3")
 165#define SUNXI_PINCTRL_PIN_PE4   PINCTRL_PIN(PE_BASE + 4, "PE4")
 166#define SUNXI_PINCTRL_PIN_PE5   PINCTRL_PIN(PE_BASE + 5, "PE5")
 167#define SUNXI_PINCTRL_PIN_PE6   PINCTRL_PIN(PE_BASE + 6, "PE6")
 168#define SUNXI_PINCTRL_PIN_PE7   PINCTRL_PIN(PE_BASE + 7, "PE7")
 169#define SUNXI_PINCTRL_PIN_PE8   PINCTRL_PIN(PE_BASE + 8, "PE8")
 170#define SUNXI_PINCTRL_PIN_PE9   PINCTRL_PIN(PE_BASE + 9, "PE9")
 171#define SUNXI_PINCTRL_PIN_PE10  PINCTRL_PIN(PE_BASE + 10, "PE10")
 172#define SUNXI_PINCTRL_PIN_PE11  PINCTRL_PIN(PE_BASE + 11, "PE11")
 173#define SUNXI_PINCTRL_PIN_PE12  PINCTRL_PIN(PE_BASE + 12, "PE12")
 174#define SUNXI_PINCTRL_PIN_PE13  PINCTRL_PIN(PE_BASE + 13, "PE13")
 175#define SUNXI_PINCTRL_PIN_PE14  PINCTRL_PIN(PE_BASE + 14, "PE14")
 176#define SUNXI_PINCTRL_PIN_PE15  PINCTRL_PIN(PE_BASE + 15, "PE15")
 177#define SUNXI_PINCTRL_PIN_PE16  PINCTRL_PIN(PE_BASE + 16, "PE16")
 178#define SUNXI_PINCTRL_PIN_PE17  PINCTRL_PIN(PE_BASE + 17, "PE17")
 179#define SUNXI_PINCTRL_PIN_PE18  PINCTRL_PIN(PE_BASE + 18, "PE18")
 180#define SUNXI_PINCTRL_PIN_PE19  PINCTRL_PIN(PE_BASE + 19, "PE19")
 181#define SUNXI_PINCTRL_PIN_PE20  PINCTRL_PIN(PE_BASE + 20, "PE20")
 182#define SUNXI_PINCTRL_PIN_PE21  PINCTRL_PIN(PE_BASE + 21, "PE21")
 183#define SUNXI_PINCTRL_PIN_PE22  PINCTRL_PIN(PE_BASE + 22, "PE22")
 184#define SUNXI_PINCTRL_PIN_PE23  PINCTRL_PIN(PE_BASE + 23, "PE23")
 185#define SUNXI_PINCTRL_PIN_PE24  PINCTRL_PIN(PE_BASE + 24, "PE24")
 186#define SUNXI_PINCTRL_PIN_PE25  PINCTRL_PIN(PE_BASE + 25, "PE25")
 187#define SUNXI_PINCTRL_PIN_PE26  PINCTRL_PIN(PE_BASE + 26, "PE26")
 188#define SUNXI_PINCTRL_PIN_PE27  PINCTRL_PIN(PE_BASE + 27, "PE27")
 189#define SUNXI_PINCTRL_PIN_PE28  PINCTRL_PIN(PE_BASE + 28, "PE28")
 190#define SUNXI_PINCTRL_PIN_PE29  PINCTRL_PIN(PE_BASE + 29, "PE29")
 191#define SUNXI_PINCTRL_PIN_PE30  PINCTRL_PIN(PE_BASE + 30, "PE30")
 192#define SUNXI_PINCTRL_PIN_PE31  PINCTRL_PIN(PE_BASE + 31, "PE31")
 193
 194#define SUNXI_PINCTRL_PIN_PF0   PINCTRL_PIN(PF_BASE + 0, "PF0")
 195#define SUNXI_PINCTRL_PIN_PF1   PINCTRL_PIN(PF_BASE + 1, "PF1")
 196#define SUNXI_PINCTRL_PIN_PF2   PINCTRL_PIN(PF_BASE + 2, "PF2")
 197#define SUNXI_PINCTRL_PIN_PF3   PINCTRL_PIN(PF_BASE + 3, "PF3")
 198#define SUNXI_PINCTRL_PIN_PF4   PINCTRL_PIN(PF_BASE + 4, "PF4")
 199#define SUNXI_PINCTRL_PIN_PF5   PINCTRL_PIN(PF_BASE + 5, "PF5")
 200#define SUNXI_PINCTRL_PIN_PF6   PINCTRL_PIN(PF_BASE + 6, "PF6")
 201#define SUNXI_PINCTRL_PIN_PF7   PINCTRL_PIN(PF_BASE + 7, "PF7")
 202#define SUNXI_PINCTRL_PIN_PF8   PINCTRL_PIN(PF_BASE + 8, "PF8")
 203#define SUNXI_PINCTRL_PIN_PF9   PINCTRL_PIN(PF_BASE + 9, "PF9")
 204#define SUNXI_PINCTRL_PIN_PF10  PINCTRL_PIN(PF_BASE + 10, "PF10")
 205#define SUNXI_PINCTRL_PIN_PF11  PINCTRL_PIN(PF_BASE + 11, "PF11")
 206#define SUNXI_PINCTRL_PIN_PF12  PINCTRL_PIN(PF_BASE + 12, "PF12")
 207#define SUNXI_PINCTRL_PIN_PF13  PINCTRL_PIN(PF_BASE + 13, "PF13")
 208#define SUNXI_PINCTRL_PIN_PF14  PINCTRL_PIN(PF_BASE + 14, "PF14")
 209#define SUNXI_PINCTRL_PIN_PF15  PINCTRL_PIN(PF_BASE + 15, "PF15")
 210#define SUNXI_PINCTRL_PIN_PF16  PINCTRL_PIN(PF_BASE + 16, "PF16")
 211#define SUNXI_PINCTRL_PIN_PF17  PINCTRL_PIN(PF_BASE + 17, "PF17")
 212#define SUNXI_PINCTRL_PIN_PF18  PINCTRL_PIN(PF_BASE + 18, "PF18")
 213#define SUNXI_PINCTRL_PIN_PF19  PINCTRL_PIN(PF_BASE + 19, "PF19")
 214#define SUNXI_PINCTRL_PIN_PF20  PINCTRL_PIN(PF_BASE + 20, "PF20")
 215#define SUNXI_PINCTRL_PIN_PF21  PINCTRL_PIN(PF_BASE + 21, "PF21")
 216#define SUNXI_PINCTRL_PIN_PF22  PINCTRL_PIN(PF_BASE + 22, "PF22")
 217#define SUNXI_PINCTRL_PIN_PF23  PINCTRL_PIN(PF_BASE + 23, "PF23")
 218#define SUNXI_PINCTRL_PIN_PF24  PINCTRL_PIN(PF_BASE + 24, "PF24")
 219#define SUNXI_PINCTRL_PIN_PF25  PINCTRL_PIN(PF_BASE + 25, "PF25")
 220#define SUNXI_PINCTRL_PIN_PF26  PINCTRL_PIN(PF_BASE + 26, "PF26")
 221#define SUNXI_PINCTRL_PIN_PF27  PINCTRL_PIN(PF_BASE + 27, "PF27")
 222#define SUNXI_PINCTRL_PIN_PF28  PINCTRL_PIN(PF_BASE + 28, "PF28")
 223#define SUNXI_PINCTRL_PIN_PF29  PINCTRL_PIN(PF_BASE + 29, "PF29")
 224#define SUNXI_PINCTRL_PIN_PF30  PINCTRL_PIN(PF_BASE + 30, "PF30")
 225#define SUNXI_PINCTRL_PIN_PF31  PINCTRL_PIN(PF_BASE + 31, "PF31")
 226
 227#define SUNXI_PINCTRL_PIN_PG0   PINCTRL_PIN(PG_BASE + 0, "PG0")
 228#define SUNXI_PINCTRL_PIN_PG1   PINCTRL_PIN(PG_BASE + 1, "PG1")
 229#define SUNXI_PINCTRL_PIN_PG2   PINCTRL_PIN(PG_BASE + 2, "PG2")
 230#define SUNXI_PINCTRL_PIN_PG3   PINCTRL_PIN(PG_BASE + 3, "PG3")
 231#define SUNXI_PINCTRL_PIN_PG4   PINCTRL_PIN(PG_BASE + 4, "PG4")
 232#define SUNXI_PINCTRL_PIN_PG5   PINCTRL_PIN(PG_BASE + 5, "PG5")
 233#define SUNXI_PINCTRL_PIN_PG6   PINCTRL_PIN(PG_BASE + 6, "PG6")
 234#define SUNXI_PINCTRL_PIN_PG7   PINCTRL_PIN(PG_BASE + 7, "PG7")
 235#define SUNXI_PINCTRL_PIN_PG8   PINCTRL_PIN(PG_BASE + 8, "PG8")
 236#define SUNXI_PINCTRL_PIN_PG9   PINCTRL_PIN(PG_BASE + 9, "PG9")
 237#define SUNXI_PINCTRL_PIN_PG10  PINCTRL_PIN(PG_BASE + 10, "PG10")
 238#define SUNXI_PINCTRL_PIN_PG11  PINCTRL_PIN(PG_BASE + 11, "PG11")
 239#define SUNXI_PINCTRL_PIN_PG12  PINCTRL_PIN(PG_BASE + 12, "PG12")
 240#define SUNXI_PINCTRL_PIN_PG13  PINCTRL_PIN(PG_BASE + 13, "PG13")
 241#define SUNXI_PINCTRL_PIN_PG14  PINCTRL_PIN(PG_BASE + 14, "PG14")
 242#define SUNXI_PINCTRL_PIN_PG15  PINCTRL_PIN(PG_BASE + 15, "PG15")
 243#define SUNXI_PINCTRL_PIN_PG16  PINCTRL_PIN(PG_BASE + 16, "PG16")
 244#define SUNXI_PINCTRL_PIN_PG17  PINCTRL_PIN(PG_BASE + 17, "PG17")
 245#define SUNXI_PINCTRL_PIN_PG18  PINCTRL_PIN(PG_BASE + 18, "PG18")
 246#define SUNXI_PINCTRL_PIN_PG19  PINCTRL_PIN(PG_BASE + 19, "PG19")
 247#define SUNXI_PINCTRL_PIN_PG20  PINCTRL_PIN(PG_BASE + 20, "PG20")
 248#define SUNXI_PINCTRL_PIN_PG21  PINCTRL_PIN(PG_BASE + 21, "PG21")
 249#define SUNXI_PINCTRL_PIN_PG22  PINCTRL_PIN(PG_BASE + 22, "PG22")
 250#define SUNXI_PINCTRL_PIN_PG23  PINCTRL_PIN(PG_BASE + 23, "PG23")
 251#define SUNXI_PINCTRL_PIN_PG24  PINCTRL_PIN(PG_BASE + 24, "PG24")
 252#define SUNXI_PINCTRL_PIN_PG25  PINCTRL_PIN(PG_BASE + 25, "PG25")
 253#define SUNXI_PINCTRL_PIN_PG26  PINCTRL_PIN(PG_BASE + 26, "PG26")
 254#define SUNXI_PINCTRL_PIN_PG27  PINCTRL_PIN(PG_BASE + 27, "PG27")
 255#define SUNXI_PINCTRL_PIN_PG28  PINCTRL_PIN(PG_BASE + 28, "PG28")
 256#define SUNXI_PINCTRL_PIN_PG29  PINCTRL_PIN(PG_BASE + 29, "PG29")
 257#define SUNXI_PINCTRL_PIN_PG30  PINCTRL_PIN(PG_BASE + 30, "PG30")
 258#define SUNXI_PINCTRL_PIN_PG31  PINCTRL_PIN(PG_BASE + 31, "PG31")
 259
 260#define SUNXI_PINCTRL_PIN_PH0   PINCTRL_PIN(PH_BASE + 0, "PH0")
 261#define SUNXI_PINCTRL_PIN_PH1   PINCTRL_PIN(PH_BASE + 1, "PH1")
 262#define SUNXI_PINCTRL_PIN_PH2   PINCTRL_PIN(PH_BASE + 2, "PH2")
 263#define SUNXI_PINCTRL_PIN_PH3   PINCTRL_PIN(PH_BASE + 3, "PH3")
 264#define SUNXI_PINCTRL_PIN_PH4   PINCTRL_PIN(PH_BASE + 4, "PH4")
 265#define SUNXI_PINCTRL_PIN_PH5   PINCTRL_PIN(PH_BASE + 5, "PH5")
 266#define SUNXI_PINCTRL_PIN_PH6   PINCTRL_PIN(PH_BASE + 6, "PH6")
 267#define SUNXI_PINCTRL_PIN_PH7   PINCTRL_PIN(PH_BASE + 7, "PH7")
 268#define SUNXI_PINCTRL_PIN_PH8   PINCTRL_PIN(PH_BASE + 8, "PH8")
 269#define SUNXI_PINCTRL_PIN_PH9   PINCTRL_PIN(PH_BASE + 9, "PH9")
 270#define SUNXI_PINCTRL_PIN_PH10  PINCTRL_PIN(PH_BASE + 10, "PH10")
 271#define SUNXI_PINCTRL_PIN_PH11  PINCTRL_PIN(PH_BASE + 11, "PH11")
 272#define SUNXI_PINCTRL_PIN_PH12  PINCTRL_PIN(PH_BASE + 12, "PH12")
 273#define SUNXI_PINCTRL_PIN_PH13  PINCTRL_PIN(PH_BASE + 13, "PH13")
 274#define SUNXI_PINCTRL_PIN_PH14  PINCTRL_PIN(PH_BASE + 14, "PH14")
 275#define SUNXI_PINCTRL_PIN_PH15  PINCTRL_PIN(PH_BASE + 15, "PH15")
 276#define SUNXI_PINCTRL_PIN_PH16  PINCTRL_PIN(PH_BASE + 16, "PH16")
 277#define SUNXI_PINCTRL_PIN_PH17  PINCTRL_PIN(PH_BASE + 17, "PH17")
 278#define SUNXI_PINCTRL_PIN_PH18  PINCTRL_PIN(PH_BASE + 18, "PH18")
 279#define SUNXI_PINCTRL_PIN_PH19  PINCTRL_PIN(PH_BASE + 19, "PH19")
 280#define SUNXI_PINCTRL_PIN_PH20  PINCTRL_PIN(PH_BASE + 20, "PH20")
 281#define SUNXI_PINCTRL_PIN_PH21  PINCTRL_PIN(PH_BASE + 21, "PH21")
 282#define SUNXI_PINCTRL_PIN_PH22  PINCTRL_PIN(PH_BASE + 22, "PH22")
 283#define SUNXI_PINCTRL_PIN_PH23  PINCTRL_PIN(PH_BASE + 23, "PH23")
 284#define SUNXI_PINCTRL_PIN_PH24  PINCTRL_PIN(PH_BASE + 24, "PH24")
 285#define SUNXI_PINCTRL_PIN_PH25  PINCTRL_PIN(PH_BASE + 25, "PH25")
 286#define SUNXI_PINCTRL_PIN_PH26  PINCTRL_PIN(PH_BASE + 26, "PH26")
 287#define SUNXI_PINCTRL_PIN_PH27  PINCTRL_PIN(PH_BASE + 27, "PH27")
 288#define SUNXI_PINCTRL_PIN_PH28  PINCTRL_PIN(PH_BASE + 28, "PH28")
 289#define SUNXI_PINCTRL_PIN_PH29  PINCTRL_PIN(PH_BASE + 29, "PH29")
 290#define SUNXI_PINCTRL_PIN_PH30  PINCTRL_PIN(PH_BASE + 30, "PH30")
 291#define SUNXI_PINCTRL_PIN_PH31  PINCTRL_PIN(PH_BASE + 31, "PH31")
 292
 293#define SUNXI_PINCTRL_PIN_PI0   PINCTRL_PIN(PI_BASE + 0, "PI0")
 294#define SUNXI_PINCTRL_PIN_PI1   PINCTRL_PIN(PI_BASE + 1, "PI1")
 295#define SUNXI_PINCTRL_PIN_PI2   PINCTRL_PIN(PI_BASE + 2, "PI2")
 296#define SUNXI_PINCTRL_PIN_PI3   PINCTRL_PIN(PI_BASE + 3, "PI3")
 297#define SUNXI_PINCTRL_PIN_PI4   PINCTRL_PIN(PI_BASE + 4, "PI4")
 298#define SUNXI_PINCTRL_PIN_PI5   PINCTRL_PIN(PI_BASE + 5, "PI5")
 299#define SUNXI_PINCTRL_PIN_PI6   PINCTRL_PIN(PI_BASE + 6, "PI6")
 300#define SUNXI_PINCTRL_PIN_PI7   PINCTRL_PIN(PI_BASE + 7, "PI7")
 301#define SUNXI_PINCTRL_PIN_PI8   PINCTRL_PIN(PI_BASE + 8, "PI8")
 302#define SUNXI_PINCTRL_PIN_PI9   PINCTRL_PIN(PI_BASE + 9, "PI9")
 303#define SUNXI_PINCTRL_PIN_PI10  PINCTRL_PIN(PI_BASE + 10, "PI10")
 304#define SUNXI_PINCTRL_PIN_PI11  PINCTRL_PIN(PI_BASE + 11, "PI11")
 305#define SUNXI_PINCTRL_PIN_PI12  PINCTRL_PIN(PI_BASE + 12, "PI12")
 306#define SUNXI_PINCTRL_PIN_PI13  PINCTRL_PIN(PI_BASE + 13, "PI13")
 307#define SUNXI_PINCTRL_PIN_PI14  PINCTRL_PIN(PI_BASE + 14, "PI14")
 308#define SUNXI_PINCTRL_PIN_PI15  PINCTRL_PIN(PI_BASE + 15, "PI15")
 309#define SUNXI_PINCTRL_PIN_PI16  PINCTRL_PIN(PI_BASE + 16, "PI16")
 310#define SUNXI_PINCTRL_PIN_PI17  PINCTRL_PIN(PI_BASE + 17, "PI17")
 311#define SUNXI_PINCTRL_PIN_PI18  PINCTRL_PIN(PI_BASE + 18, "PI18")
 312#define SUNXI_PINCTRL_PIN_PI19  PINCTRL_PIN(PI_BASE + 19, "PI19")
 313#define SUNXI_PINCTRL_PIN_PI20  PINCTRL_PIN(PI_BASE + 20, "PI20")
 314#define SUNXI_PINCTRL_PIN_PI21  PINCTRL_PIN(PI_BASE + 21, "PI21")
 315#define SUNXI_PINCTRL_PIN_PI22  PINCTRL_PIN(PI_BASE + 22, "PI22")
 316#define SUNXI_PINCTRL_PIN_PI23  PINCTRL_PIN(PI_BASE + 23, "PI23")
 317#define SUNXI_PINCTRL_PIN_PI24  PINCTRL_PIN(PI_BASE + 24, "PI24")
 318#define SUNXI_PINCTRL_PIN_PI25  PINCTRL_PIN(PI_BASE + 25, "PI25")
 319#define SUNXI_PINCTRL_PIN_PI26  PINCTRL_PIN(PI_BASE + 26, "PI26")
 320#define SUNXI_PINCTRL_PIN_PI27  PINCTRL_PIN(PI_BASE + 27, "PI27")
 321#define SUNXI_PINCTRL_PIN_PI28  PINCTRL_PIN(PI_BASE + 28, "PI28")
 322#define SUNXI_PINCTRL_PIN_PI29  PINCTRL_PIN(PI_BASE + 29, "PI29")
 323#define SUNXI_PINCTRL_PIN_PI30  PINCTRL_PIN(PI_BASE + 30, "PI30")
 324#define SUNXI_PINCTRL_PIN_PI31  PINCTRL_PIN(PI_BASE + 31, "PI31")
 325
 326#define SUNXI_PIN_NAME_MAX_LEN  5
 327
 328#define BANK_MEM_SIZE           0x24
 329#define MUX_REGS_OFFSET         0x0
 330#define DATA_REGS_OFFSET        0x10
 331#define DLEVEL_REGS_OFFSET      0x14
 332#define PULL_REGS_OFFSET        0x1c
 333
 334#define PINS_PER_BANK           32
 335#define MUX_PINS_PER_REG        8
 336#define MUX_PINS_BITS           4
 337#define MUX_PINS_MASK           0x0f
 338#define DATA_PINS_PER_REG       32
 339#define DATA_PINS_BITS          1
 340#define DATA_PINS_MASK          0x01
 341#define DLEVEL_PINS_PER_REG     16
 342#define DLEVEL_PINS_BITS        2
 343#define DLEVEL_PINS_MASK        0x03
 344#define PULL_PINS_PER_REG       16
 345#define PULL_PINS_BITS          2
 346#define PULL_PINS_MASK          0x03
 347
 348#define SUNXI_IRQ_NUMBER        32
 349
 350#define IRQ_CFG_REG             0x200
 351#define IRQ_CFG_IRQ_PER_REG             8
 352#define IRQ_CFG_IRQ_BITS                4
 353#define IRQ_CFG_IRQ_MASK                ((1 << IRQ_CFG_IRQ_BITS) - 1)
 354#define IRQ_CTRL_REG            0x210
 355#define IRQ_CTRL_IRQ_PER_REG            32
 356#define IRQ_CTRL_IRQ_BITS               1
 357#define IRQ_CTRL_IRQ_MASK               ((1 << IRQ_CTRL_IRQ_BITS) - 1)
 358#define IRQ_STATUS_REG          0x214
 359#define IRQ_STATUS_IRQ_PER_REG          32
 360#define IRQ_STATUS_IRQ_BITS             1
 361#define IRQ_STATUS_IRQ_MASK             ((1 << IRQ_STATUS_IRQ_BITS) - 1)
 362
 363#define IRQ_EDGE_RISING         0x00
 364#define IRQ_EDGE_FALLING        0x01
 365#define IRQ_LEVEL_HIGH          0x02
 366#define IRQ_LEVEL_LOW           0x03
 367#define IRQ_EDGE_BOTH           0x04
 368
 369struct sunxi_desc_function {
 370        const char      *name;
 371        u8              muxval;
 372        u8              irqnum;
 373};
 374
 375struct sunxi_desc_pin {
 376        struct pinctrl_pin_desc         pin;
 377        struct sunxi_desc_function      *functions;
 378};
 379
 380struct sunxi_pinctrl_desc {
 381        const struct sunxi_desc_pin     *pins;
 382        int                             npins;
 383        struct pinctrl_gpio_range       *ranges;
 384        int                             nranges;
 385};
 386
 387struct sunxi_pinctrl_function {
 388        const char      *name;
 389        const char      **groups;
 390        unsigned        ngroups;
 391};
 392
 393struct sunxi_pinctrl_group {
 394        const char      *name;
 395        unsigned long   config;
 396        unsigned        pin;
 397};
 398
 399struct sunxi_pinctrl {
 400        void __iomem                    *membase;
 401        struct gpio_chip                *chip;
 402        struct sunxi_pinctrl_desc       *desc;
 403        struct device                   *dev;
 404        struct irq_domain               *domain;
 405        struct sunxi_pinctrl_function   *functions;
 406        unsigned                        nfunctions;
 407        struct sunxi_pinctrl_group      *groups;
 408        unsigned                        ngroups;
 409        int                             irq;
 410        int                             irq_array[SUNXI_IRQ_NUMBER];
 411        spinlock_t                      lock;
 412        struct pinctrl_dev              *pctl_dev;
 413};
 414
 415#define SUNXI_PIN(_pin, ...)                                    \
 416        {                                                       \
 417                .pin = _pin,                                    \
 418                .functions = (struct sunxi_desc_function[]){    \
 419                        __VA_ARGS__, { } },                     \
 420        }
 421
 422#define SUNXI_FUNCTION(_val, _name)                             \
 423        {                                                       \
 424                .name = _name,                                  \
 425                .muxval = _val,                                 \
 426        }
 427
 428#define SUNXI_FUNCTION_IRQ(_val, _irq)                          \
 429        {                                                       \
 430                .name = "irq",                                  \
 431                .muxval = _val,                                 \
 432                .irqnum = _irq,                                 \
 433        }
 434
 435/*
 436 * The sunXi PIO registers are organized as is:
 437 * 0x00 - 0x0c  Muxing values.
 438 *              8 pins per register, each pin having a 4bits value
 439 * 0x10         Pin values
 440 *              32 bits per register, each pin corresponding to one bit
 441 * 0x14 - 0x18  Drive level
 442 *              16 pins per register, each pin having a 2bits value
 443 * 0x1c - 0x20  Pull-Up values
 444 *              16 pins per register, each pin having a 2bits value
 445 *
 446 * This is for the first bank. Each bank will have the same layout,
 447 * with an offset being a multiple of 0x24.
 448 *
 449 * The following functions calculate from the pin number the register
 450 * and the bit offset that we should access.
 451 */
 452static inline u32 sunxi_mux_reg(u16 pin)
 453{
 454        u8 bank = pin / PINS_PER_BANK;
 455        u32 offset = bank * BANK_MEM_SIZE;
 456        offset += MUX_REGS_OFFSET;
 457        offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
 458        return round_down(offset, 4);
 459}
 460
 461static inline u32 sunxi_mux_offset(u16 pin)
 462{
 463        u32 pin_num = pin % MUX_PINS_PER_REG;
 464        return pin_num * MUX_PINS_BITS;
 465}
 466
 467static inline u32 sunxi_data_reg(u16 pin)
 468{
 469        u8 bank = pin / PINS_PER_BANK;
 470        u32 offset = bank * BANK_MEM_SIZE;
 471        offset += DATA_REGS_OFFSET;
 472        offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
 473        return round_down(offset, 4);
 474}
 475
 476static inline u32 sunxi_data_offset(u16 pin)
 477{
 478        u32 pin_num = pin % DATA_PINS_PER_REG;
 479        return pin_num * DATA_PINS_BITS;
 480}
 481
 482static inline u32 sunxi_dlevel_reg(u16 pin)
 483{
 484        u8 bank = pin / PINS_PER_BANK;
 485        u32 offset = bank * BANK_MEM_SIZE;
 486        offset += DLEVEL_REGS_OFFSET;
 487        offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
 488        return round_down(offset, 4);
 489}
 490
 491static inline u32 sunxi_dlevel_offset(u16 pin)
 492{
 493        u32 pin_num = pin % DLEVEL_PINS_PER_REG;
 494        return pin_num * DLEVEL_PINS_BITS;
 495}
 496
 497static inline u32 sunxi_pull_reg(u16 pin)
 498{
 499        u8 bank = pin / PINS_PER_BANK;
 500        u32 offset = bank * BANK_MEM_SIZE;
 501        offset += PULL_REGS_OFFSET;
 502        offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
 503        return round_down(offset, 4);
 504}
 505
 506static inline u32 sunxi_pull_offset(u16 pin)
 507{
 508        u32 pin_num = pin % PULL_PINS_PER_REG;
 509        return pin_num * PULL_PINS_BITS;
 510}
 511
 512static inline u32 sunxi_irq_cfg_reg(u16 irq)
 513{
 514        u8 reg = irq / IRQ_CFG_IRQ_PER_REG;
 515        return reg + IRQ_CFG_REG;
 516}
 517
 518static inline u32 sunxi_irq_cfg_offset(u16 irq)
 519{
 520        u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
 521        return irq_num * IRQ_CFG_IRQ_BITS;
 522}
 523
 524static inline u32 sunxi_irq_ctrl_reg(u16 irq)
 525{
 526        u8 reg = irq / IRQ_CTRL_IRQ_PER_REG;
 527        return reg + IRQ_CTRL_REG;
 528}
 529
 530static inline u32 sunxi_irq_ctrl_offset(u16 irq)
 531{
 532        u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
 533        return irq_num * IRQ_CTRL_IRQ_BITS;
 534}
 535
 536static inline u32 sunxi_irq_status_reg(u16 irq)
 537{
 538        u8 reg = irq / IRQ_STATUS_IRQ_PER_REG;
 539        return reg + IRQ_STATUS_REG;
 540}
 541
 542static inline u32 sunxi_irq_status_offset(u16 irq)
 543{
 544        u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
 545        return irq_num * IRQ_STATUS_IRQ_BITS;
 546}
 547
 548#endif /* __PINCTRL_SUNXI_H */
 549
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