linux/drivers/pinctrl/pinctrl-rockchip.c
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   1/*
   2 * Pinctrl driver for Rockchip SoCs
   3 *
   4 * Copyright (c) 2013 MundoReader S.L.
   5 * Author: Heiko Stuebner <heiko@sntech.de>
   6 *
   7 * With some ideas taken from pinctrl-samsung:
   8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9 *              http://www.samsung.com
  10 * Copyright (c) 2012 Linaro Ltd
  11 *              http://www.linaro.org
  12 *
  13 * and pinctrl-at91:
  14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15 *
  16 * This program is free software; you can redistribute it and/or modify
  17 * it under the terms of the GNU General Public License version 2 as published
  18 * by the Free Software Foundation.
  19 *
  20 * This program is distributed in the hope that it will be useful,
  21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23 * GNU General Public License for more details.
  24 */
  25
  26#include <linux/module.h>
  27#include <linux/platform_device.h>
  28#include <linux/io.h>
  29#include <linux/bitops.h>
  30#include <linux/gpio.h>
  31#include <linux/of_address.h>
  32#include <linux/of_irq.h>
  33#include <linux/pinctrl/machine.h>
  34#include <linux/pinctrl/pinconf.h>
  35#include <linux/pinctrl/pinctrl.h>
  36#include <linux/pinctrl/pinmux.h>
  37#include <linux/pinctrl/pinconf-generic.h>
  38#include <linux/irqchip/chained_irq.h>
  39#include <linux/clk-provider.h>
  40#include <dt-bindings/pinctrl/rockchip.h>
  41
  42#include "core.h"
  43#include "pinconf.h"
  44
  45/* GPIO control registers */
  46#define GPIO_SWPORT_DR          0x00
  47#define GPIO_SWPORT_DDR         0x04
  48#define GPIO_INTEN              0x30
  49#define GPIO_INTMASK            0x34
  50#define GPIO_INTTYPE_LEVEL      0x38
  51#define GPIO_INT_POLARITY       0x3c
  52#define GPIO_INT_STATUS         0x40
  53#define GPIO_INT_RAWSTATUS      0x44
  54#define GPIO_DEBOUNCE           0x48
  55#define GPIO_PORTS_EOI          0x4c
  56#define GPIO_EXT_PORT           0x50
  57#define GPIO_LS_SYNC            0x60
  58
  59/**
  60 * @reg_base: register base of the gpio bank
  61 * @clk: clock of the gpio bank
  62 * @irq: interrupt of the gpio bank
  63 * @pin_base: first pin number
  64 * @nr_pins: number of pins in this bank
  65 * @name: name of the bank
  66 * @bank_num: number of the bank, to account for holes
  67 * @valid: are all necessary informations present
  68 * @of_node: dt node of this bank
  69 * @drvdata: common pinctrl basedata
  70 * @domain: irqdomain of the gpio bank
  71 * @gpio_chip: gpiolib chip
  72 * @grange: gpio range
  73 * @slock: spinlock for the gpio bank
  74 */
  75struct rockchip_pin_bank {
  76        void __iomem                    *reg_base;
  77        struct clk                      *clk;
  78        int                             irq;
  79        u32                             pin_base;
  80        u8                              nr_pins;
  81        char                            *name;
  82        u8                              bank_num;
  83        bool                            valid;
  84        struct device_node              *of_node;
  85        struct rockchip_pinctrl         *drvdata;
  86        struct irq_domain               *domain;
  87        struct gpio_chip                gpio_chip;
  88        struct pinctrl_gpio_range       grange;
  89        spinlock_t                      slock;
  90
  91};
  92
  93#define PIN_BANK(id, pins, label)                       \
  94        {                                               \
  95                .bank_num       = id,                   \
  96                .nr_pins        = pins,                 \
  97                .name           = label,                \
  98        }
  99
 100/**
 101 * @pull_auto: some SoCs don't allow pulls to be specified as up or down, but
 102 *             instead decide this automatically based on the pad-type.
 103 */
 104struct rockchip_pin_ctrl {
 105        struct rockchip_pin_bank        *pin_banks;
 106        u32                             nr_banks;
 107        u32                             nr_pins;
 108        char                            *label;
 109        int                             mux_offset;
 110        int                             pull_offset;
 111        bool                            pull_auto;
 112        int                             pull_bank_stride;
 113};
 114
 115struct rockchip_pin_config {
 116        unsigned int            func;
 117        unsigned long           *configs;
 118        unsigned int            nconfigs;
 119};
 120
 121/**
 122 * struct rockchip_pin_group: represent group of pins of a pinmux function.
 123 * @name: name of the pin group, used to lookup the group.
 124 * @pins: the pins included in this group.
 125 * @npins: number of pins included in this group.
 126 * @func: the mux function number to be programmed when selected.
 127 * @configs: the config values to be set for each pin
 128 * @nconfigs: number of configs for each pin
 129 */
 130struct rockchip_pin_group {
 131        const char                      *name;
 132        unsigned int                    npins;
 133        unsigned int                    *pins;
 134        struct rockchip_pin_config      *data;
 135};
 136
 137/**
 138 * struct rockchip_pmx_func: represent a pin function.
 139 * @name: name of the pin function, used to lookup the function.
 140 * @groups: one or more names of pin groups that provide this function.
 141 * @num_groups: number of groups included in @groups.
 142 */
 143struct rockchip_pmx_func {
 144        const char              *name;
 145        const char              **groups;
 146        u8                      ngroups;
 147};
 148
 149struct rockchip_pinctrl {
 150        void __iomem                    *reg_base;
 151        struct device                   *dev;
 152        struct rockchip_pin_ctrl        *ctrl;
 153        struct pinctrl_desc             pctl;
 154        struct pinctrl_dev              *pctl_dev;
 155        struct rockchip_pin_group       *groups;
 156        unsigned int                    ngroups;
 157        struct rockchip_pmx_func        *functions;
 158        unsigned int                    nfunctions;
 159};
 160
 161static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 162{
 163        return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 164}
 165
 166static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 167                                        const struct rockchip_pinctrl *info,
 168                                        const char *name)
 169{
 170        const struct rockchip_pin_group *grp = NULL;
 171        int i;
 172
 173        for (i = 0; i < info->ngroups; i++) {
 174                if (strcmp(info->groups[i].name, name))
 175                        continue;
 176
 177                grp = &info->groups[i];
 178                break;
 179        }
 180
 181        return grp;
 182}
 183
 184/*
 185 * given a pin number that is local to a pin controller, find out the pin bank
 186 * and the register base of the pin bank.
 187 */
 188static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 189                                                                unsigned pin)
 190{
 191        struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 192
 193        while ((pin >= b->pin_base) &&
 194                        ((b->pin_base + b->nr_pins - 1) < pin))
 195                b++;
 196
 197        return b;
 198}
 199
 200static struct rockchip_pin_bank *bank_num_to_bank(
 201                                        struct rockchip_pinctrl *info,
 202                                        unsigned num)
 203{
 204        struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 205        int i;
 206
 207        for (i = 0; i < info->ctrl->nr_banks; i++) {
 208                if (b->bank_num == num)
 209                        break;
 210
 211                b++;
 212        }
 213
 214        if (b->bank_num != num)
 215                return ERR_PTR(-EINVAL);
 216
 217        return b;
 218}
 219
 220/*
 221 * Pinctrl_ops handling
 222 */
 223
 224static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 225{
 226        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 227
 228        return info->ngroups;
 229}
 230
 231static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 232                                                        unsigned selector)
 233{
 234        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 235
 236        return info->groups[selector].name;
 237}
 238
 239static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 240                                      unsigned selector, const unsigned **pins,
 241                                      unsigned *npins)
 242{
 243        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 244
 245        if (selector >= info->ngroups)
 246                return -EINVAL;
 247
 248        *pins = info->groups[selector].pins;
 249        *npins = info->groups[selector].npins;
 250
 251        return 0;
 252}
 253
 254static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 255                                 struct device_node *np,
 256                                 struct pinctrl_map **map, unsigned *num_maps)
 257{
 258        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 259        const struct rockchip_pin_group *grp;
 260        struct pinctrl_map *new_map;
 261        struct device_node *parent;
 262        int map_num = 1;
 263        int i;
 264
 265        /*
 266         * first find the group of this node and check if we need to create
 267         * config maps for pins
 268         */
 269        grp = pinctrl_name_to_group(info, np->name);
 270        if (!grp) {
 271                dev_err(info->dev, "unable to find group for node %s\n",
 272                        np->name);
 273                return -EINVAL;
 274        }
 275
 276        map_num += grp->npins;
 277        new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 278                                                                GFP_KERNEL);
 279        if (!new_map)
 280                return -ENOMEM;
 281
 282        *map = new_map;
 283        *num_maps = map_num;
 284
 285        /* create mux map */
 286        parent = of_get_parent(np);
 287        if (!parent) {
 288                devm_kfree(pctldev->dev, new_map);
 289                return -EINVAL;
 290        }
 291        new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 292        new_map[0].data.mux.function = parent->name;
 293        new_map[0].data.mux.group = np->name;
 294        of_node_put(parent);
 295
 296        /* create config map */
 297        new_map++;
 298        for (i = 0; i < grp->npins; i++) {
 299                new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 300                new_map[i].data.configs.group_or_pin =
 301                                pin_get_name(pctldev, grp->pins[i]);
 302                new_map[i].data.configs.configs = grp->data[i].configs;
 303                new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 304        }
 305
 306        dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 307                (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 308
 309        return 0;
 310}
 311
 312static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 313                                    struct pinctrl_map *map, unsigned num_maps)
 314{
 315}
 316
 317static const struct pinctrl_ops rockchip_pctrl_ops = {
 318        .get_groups_count       = rockchip_get_groups_count,
 319        .get_group_name         = rockchip_get_group_name,
 320        .get_group_pins         = rockchip_get_group_pins,
 321        .dt_node_to_map         = rockchip_dt_node_to_map,
 322        .dt_free_map            = rockchip_dt_free_map,
 323};
 324
 325/*
 326 * Hardware access
 327 */
 328
 329/*
 330 * Set a new mux function for a pin.
 331 *
 332 * The register is divided into the upper and lower 16 bit. When changing
 333 * a value, the previous register value is not read and changed. Instead
 334 * it seems the changed bits are marked in the upper 16 bit, while the
 335 * changed value gets set in the same offset in the lower 16 bit.
 336 * All pin settings seem to be 2 bit wide in both the upper and lower
 337 * parts.
 338 * @bank: pin bank to change
 339 * @pin: pin to change
 340 * @mux: new mux function to set
 341 */
 342static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 343{
 344        struct rockchip_pinctrl *info = bank->drvdata;
 345        void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
 346        unsigned long flags;
 347        u8 bit;
 348        u32 data;
 349
 350        dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 351                                                bank->bank_num, pin, mux);
 352
 353        /* get basic quadrupel of mux registers and the correct reg inside */
 354        reg += bank->bank_num * 0x10;
 355        reg += (pin / 8) * 4;
 356        bit = (pin % 8) * 2;
 357
 358        spin_lock_irqsave(&bank->slock, flags);
 359
 360        data = (3 << (bit + 16));
 361        data |= (mux & 3) << bit;
 362        writel(data, reg);
 363
 364        spin_unlock_irqrestore(&bank->slock, flags);
 365}
 366
 367static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 368{
 369        struct rockchip_pinctrl *info = bank->drvdata;
 370        struct rockchip_pin_ctrl *ctrl = info->ctrl;
 371        void __iomem *reg;
 372        u8 bit;
 373
 374        /* rk3066b does support any pulls */
 375        if (!ctrl->pull_offset)
 376                return PIN_CONFIG_BIAS_DISABLE;
 377
 378        reg = info->reg_base + ctrl->pull_offset;
 379
 380        if (ctrl->pull_auto) {
 381                reg += bank->bank_num * ctrl->pull_bank_stride;
 382                reg += (pin_num / 16) * 4;
 383                bit = pin_num % 16;
 384
 385                return !(readl_relaxed(reg) & BIT(bit))
 386                                ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 387                                : PIN_CONFIG_BIAS_DISABLE;
 388        } else {
 389                dev_err(info->dev, "pull support for rk31xx not implemented\n");
 390                return -EIO;
 391        }
 392}
 393
 394static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 395                                        int pin_num, int pull)
 396{
 397        struct rockchip_pinctrl *info = bank->drvdata;
 398        struct rockchip_pin_ctrl *ctrl = info->ctrl;
 399        void __iomem *reg;
 400        unsigned long flags;
 401        u8 bit;
 402        u32 data;
 403
 404        dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 405                 bank->bank_num, pin_num, pull);
 406
 407        /* rk3066b does support any pulls */
 408        if (!ctrl->pull_offset)
 409                return pull ? -EINVAL : 0;
 410
 411        reg = info->reg_base + ctrl->pull_offset;
 412
 413        if (ctrl->pull_auto) {
 414                if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
 415                                        pull != PIN_CONFIG_BIAS_DISABLE) {
 416                        dev_err(info->dev, "only PIN_DEFAULT and DISABLE allowed\n");
 417                        return -EINVAL;
 418                }
 419
 420                reg += bank->bank_num * ctrl->pull_bank_stride;
 421                reg += (pin_num / 16) * 4;
 422                bit = pin_num % 16;
 423
 424                spin_lock_irqsave(&bank->slock, flags);
 425
 426                data = BIT(bit + 16);
 427                if (pull == PIN_CONFIG_BIAS_DISABLE)
 428                        data |= BIT(bit);
 429                writel(data, reg);
 430
 431                spin_unlock_irqrestore(&bank->slock, flags);
 432        } else {
 433                if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) {
 434                        dev_err(info->dev, "pull direction (up/down) needs to be specified\n");
 435                        return -EINVAL;
 436                }
 437
 438                dev_err(info->dev, "pull support for rk31xx not implemented\n");
 439                return -EIO;
 440        }
 441
 442        return 0;
 443}
 444
 445/*
 446 * Pinmux_ops handling
 447 */
 448
 449static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 450{
 451        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 452
 453        return info->nfunctions;
 454}
 455
 456static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 457                                          unsigned selector)
 458{
 459        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 460
 461        return info->functions[selector].name;
 462}
 463
 464static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 465                                unsigned selector, const char * const **groups,
 466                                unsigned * const num_groups)
 467{
 468        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 469
 470        *groups = info->functions[selector].groups;
 471        *num_groups = info->functions[selector].ngroups;
 472
 473        return 0;
 474}
 475
 476static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 477                                                            unsigned group)
 478{
 479        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 480        const unsigned int *pins = info->groups[group].pins;
 481        const struct rockchip_pin_config *data = info->groups[group].data;
 482        struct rockchip_pin_bank *bank;
 483        int cnt;
 484
 485        dev_dbg(info->dev, "enable function %s group %s\n",
 486                info->functions[selector].name, info->groups[group].name);
 487
 488        /*
 489         * for each pin in the pin group selected, program the correspoding pin
 490         * pin function number in the config register.
 491         */
 492        for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 493                bank = pin_to_bank(info, pins[cnt]);
 494                rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 495                                 data[cnt].func);
 496        }
 497
 498        return 0;
 499}
 500
 501static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
 502                                        unsigned selector, unsigned group)
 503{
 504        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 505        const unsigned int *pins = info->groups[group].pins;
 506        struct rockchip_pin_bank *bank;
 507        int cnt;
 508
 509        dev_dbg(info->dev, "disable function %s group %s\n",
 510                info->functions[selector].name, info->groups[group].name);
 511
 512        for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 513                bank = pin_to_bank(info, pins[cnt]);
 514                rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 515        }
 516}
 517
 518/*
 519 * The calls to gpio_direction_output() and gpio_direction_input()
 520 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 521 * function called from the gpiolib interface).
 522 */
 523static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 524                                              struct pinctrl_gpio_range *range,
 525                                              unsigned offset, bool input)
 526{
 527        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 528        struct rockchip_pin_bank *bank;
 529        struct gpio_chip *chip;
 530        int pin;
 531        u32 data;
 532
 533        chip = range->gc;
 534        bank = gc_to_pin_bank(chip);
 535        pin = offset - chip->base;
 536
 537        dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
 538                 offset, range->name, pin, input ? "input" : "output");
 539
 540        rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
 541
 542        data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 543        /* set bit to 1 for output, 0 for input */
 544        if (!input)
 545                data |= BIT(pin);
 546        else
 547                data &= ~BIT(pin);
 548        writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 549
 550        return 0;
 551}
 552
 553static const struct pinmux_ops rockchip_pmx_ops = {
 554        .get_functions_count    = rockchip_pmx_get_funcs_count,
 555        .get_function_name      = rockchip_pmx_get_func_name,
 556        .get_function_groups    = rockchip_pmx_get_groups,
 557        .enable                 = rockchip_pmx_enable,
 558        .disable                = rockchip_pmx_disable,
 559        .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 560};
 561
 562/*
 563 * Pinconf_ops handling
 564 */
 565
 566static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 567                                        enum pin_config_param pull)
 568{
 569        /* rk3066b does support any pulls */
 570        if (!ctrl->pull_offset)
 571                return pull ? false : true;
 572
 573        if (ctrl->pull_auto) {
 574                if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
 575                                        pull != PIN_CONFIG_BIAS_DISABLE)
 576                        return false;
 577        } else {
 578                if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
 579                        return false;
 580        }
 581
 582        return true;
 583}
 584
 585/* set the pin config settings for a specified pin */
 586static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 587                                                        unsigned long config)
 588{
 589        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 590        struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 591        enum pin_config_param param = pinconf_to_config_param(config);
 592        u16 arg = pinconf_to_config_argument(config);
 593
 594        switch (param) {
 595        case PIN_CONFIG_BIAS_DISABLE:
 596                return rockchip_set_pull(bank, pin - bank->pin_base, param);
 597                break;
 598        case PIN_CONFIG_BIAS_PULL_UP:
 599        case PIN_CONFIG_BIAS_PULL_DOWN:
 600        case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 601                if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 602                        return -ENOTSUPP;
 603
 604                if (!arg)
 605                        return -EINVAL;
 606
 607                return rockchip_set_pull(bank, pin - bank->pin_base, param);
 608                break;
 609        default:
 610                return -ENOTSUPP;
 611                break;
 612        }
 613
 614        return 0;
 615}
 616
 617/* get the pin config settings for a specified pin */
 618static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 619                                                        unsigned long *config)
 620{
 621        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 622        struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 623        enum pin_config_param param = pinconf_to_config_param(*config);
 624
 625        switch (param) {
 626        case PIN_CONFIG_BIAS_DISABLE:
 627                if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 628                        return -EINVAL;
 629
 630                *config = 0;
 631                break;
 632        case PIN_CONFIG_BIAS_PULL_UP:
 633        case PIN_CONFIG_BIAS_PULL_DOWN:
 634        case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 635                if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 636                        return -ENOTSUPP;
 637
 638                if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 639                        return -EINVAL;
 640
 641                *config = 1;
 642                break;
 643        default:
 644                return -ENOTSUPP;
 645                break;
 646        }
 647
 648        return 0;
 649}
 650
 651static const struct pinconf_ops rockchip_pinconf_ops = {
 652        .pin_config_get                 = rockchip_pinconf_get,
 653        .pin_config_set                 = rockchip_pinconf_set,
 654};
 655
 656static const char *gpio_compat = "rockchip,gpio-bank";
 657
 658static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
 659                                                struct device_node *np)
 660{
 661        struct device_node *child;
 662
 663        for_each_child_of_node(np, child) {
 664                if (of_device_is_compatible(child, gpio_compat))
 665                        continue;
 666
 667                info->nfunctions++;
 668                info->ngroups += of_get_child_count(child);
 669        }
 670}
 671
 672static int rockchip_pinctrl_parse_groups(struct device_node *np,
 673                                              struct rockchip_pin_group *grp,
 674                                              struct rockchip_pinctrl *info,
 675                                              u32 index)
 676{
 677        struct rockchip_pin_bank *bank;
 678        int size;
 679        const __be32 *list;
 680        int num;
 681        int i, j;
 682        int ret;
 683
 684        dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
 685
 686        /* Initialise group */
 687        grp->name = np->name;
 688
 689        /*
 690         * the binding format is rockchip,pins = <bank pin mux CONFIG>,
 691         * do sanity check and calculate pins number
 692         */
 693        list = of_get_property(np, "rockchip,pins", &size);
 694        /* we do not check return since it's safe node passed down */
 695        size /= sizeof(*list);
 696        if (!size || size % 4) {
 697                dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
 698                return -EINVAL;
 699        }
 700
 701        grp->npins = size / 4;
 702
 703        grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 704                                                GFP_KERNEL);
 705        grp->data = devm_kzalloc(info->dev, grp->npins *
 706                                          sizeof(struct rockchip_pin_config),
 707                                        GFP_KERNEL);
 708        if (!grp->pins || !grp->data)
 709                return -ENOMEM;
 710
 711        for (i = 0, j = 0; i < size; i += 4, j++) {
 712                const __be32 *phandle;
 713                struct device_node *np_config;
 714
 715                num = be32_to_cpu(*list++);
 716                bank = bank_num_to_bank(info, num);
 717                if (IS_ERR(bank))
 718                        return PTR_ERR(bank);
 719
 720                grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
 721                grp->data[j].func = be32_to_cpu(*list++);
 722
 723                phandle = list++;
 724                if (!phandle)
 725                        return -EINVAL;
 726
 727                np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
 728                ret = pinconf_generic_parse_dt_config(np_config,
 729                                &grp->data[j].configs, &grp->data[j].nconfigs);
 730                if (ret)
 731                        return ret;
 732        }
 733
 734        return 0;
 735}
 736
 737static int rockchip_pinctrl_parse_functions(struct device_node *np,
 738                                                struct rockchip_pinctrl *info,
 739                                                u32 index)
 740{
 741        struct device_node *child;
 742        struct rockchip_pmx_func *func;
 743        struct rockchip_pin_group *grp;
 744        int ret;
 745        static u32 grp_index;
 746        u32 i = 0;
 747
 748        dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
 749
 750        func = &info->functions[index];
 751
 752        /* Initialise function */
 753        func->name = np->name;
 754        func->ngroups = of_get_child_count(np);
 755        if (func->ngroups <= 0)
 756                return 0;
 757
 758        func->groups = devm_kzalloc(info->dev,
 759                        func->ngroups * sizeof(char *), GFP_KERNEL);
 760        if (!func->groups)
 761                return -ENOMEM;
 762
 763        for_each_child_of_node(np, child) {
 764                func->groups[i] = child->name;
 765                grp = &info->groups[grp_index++];
 766                ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
 767                if (ret)
 768                        return ret;
 769        }
 770
 771        return 0;
 772}
 773
 774static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
 775                                              struct rockchip_pinctrl *info)
 776{
 777        struct device *dev = &pdev->dev;
 778        struct device_node *np = dev->of_node;
 779        struct device_node *child;
 780        int ret;
 781        int i;
 782
 783        rockchip_pinctrl_child_count(info, np);
 784
 785        dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
 786        dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
 787
 788        info->functions = devm_kzalloc(dev, info->nfunctions *
 789                                              sizeof(struct rockchip_pmx_func),
 790                                              GFP_KERNEL);
 791        if (!info->functions) {
 792                dev_err(dev, "failed to allocate memory for function list\n");
 793                return -EINVAL;
 794        }
 795
 796        info->groups = devm_kzalloc(dev, info->ngroups *
 797                                            sizeof(struct rockchip_pin_group),
 798                                            GFP_KERNEL);
 799        if (!info->groups) {
 800                dev_err(dev, "failed allocate memory for ping group list\n");
 801                return -EINVAL;
 802        }
 803
 804        i = 0;
 805
 806        for_each_child_of_node(np, child) {
 807                if (of_device_is_compatible(child, gpio_compat))
 808                        continue;
 809                ret = rockchip_pinctrl_parse_functions(child, info, i++);
 810                if (ret) {
 811                        dev_err(&pdev->dev, "failed to parse function\n");
 812                        return ret;
 813                }
 814        }
 815
 816        return 0;
 817}
 818
 819static int rockchip_pinctrl_register(struct platform_device *pdev,
 820                                        struct rockchip_pinctrl *info)
 821{
 822        struct pinctrl_desc *ctrldesc = &info->pctl;
 823        struct pinctrl_pin_desc *pindesc, *pdesc;
 824        struct rockchip_pin_bank *pin_bank;
 825        int pin, bank, ret;
 826        int k;
 827
 828        ctrldesc->name = "rockchip-pinctrl";
 829        ctrldesc->owner = THIS_MODULE;
 830        ctrldesc->pctlops = &rockchip_pctrl_ops;
 831        ctrldesc->pmxops = &rockchip_pmx_ops;
 832        ctrldesc->confops = &rockchip_pinconf_ops;
 833
 834        pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
 835                        info->ctrl->nr_pins, GFP_KERNEL);
 836        if (!pindesc) {
 837                dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
 838                return -ENOMEM;
 839        }
 840        ctrldesc->pins = pindesc;
 841        ctrldesc->npins = info->ctrl->nr_pins;
 842
 843        pdesc = pindesc;
 844        for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
 845                pin_bank = &info->ctrl->pin_banks[bank];
 846                for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
 847                        pdesc->number = k;
 848                        pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
 849                                                pin_bank->name, pin);
 850                        pdesc++;
 851                }
 852        }
 853
 854        info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
 855        if (!info->pctl_dev) {
 856                dev_err(&pdev->dev, "could not register pinctrl driver\n");
 857                return -EINVAL;
 858        }
 859
 860        for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
 861                pin_bank = &info->ctrl->pin_banks[bank];
 862                pin_bank->grange.name = pin_bank->name;
 863                pin_bank->grange.id = bank;
 864                pin_bank->grange.pin_base = pin_bank->pin_base;
 865                pin_bank->grange.base = pin_bank->gpio_chip.base;
 866                pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
 867                pin_bank->grange.gc = &pin_bank->gpio_chip;
 868                pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
 869        }
 870
 871        ret = rockchip_pinctrl_parse_dt(pdev, info);
 872        if (ret) {
 873                pinctrl_unregister(info->pctl_dev);
 874                return ret;
 875        }
 876
 877        return 0;
 878}
 879
 880/*
 881 * GPIO handling
 882 */
 883
 884static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
 885{
 886        struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 887        void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
 888        unsigned long flags;
 889        u32 data;
 890
 891        spin_lock_irqsave(&bank->slock, flags);
 892
 893        data = readl(reg);
 894        data &= ~BIT(offset);
 895        if (value)
 896                data |= BIT(offset);
 897        writel(data, reg);
 898
 899        spin_unlock_irqrestore(&bank->slock, flags);
 900}
 901
 902/*
 903 * Returns the level of the pin for input direction and setting of the DR
 904 * register for output gpios.
 905 */
 906static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
 907{
 908        struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 909        u32 data;
 910
 911        data = readl(bank->reg_base + GPIO_EXT_PORT);
 912        data >>= offset;
 913        data &= 1;
 914        return data;
 915}
 916
 917/*
 918 * gpiolib gpio_direction_input callback function. The setting of the pin
 919 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
 920 * interface.
 921 */
 922static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
 923{
 924        return pinctrl_gpio_direction_input(gc->base + offset);
 925}
 926
 927/*
 928 * gpiolib gpio_direction_output callback function. The setting of the pin
 929 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
 930 * interface.
 931 */
 932static int rockchip_gpio_direction_output(struct gpio_chip *gc,
 933                                          unsigned offset, int value)
 934{
 935        rockchip_gpio_set(gc, offset, value);
 936        return pinctrl_gpio_direction_output(gc->base + offset);
 937}
 938
 939/*
 940 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
 941 * and a virtual IRQ, if not already present.
 942 */
 943static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 944{
 945        struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 946        unsigned int virq;
 947
 948        if (!bank->domain)
 949                return -ENXIO;
 950
 951        virq = irq_create_mapping(bank->domain, offset);
 952
 953        return (virq) ? : -ENXIO;
 954}
 955
 956static const struct gpio_chip rockchip_gpiolib_chip = {
 957        .set = rockchip_gpio_set,
 958        .get = rockchip_gpio_get,
 959        .direction_input = rockchip_gpio_direction_input,
 960        .direction_output = rockchip_gpio_direction_output,
 961        .to_irq = rockchip_gpio_to_irq,
 962        .owner = THIS_MODULE,
 963};
 964
 965/*
 966 * Interrupt handling
 967 */
 968
 969static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
 970{
 971        struct irq_chip *chip = irq_get_chip(irq);
 972        struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
 973        u32 pend;
 974
 975        dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
 976
 977        chained_irq_enter(chip, desc);
 978
 979        pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
 980
 981        while (pend) {
 982                unsigned int virq;
 983
 984                irq = __ffs(pend);
 985                pend &= ~BIT(irq);
 986                virq = irq_linear_revmap(bank->domain, irq);
 987
 988                if (!virq) {
 989                        dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
 990                        continue;
 991                }
 992
 993                dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
 994
 995                generic_handle_irq(virq);
 996        }
 997
 998        chained_irq_exit(chip, desc);
 999}
1000
1001static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1002{
1003        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1004        struct rockchip_pin_bank *bank = gc->private;
1005        u32 mask = BIT(d->hwirq);
1006        u32 polarity;
1007        u32 level;
1008        u32 data;
1009
1010        if (type & IRQ_TYPE_EDGE_BOTH)
1011                __irq_set_handler_locked(d->irq, handle_edge_irq);
1012        else
1013                __irq_set_handler_locked(d->irq, handle_level_irq);
1014
1015        irq_gc_lock(gc);
1016
1017        level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1018        polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1019
1020        switch (type) {
1021        case IRQ_TYPE_EDGE_RISING:
1022                level |= mask;
1023                polarity |= mask;
1024                break;
1025        case IRQ_TYPE_EDGE_FALLING:
1026                level |= mask;
1027                polarity &= ~mask;
1028                break;
1029        case IRQ_TYPE_LEVEL_HIGH:
1030                level &= ~mask;
1031                polarity |= mask;
1032                break;
1033        case IRQ_TYPE_LEVEL_LOW:
1034                level &= ~mask;
1035                polarity &= ~mask;
1036                break;
1037        default:
1038                irq_gc_unlock(gc);
1039                return -EINVAL;
1040        }
1041
1042        writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1043        writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1044
1045        irq_gc_unlock(gc);
1046
1047        /* make sure the pin is configured as gpio input */
1048        rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1049        data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1050        data &= ~mask;
1051        writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1052
1053        return 0;
1054}
1055
1056static int rockchip_interrupts_register(struct platform_device *pdev,
1057                                                struct rockchip_pinctrl *info)
1058{
1059        struct rockchip_pin_ctrl *ctrl = info->ctrl;
1060        struct rockchip_pin_bank *bank = ctrl->pin_banks;
1061        unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1062        struct irq_chip_generic *gc;
1063        int ret;
1064        int i;
1065
1066        for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1067                if (!bank->valid) {
1068                        dev_warn(&pdev->dev, "bank %s is not valid\n",
1069                                 bank->name);
1070                        continue;
1071                }
1072
1073                bank->domain = irq_domain_add_linear(bank->of_node, 32,
1074                                                &irq_generic_chip_ops, NULL);
1075                if (!bank->domain) {
1076                        dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1077                                 bank->name);
1078                        continue;
1079                }
1080
1081                ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1082                                         "rockchip_gpio_irq", handle_level_irq,
1083                                         clr, 0, IRQ_GC_INIT_MASK_CACHE);
1084                if (ret) {
1085                        dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1086                                bank->name);
1087                        irq_domain_remove(bank->domain);
1088                        continue;
1089                }
1090
1091                gc = irq_get_domain_generic_chip(bank->domain, 0);
1092                gc->reg_base = bank->reg_base;
1093                gc->private = bank;
1094                gc->chip_types[0].regs.mask = GPIO_INTEN;
1095                gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1096                gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1097                gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1098                gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1099                gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1100                gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1101
1102                irq_set_handler_data(bank->irq, bank);
1103                irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1104        }
1105
1106        return 0;
1107}
1108
1109static int rockchip_gpiolib_register(struct platform_device *pdev,
1110                                                struct rockchip_pinctrl *info)
1111{
1112        struct rockchip_pin_ctrl *ctrl = info->ctrl;
1113        struct rockchip_pin_bank *bank = ctrl->pin_banks;
1114        struct gpio_chip *gc;
1115        int ret;
1116        int i;
1117
1118        for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1119                if (!bank->valid) {
1120                        dev_warn(&pdev->dev, "bank %s is not valid\n",
1121                                 bank->name);
1122                        continue;
1123                }
1124
1125                bank->gpio_chip = rockchip_gpiolib_chip;
1126
1127                gc = &bank->gpio_chip;
1128                gc->base = bank->pin_base;
1129                gc->ngpio = bank->nr_pins;
1130                gc->dev = &pdev->dev;
1131                gc->of_node = bank->of_node;
1132                gc->label = bank->name;
1133
1134                ret = gpiochip_add(gc);
1135                if (ret) {
1136                        dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1137                                                        gc->label, ret);
1138                        goto fail;
1139                }
1140        }
1141
1142        rockchip_interrupts_register(pdev, info);
1143
1144        return 0;
1145
1146fail:
1147        for (--i, --bank; i >= 0; --i, --bank) {
1148                if (!bank->valid)
1149                        continue;
1150
1151                if (gpiochip_remove(&bank->gpio_chip))
1152                        dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1153                                                        bank->gpio_chip.label);
1154        }
1155        return ret;
1156}
1157
1158static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1159                                                struct rockchip_pinctrl *info)
1160{
1161        struct rockchip_pin_ctrl *ctrl = info->ctrl;
1162        struct rockchip_pin_bank *bank = ctrl->pin_banks;
1163        int ret = 0;
1164        int i;
1165
1166        for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1167                if (!bank->valid)
1168                        continue;
1169
1170                ret = gpiochip_remove(&bank->gpio_chip);
1171        }
1172
1173        if (ret)
1174                dev_err(&pdev->dev, "gpio chip remove failed\n");
1175
1176        return ret;
1177}
1178
1179static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1180                                  struct device *dev)
1181{
1182        struct resource res;
1183
1184        if (of_address_to_resource(bank->of_node, 0, &res)) {
1185                dev_err(dev, "cannot find IO resource for bank\n");
1186                return -ENOENT;
1187        }
1188
1189        bank->reg_base = devm_ioremap_resource(dev, &res);
1190        if (IS_ERR(bank->reg_base))
1191                return PTR_ERR(bank->reg_base);
1192
1193        bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1194
1195        bank->clk = of_clk_get(bank->of_node, 0);
1196        if (IS_ERR(bank->clk))
1197                return PTR_ERR(bank->clk);
1198
1199        return clk_prepare_enable(bank->clk);
1200}
1201
1202static const struct of_device_id rockchip_pinctrl_dt_match[];
1203
1204/* retrieve the soc specific data */
1205static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1206                                                struct rockchip_pinctrl *d,
1207                                                struct platform_device *pdev)
1208{
1209        const struct of_device_id *match;
1210        struct device_node *node = pdev->dev.of_node;
1211        struct device_node *np;
1212        struct rockchip_pin_ctrl *ctrl;
1213        struct rockchip_pin_bank *bank;
1214        int i;
1215
1216        match = of_match_node(rockchip_pinctrl_dt_match, node);
1217        ctrl = (struct rockchip_pin_ctrl *)match->data;
1218
1219        for_each_child_of_node(node, np) {
1220                if (!of_find_property(np, "gpio-controller", NULL))
1221                        continue;
1222
1223                bank = ctrl->pin_banks;
1224                for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1225                        if (!strcmp(bank->name, np->name)) {
1226                                bank->of_node = np;
1227
1228                                if (!rockchip_get_bank_data(bank, &pdev->dev))
1229                                        bank->valid = true;
1230
1231                                break;
1232                        }
1233                }
1234        }
1235
1236        bank = ctrl->pin_banks;
1237        for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1238                spin_lock_init(&bank->slock);
1239                bank->drvdata = d;
1240                bank->pin_base = ctrl->nr_pins;
1241                ctrl->nr_pins += bank->nr_pins;
1242        }
1243
1244        return ctrl;
1245}
1246
1247static int rockchip_pinctrl_probe(struct platform_device *pdev)
1248{
1249        struct rockchip_pinctrl *info;
1250        struct device *dev = &pdev->dev;
1251        struct rockchip_pin_ctrl *ctrl;
1252        struct resource *res;
1253        int ret;
1254
1255        if (!dev->of_node) {
1256                dev_err(dev, "device tree node not found\n");
1257                return -ENODEV;
1258        }
1259
1260        info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1261        if (!info)
1262                return -ENOMEM;
1263
1264        ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1265        if (!ctrl) {
1266                dev_err(dev, "driver data not available\n");
1267                return -EINVAL;
1268        }
1269        info->ctrl = ctrl;
1270        info->dev = dev;
1271
1272        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1273        if (!res) {
1274                dev_err(dev, "cannot find IO resource\n");
1275                return -ENOENT;
1276        }
1277
1278        info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1279        if (IS_ERR(info->reg_base))
1280                return PTR_ERR(info->reg_base);
1281
1282        ret = rockchip_gpiolib_register(pdev, info);
1283        if (ret)
1284                return ret;
1285
1286        ret = rockchip_pinctrl_register(pdev, info);
1287        if (ret) {
1288                rockchip_gpiolib_unregister(pdev, info);
1289                return ret;
1290        }
1291
1292        platform_set_drvdata(pdev, info);
1293
1294        return 0;
1295}
1296
1297static struct rockchip_pin_bank rk2928_pin_banks[] = {
1298        PIN_BANK(0, 32, "gpio0"),
1299        PIN_BANK(1, 32, "gpio1"),
1300        PIN_BANK(2, 32, "gpio2"),
1301        PIN_BANK(3, 32, "gpio3"),
1302};
1303
1304static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1305                .pin_banks              = rk2928_pin_banks,
1306                .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
1307                .label                  = "RK2928-GPIO",
1308                .mux_offset             = 0xa8,
1309                .pull_offset            = 0x118,
1310                .pull_auto              = 1,
1311                .pull_bank_stride       = 8,
1312};
1313
1314static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1315        PIN_BANK(0, 32, "gpio0"),
1316        PIN_BANK(1, 32, "gpio1"),
1317        PIN_BANK(2, 32, "gpio2"),
1318        PIN_BANK(3, 32, "gpio3"),
1319        PIN_BANK(4, 32, "gpio4"),
1320        PIN_BANK(6, 16, "gpio6"),
1321};
1322
1323static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1324                .pin_banks              = rk3066a_pin_banks,
1325                .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
1326                .label                  = "RK3066a-GPIO",
1327                .mux_offset             = 0xa8,
1328                .pull_offset            = 0x118,
1329                .pull_auto              = 1,
1330                .pull_bank_stride       = 8,
1331};
1332
1333static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1334        PIN_BANK(0, 32, "gpio0"),
1335        PIN_BANK(1, 32, "gpio1"),
1336        PIN_BANK(2, 32, "gpio2"),
1337        PIN_BANK(3, 32, "gpio3"),
1338};
1339
1340static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1341                .pin_banks      = rk3066b_pin_banks,
1342                .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
1343                .label          = "RK3066b-GPIO",
1344                .mux_offset     = 0x60,
1345                .pull_offset    = -EINVAL,
1346};
1347
1348static struct rockchip_pin_bank rk3188_pin_banks[] = {
1349        PIN_BANK(0, 32, "gpio0"),
1350        PIN_BANK(1, 32, "gpio1"),
1351        PIN_BANK(2, 32, "gpio2"),
1352        PIN_BANK(3, 32, "gpio3"),
1353};
1354
1355static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1356                .pin_banks              = rk3188_pin_banks,
1357                .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
1358                .label                  = "RK3188-GPIO",
1359                .mux_offset             = 0x68,
1360                .pull_offset            = 0x164,
1361                .pull_bank_stride       = 16,
1362};
1363
1364static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1365        { .compatible = "rockchip,rk2928-pinctrl",
1366                .data = (void *)&rk2928_pin_ctrl },
1367        { .compatible = "rockchip,rk3066a-pinctrl",
1368                .data = (void *)&rk3066a_pin_ctrl },
1369        { .compatible = "rockchip,rk3066b-pinctrl",
1370                .data = (void *)&rk3066b_pin_ctrl },
1371        { .compatible = "rockchip,rk3188-pinctrl",
1372                .data = (void *)&rk3188_pin_ctrl },
1373        {},
1374};
1375MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1376
1377static struct platform_driver rockchip_pinctrl_driver = {
1378        .probe          = rockchip_pinctrl_probe,
1379        .driver = {
1380                .name   = "rockchip-pinctrl",
1381                .owner  = THIS_MODULE,
1382                .of_match_table = of_match_ptr(rockchip_pinctrl_dt_match),
1383        },
1384};
1385
1386static int __init rockchip_pinctrl_drv_register(void)
1387{
1388        return platform_driver_register(&rockchip_pinctrl_driver);
1389}
1390postcore_initcall(rockchip_pinctrl_drv_register);
1391
1392MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1393MODULE_DESCRIPTION("Rockchip pinctrl driver");
1394MODULE_LICENSE("GPL v2");
1395
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