linux/drivers/iommu/omap-iommu2.c
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   1/*
   2 * omap iommu: omap2/3 architecture specific functions
   3 *
   4 * Copyright (C) 2008-2009 Nokia Corporation
   5 *
   6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
   7 *              Paul Mundt and Toshihiro Kobayashi
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License version 2 as
  11 * published by the Free Software Foundation.
  12 */
  13
  14#include <linux/err.h>
  15#include <linux/device.h>
  16#include <linux/io.h>
  17#include <linux/jiffies.h>
  18#include <linux/module.h>
  19#include <linux/omap-iommu.h>
  20#include <linux/slab.h>
  21#include <linux/stringify.h>
  22#include <linux/platform_data/iommu-omap.h>
  23
  24#include "omap-iommu.h"
  25
  26/*
  27 * omap2 architecture specific register bit definitions
  28 */
  29#define IOMMU_ARCH_VERSION      0x00000011
  30
  31/* IRQSTATUS & IRQENABLE */
  32#define MMU_IRQ_MULTIHITFAULT   (1 << 4)
  33#define MMU_IRQ_TABLEWALKFAULT  (1 << 3)
  34#define MMU_IRQ_EMUMISS         (1 << 2)
  35#define MMU_IRQ_TRANSLATIONFAULT        (1 << 1)
  36#define MMU_IRQ_TLBMISS         (1 << 0)
  37
  38#define __MMU_IRQ_FAULT         \
  39        (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
  40#define MMU_IRQ_MASK            \
  41        (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
  42#define MMU_IRQ_TWL_MASK        (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
  43#define MMU_IRQ_TLB_MISS_MASK   (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
  44
  45/* MMU_CNTL */
  46#define MMU_CNTL_SHIFT          1
  47#define MMU_CNTL_MASK           (7 << MMU_CNTL_SHIFT)
  48#define MMU_CNTL_EML_TLB        (1 << 3)
  49#define MMU_CNTL_TWL_EN         (1 << 2)
  50#define MMU_CNTL_MMU_EN         (1 << 1)
  51
  52#define get_cam_va_mask(pgsz)                           \
  53        (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :    \
  54         ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :    \
  55         ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :    \
  56         ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
  57
  58/* IOMMU errors */
  59#define OMAP_IOMMU_ERR_TLB_MISS         (1 << 0)
  60#define OMAP_IOMMU_ERR_TRANS_FAULT      (1 << 1)
  61#define OMAP_IOMMU_ERR_EMU_MISS         (1 << 2)
  62#define OMAP_IOMMU_ERR_TBLWALK_FAULT    (1 << 3)
  63#define OMAP_IOMMU_ERR_MULTIHIT_FAULT   (1 << 4)
  64
  65static void __iommu_set_twl(struct omap_iommu *obj, bool on)
  66{
  67        u32 l = iommu_read_reg(obj, MMU_CNTL);
  68
  69        if (on)
  70                iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
  71        else
  72                iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
  73
  74        l &= ~MMU_CNTL_MASK;
  75        if (on)
  76                l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
  77        else
  78                l |= (MMU_CNTL_MMU_EN);
  79
  80        iommu_write_reg(obj, l, MMU_CNTL);
  81}
  82
  83
  84static int omap2_iommu_enable(struct omap_iommu *obj)
  85{
  86        u32 l, pa;
  87
  88        if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd,  SZ_16K))
  89                return -EINVAL;
  90
  91        pa = virt_to_phys(obj->iopgd);
  92        if (!IS_ALIGNED(pa, SZ_16K))
  93                return -EINVAL;
  94
  95        l = iommu_read_reg(obj, MMU_REVISION);
  96        dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
  97                 (l >> 4) & 0xf, l & 0xf);
  98
  99        iommu_write_reg(obj, pa, MMU_TTB);
 100
 101        __iommu_set_twl(obj, true);
 102
 103        return 0;
 104}
 105
 106static void omap2_iommu_disable(struct omap_iommu *obj)
 107{
 108        u32 l = iommu_read_reg(obj, MMU_CNTL);
 109
 110        l &= ~MMU_CNTL_MASK;
 111        iommu_write_reg(obj, l, MMU_CNTL);
 112
 113        dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
 114}
 115
 116static void omap2_iommu_set_twl(struct omap_iommu *obj, bool on)
 117{
 118        __iommu_set_twl(obj, false);
 119}
 120
 121static u32 omap2_iommu_fault_isr(struct omap_iommu *obj, u32 *ra)
 122{
 123        u32 stat, da;
 124        u32 errs = 0;
 125
 126        stat = iommu_read_reg(obj, MMU_IRQSTATUS);
 127        stat &= MMU_IRQ_MASK;
 128        if (!stat) {
 129                *ra = 0;
 130                return 0;
 131        }
 132
 133        da = iommu_read_reg(obj, MMU_FAULT_AD);
 134        *ra = da;
 135
 136        if (stat & MMU_IRQ_TLBMISS)
 137                errs |= OMAP_IOMMU_ERR_TLB_MISS;
 138        if (stat & MMU_IRQ_TRANSLATIONFAULT)
 139                errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
 140        if (stat & MMU_IRQ_EMUMISS)
 141                errs |= OMAP_IOMMU_ERR_EMU_MISS;
 142        if (stat & MMU_IRQ_TABLEWALKFAULT)
 143                errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
 144        if (stat & MMU_IRQ_MULTIHITFAULT)
 145                errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
 146        iommu_write_reg(obj, stat, MMU_IRQSTATUS);
 147
 148        return errs;
 149}
 150
 151static void omap2_tlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
 152{
 153        cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
 154        cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
 155}
 156
 157static void omap2_tlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
 158{
 159        iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
 160        iommu_write_reg(obj, cr->ram, MMU_RAM);
 161}
 162
 163static u32 omap2_cr_to_virt(struct cr_regs *cr)
 164{
 165        u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
 166        u32 mask = get_cam_va_mask(cr->cam & page_size);
 167
 168        return cr->cam & mask;
 169}
 170
 171static struct cr_regs *omap2_alloc_cr(struct omap_iommu *obj,
 172                                                struct iotlb_entry *e)
 173{
 174        struct cr_regs *cr;
 175
 176        if (e->da & ~(get_cam_va_mask(e->pgsz))) {
 177                dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
 178                        e->da);
 179                return ERR_PTR(-EINVAL);
 180        }
 181
 182        cr = kmalloc(sizeof(*cr), GFP_KERNEL);
 183        if (!cr)
 184                return ERR_PTR(-ENOMEM);
 185
 186        cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
 187        cr->ram = e->pa | e->endian | e->elsz | e->mixed;
 188
 189        return cr;
 190}
 191
 192static inline int omap2_cr_valid(struct cr_regs *cr)
 193{
 194        return cr->cam & MMU_CAM_V;
 195}
 196
 197static u32 omap2_get_pte_attr(struct iotlb_entry *e)
 198{
 199        u32 attr;
 200
 201        attr = e->mixed << 5;
 202        attr |= e->endian;
 203        attr |= e->elsz >> 3;
 204        attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
 205                        (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
 206        return attr;
 207}
 208
 209static ssize_t
 210omap2_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, char *buf)
 211{
 212        char *p = buf;
 213
 214        /* FIXME: Need more detail analysis of cam/ram */
 215        p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
 216                                        (cr->cam & MMU_CAM_P) ? 1 : 0);
 217
 218        return p - buf;
 219}
 220
 221#define pr_reg(name)                                                    \
 222        do {                                                            \
 223                ssize_t bytes;                                          \
 224                const char *str = "%20s: %08x\n";                       \
 225                const int maxcol = 32;                                  \
 226                bytes = snprintf(p, maxcol, str, __stringify(name),     \
 227                                 iommu_read_reg(obj, MMU_##name));      \
 228                p += bytes;                                             \
 229                len -= bytes;                                           \
 230                if (len < maxcol)                                       \
 231                        goto out;                                       \
 232        } while (0)
 233
 234static ssize_t
 235omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len)
 236{
 237        char *p = buf;
 238
 239        pr_reg(REVISION);
 240        pr_reg(IRQSTATUS);
 241        pr_reg(IRQENABLE);
 242        pr_reg(WALKING_ST);
 243        pr_reg(CNTL);
 244        pr_reg(FAULT_AD);
 245        pr_reg(TTB);
 246        pr_reg(LOCK);
 247        pr_reg(LD_TLB);
 248        pr_reg(CAM);
 249        pr_reg(RAM);
 250        pr_reg(GFLUSH);
 251        pr_reg(FLUSH_ENTRY);
 252        pr_reg(READ_CAM);
 253        pr_reg(READ_RAM);
 254        pr_reg(EMU_FAULT_AD);
 255out:
 256        return p - buf;
 257}
 258
 259static void omap2_iommu_save_ctx(struct omap_iommu *obj)
 260{
 261        int i;
 262        u32 *p = obj->ctx;
 263
 264        for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
 265                p[i] = iommu_read_reg(obj, i * sizeof(u32));
 266                dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
 267        }
 268
 269        BUG_ON(p[0] != IOMMU_ARCH_VERSION);
 270}
 271
 272static void omap2_iommu_restore_ctx(struct omap_iommu *obj)
 273{
 274        int i;
 275        u32 *p = obj->ctx;
 276
 277        for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
 278                iommu_write_reg(obj, p[i], i * sizeof(u32));
 279                dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
 280        }
 281
 282        BUG_ON(p[0] != IOMMU_ARCH_VERSION);
 283}
 284
 285static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
 286{
 287        e->da           = cr->cam & MMU_CAM_VATAG_MASK;
 288        e->pa           = cr->ram & MMU_RAM_PADDR_MASK;
 289        e->valid        = cr->cam & MMU_CAM_V;
 290        e->pgsz         = cr->cam & MMU_CAM_PGSZ_MASK;
 291        e->endian       = cr->ram & MMU_RAM_ENDIAN_MASK;
 292        e->elsz         = cr->ram & MMU_RAM_ELSZ_MASK;
 293        e->mixed        = cr->ram & MMU_RAM_MIXED;
 294}
 295
 296static const struct iommu_functions omap2_iommu_ops = {
 297        .version        = IOMMU_ARCH_VERSION,
 298
 299        .enable         = omap2_iommu_enable,
 300        .disable        = omap2_iommu_disable,
 301        .set_twl        = omap2_iommu_set_twl,
 302        .fault_isr      = omap2_iommu_fault_isr,
 303
 304        .tlb_read_cr    = omap2_tlb_read_cr,
 305        .tlb_load_cr    = omap2_tlb_load_cr,
 306
 307        .cr_to_e        = omap2_cr_to_e,
 308        .cr_to_virt     = omap2_cr_to_virt,
 309        .alloc_cr       = omap2_alloc_cr,
 310        .cr_valid       = omap2_cr_valid,
 311        .dump_cr        = omap2_dump_cr,
 312
 313        .get_pte_attr   = omap2_get_pte_attr,
 314
 315        .save_ctx       = omap2_iommu_save_ctx,
 316        .restore_ctx    = omap2_iommu_restore_ctx,
 317        .dump_ctx       = omap2_iommu_dump_ctx,
 318};
 319
 320static int __init omap2_iommu_init(void)
 321{
 322        return omap_install_iommu_arch(&omap2_iommu_ops);
 323}
 324module_init(omap2_iommu_init);
 325
 326static void __exit omap2_iommu_exit(void)
 327{
 328        omap_uninstall_iommu_arch(&omap2_iommu_ops);
 329}
 330module_exit(omap2_iommu_exit);
 331
 332MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
 333MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
 334MODULE_LICENSE("GPL v2");
 335
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