linux/drivers/gpio/gpio-rcar.c
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   1/*
   2 * Renesas R-Car GPIO Support
   3 *
   4 *  Copyright (C) 2013 Magnus Damm
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 */
  15
  16#include <linux/err.h>
  17#include <linux/gpio.h>
  18#include <linux/init.h>
  19#include <linux/interrupt.h>
  20#include <linux/io.h>
  21#include <linux/ioport.h>
  22#include <linux/irq.h>
  23#include <linux/irqdomain.h>
  24#include <linux/module.h>
  25#include <linux/pinctrl/consumer.h>
  26#include <linux/platform_data/gpio-rcar.h>
  27#include <linux/platform_device.h>
  28#include <linux/spinlock.h>
  29#include <linux/slab.h>
  30
  31struct gpio_rcar_priv {
  32        void __iomem *base;
  33        spinlock_t lock;
  34        struct gpio_rcar_config config;
  35        struct platform_device *pdev;
  36        struct gpio_chip gpio_chip;
  37        struct irq_chip irq_chip;
  38        struct irq_domain *irq_domain;
  39};
  40
  41#define IOINTSEL 0x00
  42#define INOUTSEL 0x04
  43#define OUTDT 0x08
  44#define INDT 0x0c
  45#define INTDT 0x10
  46#define INTCLR 0x14
  47#define INTMSK 0x18
  48#define MSKCLR 0x1c
  49#define POSNEG 0x20
  50#define EDGLEVEL 0x24
  51#define FILONOFF 0x28
  52#define BOTHEDGE 0x4c
  53
  54#define RCAR_MAX_GPIO_PER_BANK          32
  55
  56static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
  57{
  58        return ioread32(p->base + offs);
  59}
  60
  61static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
  62                                   u32 value)
  63{
  64        iowrite32(value, p->base + offs);
  65}
  66
  67static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
  68                                 int bit, bool value)
  69{
  70        u32 tmp = gpio_rcar_read(p, offs);
  71
  72        if (value)
  73                tmp |= BIT(bit);
  74        else
  75                tmp &= ~BIT(bit);
  76
  77        gpio_rcar_write(p, offs, tmp);
  78}
  79
  80static void gpio_rcar_irq_disable(struct irq_data *d)
  81{
  82        struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
  83
  84        gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
  85}
  86
  87static void gpio_rcar_irq_enable(struct irq_data *d)
  88{
  89        struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
  90
  91        gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
  92}
  93
  94static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
  95                                                  unsigned int hwirq,
  96                                                  bool active_high_rising_edge,
  97                                                  bool level_trigger,
  98                                                  bool both)
  99{
 100        unsigned long flags;
 101
 102        /* follow steps in the GPIO documentation for
 103         * "Setting Edge-Sensitive Interrupt Input Mode" and
 104         * "Setting Level-Sensitive Interrupt Input Mode"
 105         */
 106
 107        spin_lock_irqsave(&p->lock, flags);
 108
 109        /* Configure postive or negative logic in POSNEG */
 110        gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
 111
 112        /* Configure edge or level trigger in EDGLEVEL */
 113        gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
 114
 115        /* Select one edge or both edges in BOTHEDGE */
 116        if (p->config.has_both_edge_trigger)
 117                gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
 118
 119        /* Select "Interrupt Input Mode" in IOINTSEL */
 120        gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
 121
 122        /* Write INTCLR in case of edge trigger */
 123        if (!level_trigger)
 124                gpio_rcar_write(p, INTCLR, BIT(hwirq));
 125
 126        spin_unlock_irqrestore(&p->lock, flags);
 127}
 128
 129static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
 130{
 131        struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
 132        unsigned int hwirq = irqd_to_hwirq(d);
 133
 134        dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
 135
 136        switch (type & IRQ_TYPE_SENSE_MASK) {
 137        case IRQ_TYPE_LEVEL_HIGH:
 138                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
 139                                                      false);
 140                break;
 141        case IRQ_TYPE_LEVEL_LOW:
 142                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
 143                                                      false);
 144                break;
 145        case IRQ_TYPE_EDGE_RISING:
 146                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
 147                                                      false);
 148                break;
 149        case IRQ_TYPE_EDGE_FALLING:
 150                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
 151                                                      false);
 152                break;
 153        case IRQ_TYPE_EDGE_BOTH:
 154                if (!p->config.has_both_edge_trigger)
 155                        return -EINVAL;
 156                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
 157                                                      true);
 158                break;
 159        default:
 160                return -EINVAL;
 161        }
 162        return 0;
 163}
 164
 165static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
 166{
 167        struct gpio_rcar_priv *p = dev_id;
 168        u32 pending;
 169        unsigned int offset, irqs_handled = 0;
 170
 171        while ((pending = gpio_rcar_read(p, INTDT))) {
 172                offset = __ffs(pending);
 173                gpio_rcar_write(p, INTCLR, BIT(offset));
 174                generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
 175                irqs_handled++;
 176        }
 177
 178        return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
 179}
 180
 181static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
 182{
 183        return container_of(chip, struct gpio_rcar_priv, gpio_chip);
 184}
 185
 186static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
 187                                                       unsigned int gpio,
 188                                                       bool output)
 189{
 190        struct gpio_rcar_priv *p = gpio_to_priv(chip);
 191        unsigned long flags;
 192
 193        /* follow steps in the GPIO documentation for
 194         * "Setting General Output Mode" and
 195         * "Setting General Input Mode"
 196         */
 197
 198        spin_lock_irqsave(&p->lock, flags);
 199
 200        /* Configure postive logic in POSNEG */
 201        gpio_rcar_modify_bit(p, POSNEG, gpio, false);
 202
 203        /* Select "General Input/Output Mode" in IOINTSEL */
 204        gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
 205
 206        /* Select Input Mode or Output Mode in INOUTSEL */
 207        gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
 208
 209        spin_unlock_irqrestore(&p->lock, flags);
 210}
 211
 212static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
 213{
 214        return pinctrl_request_gpio(chip->base + offset);
 215}
 216
 217static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
 218{
 219        pinctrl_free_gpio(chip->base + offset);
 220
 221        /* Set the GPIO as an input to ensure that the next GPIO request won't
 222         * drive the GPIO pin as an output.
 223         */
 224        gpio_rcar_config_general_input_output_mode(chip, offset, false);
 225}
 226
 227static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
 228{
 229        gpio_rcar_config_general_input_output_mode(chip, offset, false);
 230        return 0;
 231}
 232
 233static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
 234{
 235        u32 bit = BIT(offset);
 236
 237        /* testing on r8a7790 shows that INDT does not show correct pin state
 238         * when configured as output, so use OUTDT in case of output pins */
 239        if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit)
 240                return (int)(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit);
 241        else
 242                return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit);
 243}
 244
 245static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
 246{
 247        struct gpio_rcar_priv *p = gpio_to_priv(chip);
 248        unsigned long flags;
 249
 250        spin_lock_irqsave(&p->lock, flags);
 251        gpio_rcar_modify_bit(p, OUTDT, offset, value);
 252        spin_unlock_irqrestore(&p->lock, flags);
 253}
 254
 255static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
 256                                      int value)
 257{
 258        /* write GPIO value to output before selecting output mode of pin */
 259        gpio_rcar_set(chip, offset, value);
 260        gpio_rcar_config_general_input_output_mode(chip, offset, true);
 261        return 0;
 262}
 263
 264static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
 265{
 266        return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
 267}
 268
 269static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int virq,
 270                                 irq_hw_number_t hw)
 271{
 272        struct gpio_rcar_priv *p = h->host_data;
 273
 274        dev_dbg(&p->pdev->dev, "map hw irq = %d, virq = %d\n", (int)hw, virq);
 275
 276        irq_set_chip_data(virq, h->host_data);
 277        irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
 278        set_irq_flags(virq, IRQF_VALID); /* kill me now */
 279        return 0;
 280}
 281
 282static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
 283        .map    = gpio_rcar_irq_domain_map,
 284};
 285
 286static void gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
 287{
 288        struct gpio_rcar_config *pdata = p->pdev->dev.platform_data;
 289        struct device_node *np = p->pdev->dev.of_node;
 290        struct of_phandle_args args;
 291        int ret;
 292
 293        if (pdata) {
 294                p->config = *pdata;
 295        } else if (IS_ENABLED(CONFIG_OF) && np) {
 296                ret = of_parse_phandle_with_args(np, "gpio-ranges",
 297                                "#gpio-range-cells", 0, &args);
 298                p->config.number_of_pins = ret == 0 && args.args_count == 3
 299                                         ? args.args[2]
 300                                         : RCAR_MAX_GPIO_PER_BANK;
 301                p->config.gpio_base = -1;
 302        }
 303
 304        if (p->config.number_of_pins == 0 ||
 305            p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) {
 306                dev_warn(&p->pdev->dev,
 307                         "Invalid number of gpio lines %u, using %u\n",
 308                         p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK);
 309                p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK;
 310        }
 311}
 312
 313static int gpio_rcar_probe(struct platform_device *pdev)
 314{
 315        struct gpio_rcar_priv *p;
 316        struct resource *io, *irq;
 317        struct gpio_chip *gpio_chip;
 318        struct irq_chip *irq_chip;
 319        const char *name = dev_name(&pdev->dev);
 320        int ret;
 321
 322        p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
 323        if (!p) {
 324                dev_err(&pdev->dev, "failed to allocate driver data\n");
 325                ret = -ENOMEM;
 326                goto err0;
 327        }
 328
 329        p->pdev = pdev;
 330        spin_lock_init(&p->lock);
 331
 332        /* Get device configuration from DT node or platform data. */
 333        gpio_rcar_parse_pdata(p);
 334
 335        platform_set_drvdata(pdev, p);
 336
 337        io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 338        irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 339
 340        if (!io || !irq) {
 341                dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
 342                ret = -EINVAL;
 343                goto err0;
 344        }
 345
 346        p->base = devm_ioremap_nocache(&pdev->dev, io->start,
 347                                       resource_size(io));
 348        if (!p->base) {
 349                dev_err(&pdev->dev, "failed to remap I/O memory\n");
 350                ret = -ENXIO;
 351                goto err0;
 352        }
 353
 354        gpio_chip = &p->gpio_chip;
 355        gpio_chip->request = gpio_rcar_request;
 356        gpio_chip->free = gpio_rcar_free;
 357        gpio_chip->direction_input = gpio_rcar_direction_input;
 358        gpio_chip->get = gpio_rcar_get;
 359        gpio_chip->direction_output = gpio_rcar_direction_output;
 360        gpio_chip->set = gpio_rcar_set;
 361        gpio_chip->to_irq = gpio_rcar_to_irq;
 362        gpio_chip->label = name;
 363        gpio_chip->dev = &pdev->dev;
 364        gpio_chip->owner = THIS_MODULE;
 365        gpio_chip->base = p->config.gpio_base;
 366        gpio_chip->ngpio = p->config.number_of_pins;
 367
 368        irq_chip = &p->irq_chip;
 369        irq_chip->name = name;
 370        irq_chip->irq_mask = gpio_rcar_irq_disable;
 371        irq_chip->irq_unmask = gpio_rcar_irq_enable;
 372        irq_chip->irq_enable = gpio_rcar_irq_enable;
 373        irq_chip->irq_disable = gpio_rcar_irq_disable;
 374        irq_chip->irq_set_type = gpio_rcar_irq_set_type;
 375        irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED;
 376
 377        p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
 378                                              p->config.number_of_pins,
 379                                              p->config.irq_base,
 380                                              &gpio_rcar_irq_domain_ops, p);
 381        if (!p->irq_domain) {
 382                ret = -ENXIO;
 383                dev_err(&pdev->dev, "cannot initialize irq domain\n");
 384                goto err1;
 385        }
 386
 387        if (devm_request_irq(&pdev->dev, irq->start,
 388                             gpio_rcar_irq_handler, IRQF_SHARED, name, p)) {
 389                dev_err(&pdev->dev, "failed to request IRQ\n");
 390                ret = -ENOENT;
 391                goto err1;
 392        }
 393
 394        ret = gpiochip_add(gpio_chip);
 395        if (ret) {
 396                dev_err(&pdev->dev, "failed to add GPIO controller\n");
 397                goto err1;
 398        }
 399
 400        dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins);
 401
 402        /* warn in case of mismatch if irq base is specified */
 403        if (p->config.irq_base) {
 404                ret = irq_find_mapping(p->irq_domain, 0);
 405                if (p->config.irq_base != ret)
 406                        dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n",
 407                                 p->config.irq_base, ret);
 408        }
 409
 410        if (p->config.pctl_name) {
 411                ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
 412                                             gpio_chip->base, gpio_chip->ngpio);
 413                if (ret < 0)
 414                        dev_warn(&pdev->dev, "failed to add pin range\n");
 415        }
 416
 417        return 0;
 418
 419err1:
 420        irq_domain_remove(p->irq_domain);
 421err0:
 422        return ret;
 423}
 424
 425static int gpio_rcar_remove(struct platform_device *pdev)
 426{
 427        struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
 428        int ret;
 429
 430        ret = gpiochip_remove(&p->gpio_chip);
 431        if (ret)
 432                return ret;
 433
 434        irq_domain_remove(p->irq_domain);
 435        return 0;
 436}
 437
 438#ifdef CONFIG_OF
 439static const struct of_device_id gpio_rcar_of_table[] = {
 440        {
 441                .compatible = "renesas,gpio-rcar",
 442        },
 443        { },
 444};
 445
 446MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
 447#endif
 448
 449static struct platform_driver gpio_rcar_device_driver = {
 450        .probe          = gpio_rcar_probe,
 451        .remove         = gpio_rcar_remove,
 452        .driver         = {
 453                .name   = "gpio_rcar",
 454                .of_match_table = of_match_ptr(gpio_rcar_of_table),
 455        }
 456};
 457
 458module_platform_driver(gpio_rcar_device_driver);
 459
 460MODULE_AUTHOR("Magnus Damm");
 461MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
 462MODULE_LICENSE("GPL v2");
 463
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