linux/drivers/firewire/ohci.c
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   1/*
   2 * Driver for OHCI 1394 controllers
   3 *
   4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software Foundation,
  18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19 */
  20
  21#include <linux/bitops.h>
  22#include <linux/bug.h>
  23#include <linux/compiler.h>
  24#include <linux/delay.h>
  25#include <linux/device.h>
  26#include <linux/dma-mapping.h>
  27#include <linux/firewire.h>
  28#include <linux/firewire-constants.h>
  29#include <linux/init.h>
  30#include <linux/interrupt.h>
  31#include <linux/io.h>
  32#include <linux/kernel.h>
  33#include <linux/list.h>
  34#include <linux/mm.h>
  35#include <linux/module.h>
  36#include <linux/moduleparam.h>
  37#include <linux/mutex.h>
  38#include <linux/pci.h>
  39#include <linux/pci_ids.h>
  40#include <linux/slab.h>
  41#include <linux/spinlock.h>
  42#include <linux/string.h>
  43#include <linux/time.h>
  44#include <linux/vmalloc.h>
  45#include <linux/workqueue.h>
  46
  47#include <asm/byteorder.h>
  48#include <asm/page.h>
  49
  50#ifdef CONFIG_PPC_PMAC
  51#include <asm/pmac_feature.h>
  52#endif
  53
  54#include "core.h"
  55#include "ohci.h"
  56
  57#define ohci_info(ohci, f, args...)     dev_info(ohci->card.device, f, ##args)
  58#define ohci_notice(ohci, f, args...)   dev_notice(ohci->card.device, f, ##args)
  59#define ohci_err(ohci, f, args...)      dev_err(ohci->card.device, f, ##args)
  60
  61#define DESCRIPTOR_OUTPUT_MORE          0
  62#define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  63#define DESCRIPTOR_INPUT_MORE           (2 << 12)
  64#define DESCRIPTOR_INPUT_LAST           (3 << 12)
  65#define DESCRIPTOR_STATUS               (1 << 11)
  66#define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  67#define DESCRIPTOR_PING                 (1 << 7)
  68#define DESCRIPTOR_YY                   (1 << 6)
  69#define DESCRIPTOR_NO_IRQ               (0 << 4)
  70#define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  71#define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  72#define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  73#define DESCRIPTOR_WAIT                 (3 << 0)
  74
  75#define DESCRIPTOR_CMD                  (0xf << 12)
  76
  77struct descriptor {
  78        __le16 req_count;
  79        __le16 control;
  80        __le32 data_address;
  81        __le32 branch_address;
  82        __le16 res_count;
  83        __le16 transfer_status;
  84} __attribute__((aligned(16)));
  85
  86#define CONTROL_SET(regs)       (regs)
  87#define CONTROL_CLEAR(regs)     ((regs) + 4)
  88#define COMMAND_PTR(regs)       ((regs) + 12)
  89#define CONTEXT_MATCH(regs)     ((regs) + 16)
  90
  91#define AR_BUFFER_SIZE  (32*1024)
  92#define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  93/* we need at least two pages for proper list management */
  94#define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  95
  96#define MAX_ASYNC_PAYLOAD       4096
  97#define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
  98#define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  99
 100struct ar_context {
 101        struct fw_ohci *ohci;
 102        struct page *pages[AR_BUFFERS];
 103        void *buffer;
 104        struct descriptor *descriptors;
 105        dma_addr_t descriptors_bus;
 106        void *pointer;
 107        unsigned int last_buffer_index;
 108        u32 regs;
 109        struct tasklet_struct tasklet;
 110};
 111
 112struct context;
 113
 114typedef int (*descriptor_callback_t)(struct context *ctx,
 115                                     struct descriptor *d,
 116                                     struct descriptor *last);
 117
 118/*
 119 * A buffer that contains a block of DMA-able coherent memory used for
 120 * storing a portion of a DMA descriptor program.
 121 */
 122struct descriptor_buffer {
 123        struct list_head list;
 124        dma_addr_t buffer_bus;
 125        size_t buffer_size;
 126        size_t used;
 127        struct descriptor buffer[0];
 128};
 129
 130struct context {
 131        struct fw_ohci *ohci;
 132        u32 regs;
 133        int total_allocation;
 134        u32 current_bus;
 135        bool running;
 136        bool flushing;
 137
 138        /*
 139         * List of page-sized buffers for storing DMA descriptors.
 140         * Head of list contains buffers in use and tail of list contains
 141         * free buffers.
 142         */
 143        struct list_head buffer_list;
 144
 145        /*
 146         * Pointer to a buffer inside buffer_list that contains the tail
 147         * end of the current DMA program.
 148         */
 149        struct descriptor_buffer *buffer_tail;
 150
 151        /*
 152         * The descriptor containing the branch address of the first
 153         * descriptor that has not yet been filled by the device.
 154         */
 155        struct descriptor *last;
 156
 157        /*
 158         * The last descriptor block in the DMA program. It contains the branch
 159         * address that must be updated upon appending a new descriptor.
 160         */
 161        struct descriptor *prev;
 162        int prev_z;
 163
 164        descriptor_callback_t callback;
 165
 166        struct tasklet_struct tasklet;
 167};
 168
 169#define IT_HEADER_SY(v)          ((v) <<  0)
 170#define IT_HEADER_TCODE(v)       ((v) <<  4)
 171#define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 172#define IT_HEADER_TAG(v)         ((v) << 14)
 173#define IT_HEADER_SPEED(v)       ((v) << 16)
 174#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 175
 176struct iso_context {
 177        struct fw_iso_context base;
 178        struct context context;
 179        void *header;
 180        size_t header_length;
 181        unsigned long flushing_completions;
 182        u32 mc_buffer_bus;
 183        u16 mc_completed;
 184        u16 last_timestamp;
 185        u8 sync;
 186        u8 tags;
 187};
 188
 189#define CONFIG_ROM_SIZE 1024
 190
 191struct fw_ohci {
 192        struct fw_card card;
 193
 194        __iomem char *registers;
 195        int node_id;
 196        int generation;
 197        int request_generation; /* for timestamping incoming requests */
 198        unsigned quirks;
 199        unsigned int pri_req_max;
 200        u32 bus_time;
 201        bool bus_time_running;
 202        bool is_root;
 203        bool csr_state_setclear_abdicate;
 204        int n_ir;
 205        int n_it;
 206        /*
 207         * Spinlock for accessing fw_ohci data.  Never call out of
 208         * this driver with this lock held.
 209         */
 210        spinlock_t lock;
 211
 212        struct mutex phy_reg_mutex;
 213
 214        void *misc_buffer;
 215        dma_addr_t misc_buffer_bus;
 216
 217        struct ar_context ar_request_ctx;
 218        struct ar_context ar_response_ctx;
 219        struct context at_request_ctx;
 220        struct context at_response_ctx;
 221
 222        u32 it_context_support;
 223        u32 it_context_mask;     /* unoccupied IT contexts */
 224        struct iso_context *it_context_list;
 225        u64 ir_context_channels; /* unoccupied channels */
 226        u32 ir_context_support;
 227        u32 ir_context_mask;     /* unoccupied IR contexts */
 228        struct iso_context *ir_context_list;
 229        u64 mc_channels; /* channels in use by the multichannel IR context */
 230        bool mc_allocated;
 231
 232        __be32    *config_rom;
 233        dma_addr_t config_rom_bus;
 234        __be32    *next_config_rom;
 235        dma_addr_t next_config_rom_bus;
 236        __be32     next_header;
 237
 238        __le32    *self_id_cpu;
 239        dma_addr_t self_id_bus;
 240        struct work_struct bus_reset_work;
 241
 242        u32 self_id_buffer[512];
 243};
 244
 245static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 246{
 247        return container_of(card, struct fw_ohci, card);
 248}
 249
 250#define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 251#define IR_CONTEXT_BUFFER_FILL          0x80000000
 252#define IR_CONTEXT_ISOCH_HEADER         0x40000000
 253#define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 254#define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 255#define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 256
 257#define CONTEXT_RUN     0x8000
 258#define CONTEXT_WAKE    0x1000
 259#define CONTEXT_DEAD    0x0800
 260#define CONTEXT_ACTIVE  0x0400
 261
 262#define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 263#define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 264#define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 265
 266#define OHCI1394_REGISTER_SIZE          0x800
 267#define OHCI1394_PCI_HCI_Control        0x40
 268#define SELF_ID_BUF_SIZE                0x800
 269#define OHCI_TCODE_PHY_PACKET           0x0e
 270#define OHCI_VERSION_1_1                0x010010
 271
 272static char ohci_driver_name[] = KBUILD_MODNAME;
 273
 274#define PCI_DEVICE_ID_AGERE_FW643       0x5901
 275#define PCI_DEVICE_ID_CREATIVE_SB1394   0x4001
 276#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 277#define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 278#define PCI_DEVICE_ID_TI_TSB12LV26      0x8020
 279#define PCI_DEVICE_ID_TI_TSB82AA2       0x8025
 280#define PCI_DEVICE_ID_VIA_VT630X        0x3044
 281#define PCI_VENDOR_ID_PINNACLE_SYSTEMS  0x11bd
 282#define PCI_REV_ID_VIA_VT6306           0x46
 283
 284#define QUIRK_CYCLE_TIMER               1
 285#define QUIRK_RESET_PACKET              2
 286#define QUIRK_BE_HEADERS                4
 287#define QUIRK_NO_1394A                  8
 288#define QUIRK_NO_MSI                    16
 289#define QUIRK_TI_SLLZ059                32
 290#define QUIRK_IR_WAKE                   64
 291#define QUIRK_PHY_LCTRL_TIMEOUT         128
 292
 293/* In case of multiple matches in ohci_quirks[], only the first one is used. */
 294static const struct {
 295        unsigned short vendor, device, revision, flags;
 296} ohci_quirks[] = {
 297        {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 298                QUIRK_CYCLE_TIMER},
 299
 300        {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 301                QUIRK_BE_HEADERS},
 302
 303        {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 304                QUIRK_PHY_LCTRL_TIMEOUT | QUIRK_NO_MSI},
 305
 306        {PCI_VENDOR_ID_ATT, PCI_ANY_ID, PCI_ANY_ID,
 307                QUIRK_PHY_LCTRL_TIMEOUT},
 308
 309        {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
 310                QUIRK_RESET_PACKET},
 311
 312        {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 313                QUIRK_NO_MSI},
 314
 315        {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 316                QUIRK_CYCLE_TIMER},
 317
 318        {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
 319                QUIRK_NO_MSI},
 320
 321        {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 322                QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 323
 324        {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 325                QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 326
 327        {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
 328                QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 329
 330        {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
 331                QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 332
 333        {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 334                QUIRK_RESET_PACKET},
 335
 336        {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
 337                QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
 338
 339        {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 340                QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 341};
 342
 343/* This overrides anything that was found in ohci_quirks[]. */
 344static int param_quirks;
 345module_param_named(quirks, param_quirks, int, 0644);
 346MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 347        ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 348        ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 349        ", AR/selfID endianness = "     __stringify(QUIRK_BE_HEADERS)
 350        ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 351        ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 352        ", TI SLLZ059 erratum = "       __stringify(QUIRK_TI_SLLZ059)
 353        ", IR wake unreliable = "       __stringify(QUIRK_IR_WAKE)
 354        ", phy LCtrl timeout = "        __stringify(QUIRK_PHY_LCTRL_TIMEOUT)
 355        ")");
 356
 357#define OHCI_PARAM_DEBUG_AT_AR          1
 358#define OHCI_PARAM_DEBUG_SELFIDS        2
 359#define OHCI_PARAM_DEBUG_IRQS           4
 360#define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 361
 362static int param_debug;
 363module_param_named(debug, param_debug, int, 0644);
 364MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 365        ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 366        ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 367        ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 368        ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 369        ", or a combination, or all = -1)");
 370
 371static void log_irqs(struct fw_ohci *ohci, u32 evt)
 372{
 373        if (likely(!(param_debug &
 374                        (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 375                return;
 376
 377        if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 378            !(evt & OHCI1394_busReset))
 379                return;
 380
 381        ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 382            evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 383            evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 384            evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 385            evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 386            evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 387            evt & OHCI1394_isochRx              ? " IR"                 : "",
 388            evt & OHCI1394_isochTx              ? " IT"                 : "",
 389            evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 390            evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 391            evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 392            evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 393            evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 394            evt & OHCI1394_unrecoverableError   ? " unrecoverableError" : "",
 395            evt & OHCI1394_busReset             ? " busReset"           : "",
 396            evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 397                    OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 398                    OHCI1394_respTxComplete | OHCI1394_isochRx |
 399                    OHCI1394_isochTx | OHCI1394_postedWriteErr |
 400                    OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 401                    OHCI1394_cycleInconsistent |
 402                    OHCI1394_regAccessFail | OHCI1394_busReset)
 403                                                ? " ?"                  : "");
 404}
 405
 406static const char *speed[] = {
 407        [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 408};
 409static const char *power[] = {
 410        [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 411        [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 412};
 413static const char port[] = { '.', '-', 'p', 'c', };
 414
 415static char _p(u32 *s, int shift)
 416{
 417        return port[*s >> shift & 3];
 418}
 419
 420static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
 421{
 422        u32 *s;
 423
 424        if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 425                return;
 426
 427        ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
 428                    self_id_count, generation, ohci->node_id);
 429
 430        for (s = ohci->self_id_buffer; self_id_count--; ++s)
 431                if ((*s & 1 << 23) == 0)
 432                        ohci_notice(ohci,
 433                            "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
 434                            *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 435                            speed[*s >> 14 & 3], *s >> 16 & 63,
 436                            power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 437                            *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 438                else
 439                        ohci_notice(ohci,
 440                            "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 441                            *s, *s >> 24 & 63,
 442                            _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 443                            _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 444}
 445
 446static const char *evts[] = {
 447        [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 448        [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 449        [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 450        [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 451        [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 452        [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 453        [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 454        [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 455        [0x10] = "-reserved-",          [0x11] = "ack_complete",
 456        [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 457        [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 458        [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 459        [0x18] = "-reserved-",          [0x19] = "-reserved-",
 460        [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 461        [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 462        [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 463        [0x20] = "pending/cancelled",
 464};
 465static const char *tcodes[] = {
 466        [0x0] = "QW req",               [0x1] = "BW req",
 467        [0x2] = "W resp",               [0x3] = "-reserved-",
 468        [0x4] = "QR req",               [0x5] = "BR req",
 469        [0x6] = "QR resp",              [0x7] = "BR resp",
 470        [0x8] = "cycle start",          [0x9] = "Lk req",
 471        [0xa] = "async stream packet",  [0xb] = "Lk resp",
 472        [0xc] = "-reserved-",           [0xd] = "-reserved-",
 473        [0xe] = "link internal",        [0xf] = "-reserved-",
 474};
 475
 476static void log_ar_at_event(struct fw_ohci *ohci,
 477                            char dir, int speed, u32 *header, int evt)
 478{
 479        int tcode = header[0] >> 4 & 0xf;
 480        char specific[12];
 481
 482        if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 483                return;
 484
 485        if (unlikely(evt >= ARRAY_SIZE(evts)))
 486                        evt = 0x1f;
 487
 488        if (evt == OHCI1394_evt_bus_reset) {
 489                ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
 490                            dir, (header[2] >> 16) & 0xff);
 491                return;
 492        }
 493
 494        switch (tcode) {
 495        case 0x0: case 0x6: case 0x8:
 496                snprintf(specific, sizeof(specific), " = %08x",
 497                         be32_to_cpu((__force __be32)header[3]));
 498                break;
 499        case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 500                snprintf(specific, sizeof(specific), " %x,%x",
 501                         header[3] >> 16, header[3] & 0xffff);
 502                break;
 503        default:
 504                specific[0] = '\0';
 505        }
 506
 507        switch (tcode) {
 508        case 0xa:
 509                ohci_notice(ohci, "A%c %s, %s\n",
 510                            dir, evts[evt], tcodes[tcode]);
 511                break;
 512        case 0xe:
 513                ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
 514                            dir, evts[evt], header[1], header[2]);
 515                break;
 516        case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 517                ohci_notice(ohci,
 518                            "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n",
 519                            dir, speed, header[0] >> 10 & 0x3f,
 520                            header[1] >> 16, header[0] >> 16, evts[evt],
 521                            tcodes[tcode], header[1] & 0xffff, header[2], specific);
 522                break;
 523        default:
 524                ohci_notice(ohci,
 525                            "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
 526                            dir, speed, header[0] >> 10 & 0x3f,
 527                            header[1] >> 16, header[0] >> 16, evts[evt],
 528                            tcodes[tcode], specific);
 529        }
 530}
 531
 532static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 533{
 534        writel(data, ohci->registers + offset);
 535}
 536
 537static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 538{
 539        return readl(ohci->registers + offset);
 540}
 541
 542static inline void flush_writes(const struct fw_ohci *ohci)
 543{
 544        /* Do a dummy read to flush writes. */
 545        reg_read(ohci, OHCI1394_Version);
 546}
 547
 548/*
 549 * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
 550 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
 551 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
 552 * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
 553 */
 554static int read_phy_reg(struct fw_ohci *ohci, int addr)
 555{
 556        u32 val;
 557        int i;
 558
 559        reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 560        for (i = 0; i < 3 + 100; i++) {
 561                val = reg_read(ohci, OHCI1394_PhyControl);
 562                if (!~val)
 563                        return -ENODEV; /* Card was ejected. */
 564
 565                if (val & OHCI1394_PhyControl_ReadDone)
 566                        return OHCI1394_PhyControl_ReadData(val);
 567
 568                /*
 569                 * Try a few times without waiting.  Sleeping is necessary
 570                 * only when the link/PHY interface is busy.
 571                 */
 572                if (i >= 3)
 573                        msleep(1);
 574        }
 575        ohci_err(ohci, "failed to read phy reg %d\n", addr);
 576        dump_stack();
 577
 578        return -EBUSY;
 579}
 580
 581static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 582{
 583        int i;
 584
 585        reg_write(ohci, OHCI1394_PhyControl,
 586                  OHCI1394_PhyControl_Write(addr, val));
 587        for (i = 0; i < 3 + 100; i++) {
 588                val = reg_read(ohci, OHCI1394_PhyControl);
 589                if (!~val)
 590                        return -ENODEV; /* Card was ejected. */
 591
 592                if (!(val & OHCI1394_PhyControl_WritePending))
 593                        return 0;
 594
 595                if (i >= 3)
 596                        msleep(1);
 597        }
 598        ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
 599        dump_stack();
 600
 601        return -EBUSY;
 602}
 603
 604static int update_phy_reg(struct fw_ohci *ohci, int addr,
 605                          int clear_bits, int set_bits)
 606{
 607        int ret = read_phy_reg(ohci, addr);
 608        if (ret < 0)
 609                return ret;
 610
 611        /*
 612         * The interrupt status bits are cleared by writing a one bit.
 613         * Avoid clearing them unless explicitly requested in set_bits.
 614         */
 615        if (addr == 5)
 616                clear_bits |= PHY_INT_STATUS_BITS;
 617
 618        return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 619}
 620
 621static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 622{
 623        int ret;
 624
 625        ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 626        if (ret < 0)
 627                return ret;
 628
 629        return read_phy_reg(ohci, addr);
 630}
 631
 632static int ohci_read_phy_reg(struct fw_card *card, int addr)
 633{
 634        struct fw_ohci *ohci = fw_ohci(card);
 635        int ret;
 636
 637        mutex_lock(&ohci->phy_reg_mutex);
 638        ret = read_phy_reg(ohci, addr);
 639        mutex_unlock(&ohci->phy_reg_mutex);
 640
 641        return ret;
 642}
 643
 644static int ohci_update_phy_reg(struct fw_card *card, int addr,
 645                               int clear_bits, int set_bits)
 646{
 647        struct fw_ohci *ohci = fw_ohci(card);
 648        int ret;
 649
 650        mutex_lock(&ohci->phy_reg_mutex);
 651        ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 652        mutex_unlock(&ohci->phy_reg_mutex);
 653
 654        return ret;
 655}
 656
 657static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 658{
 659        return page_private(ctx->pages[i]);
 660}
 661
 662static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 663{
 664        struct descriptor *d;
 665
 666        d = &ctx->descriptors[index];
 667        d->branch_address  &= cpu_to_le32(~0xf);
 668        d->res_count       =  cpu_to_le16(PAGE_SIZE);
 669        d->transfer_status =  0;
 670
 671        wmb(); /* finish init of new descriptors before branch_address update */
 672        d = &ctx->descriptors[ctx->last_buffer_index];
 673        d->branch_address  |= cpu_to_le32(1);
 674
 675        ctx->last_buffer_index = index;
 676
 677        reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 678}
 679
 680static void ar_context_release(struct ar_context *ctx)
 681{
 682        unsigned int i;
 683
 684        if (ctx->buffer)
 685                vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
 686
 687        for (i = 0; i < AR_BUFFERS; i++)
 688                if (ctx->pages[i]) {
 689                        dma_unmap_page(ctx->ohci->card.device,
 690                                       ar_buffer_bus(ctx, i),
 691                                       PAGE_SIZE, DMA_FROM_DEVICE);
 692                        __free_page(ctx->pages[i]);
 693                }
 694}
 695
 696static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 697{
 698        struct fw_ohci *ohci = ctx->ohci;
 699
 700        if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 701                reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 702                flush_writes(ohci);
 703
 704                ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
 705        }
 706        /* FIXME: restart? */
 707}
 708
 709static inline unsigned int ar_next_buffer_index(unsigned int index)
 710{
 711        return (index + 1) % AR_BUFFERS;
 712}
 713
 714static inline unsigned int ar_prev_buffer_index(unsigned int index)
 715{
 716        return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
 717}
 718
 719static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 720{
 721        return ar_next_buffer_index(ctx->last_buffer_index);
 722}
 723
 724/*
 725 * We search for the buffer that contains the last AR packet DMA data written
 726 * by the controller.
 727 */
 728static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 729                                                 unsigned int *buffer_offset)
 730{
 731        unsigned int i, next_i, last = ctx->last_buffer_index;
 732        __le16 res_count, next_res_count;
 733
 734        i = ar_first_buffer_index(ctx);
 735        res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
 736
 737        /* A buffer that is not yet completely filled must be the last one. */
 738        while (i != last && res_count == 0) {
 739
 740                /* Peek at the next descriptor. */
 741                next_i = ar_next_buffer_index(i);
 742                rmb(); /* read descriptors in order */
 743                next_res_count = ACCESS_ONCE(
 744                                ctx->descriptors[next_i].res_count);
 745                /*
 746                 * If the next descriptor is still empty, we must stop at this
 747                 * descriptor.
 748                 */
 749                if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 750                        /*
 751                         * The exception is when the DMA data for one packet is
 752                         * split over three buffers; in this case, the middle
 753                         * buffer's descriptor might be never updated by the
 754                         * controller and look still empty, and we have to peek
 755                         * at the third one.
 756                         */
 757                        if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 758                                next_i = ar_next_buffer_index(next_i);
 759                                rmb();
 760                                next_res_count = ACCESS_ONCE(
 761                                        ctx->descriptors[next_i].res_count);
 762                                if (next_res_count != cpu_to_le16(PAGE_SIZE))
 763                                        goto next_buffer_is_active;
 764                        }
 765
 766                        break;
 767                }
 768
 769next_buffer_is_active:
 770                i = next_i;
 771                res_count = next_res_count;
 772        }
 773
 774        rmb(); /* read res_count before the DMA data */
 775
 776        *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 777        if (*buffer_offset > PAGE_SIZE) {
 778                *buffer_offset = 0;
 779                ar_context_abort(ctx, "corrupted descriptor");
 780        }
 781
 782        return i;
 783}
 784
 785static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 786                                    unsigned int end_buffer_index,
 787                                    unsigned int end_buffer_offset)
 788{
 789        unsigned int i;
 790
 791        i = ar_first_buffer_index(ctx);
 792        while (i != end_buffer_index) {
 793                dma_sync_single_for_cpu(ctx->ohci->card.device,
 794                                        ar_buffer_bus(ctx, i),
 795                                        PAGE_SIZE, DMA_FROM_DEVICE);
 796                i = ar_next_buffer_index(i);
 797        }
 798        if (end_buffer_offset > 0)
 799                dma_sync_single_for_cpu(ctx->ohci->card.device,
 800                                        ar_buffer_bus(ctx, i),
 801                                        end_buffer_offset, DMA_FROM_DEVICE);
 802}
 803
 804#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 805#define cond_le32_to_cpu(v) \
 806        (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 807#else
 808#define cond_le32_to_cpu(v) le32_to_cpu(v)
 809#endif
 810
 811static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 812{
 813        struct fw_ohci *ohci = ctx->ohci;
 814        struct fw_packet p;
 815        u32 status, length, tcode;
 816        int evt;
 817
 818        p.header[0] = cond_le32_to_cpu(buffer[0]);
 819        p.header[1] = cond_le32_to_cpu(buffer[1]);
 820        p.header[2] = cond_le32_to_cpu(buffer[2]);
 821
 822        tcode = (p.header[0] >> 4) & 0x0f;
 823        switch (tcode) {
 824        case TCODE_WRITE_QUADLET_REQUEST:
 825        case TCODE_READ_QUADLET_RESPONSE:
 826                p.header[3] = (__force __u32) buffer[3];
 827                p.header_length = 16;
 828                p.payload_length = 0;
 829                break;
 830
 831        case TCODE_READ_BLOCK_REQUEST :
 832                p.header[3] = cond_le32_to_cpu(buffer[3]);
 833                p.header_length = 16;
 834                p.payload_length = 0;
 835                break;
 836
 837        case TCODE_WRITE_BLOCK_REQUEST:
 838        case TCODE_READ_BLOCK_RESPONSE:
 839        case TCODE_LOCK_REQUEST:
 840        case TCODE_LOCK_RESPONSE:
 841                p.header[3] = cond_le32_to_cpu(buffer[3]);
 842                p.header_length = 16;
 843                p.payload_length = p.header[3] >> 16;
 844                if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 845                        ar_context_abort(ctx, "invalid packet length");
 846                        return NULL;
 847                }
 848                break;
 849
 850        case TCODE_WRITE_RESPONSE:
 851        case TCODE_READ_QUADLET_REQUEST:
 852        case OHCI_TCODE_PHY_PACKET:
 853                p.header_length = 12;
 854                p.payload_length = 0;
 855                break;
 856
 857        default:
 858                ar_context_abort(ctx, "invalid tcode");
 859                return NULL;
 860        }
 861
 862        p.payload = (void *) buffer + p.header_length;
 863
 864        /* FIXME: What to do about evt_* errors? */
 865        length = (p.header_length + p.payload_length + 3) / 4;
 866        status = cond_le32_to_cpu(buffer[length]);
 867        evt    = (status >> 16) & 0x1f;
 868
 869        p.ack        = evt - 16;
 870        p.speed      = (status >> 21) & 0x7;
 871        p.timestamp  = status & 0xffff;
 872        p.generation = ohci->request_generation;
 873
 874        log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
 875
 876        /*
 877         * Several controllers, notably from NEC and VIA, forget to
 878         * write ack_complete status at PHY packet reception.
 879         */
 880        if (evt == OHCI1394_evt_no_status &&
 881            (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 882                p.ack = ACK_COMPLETE;
 883
 884        /*
 885         * The OHCI bus reset handler synthesizes a PHY packet with
 886         * the new generation number when a bus reset happens (see
 887         * section 8.4.2.3).  This helps us determine when a request
 888         * was received and make sure we send the response in the same
 889         * generation.  We only need this for requests; for responses
 890         * we use the unique tlabel for finding the matching
 891         * request.
 892         *
 893         * Alas some chips sometimes emit bus reset packets with a
 894         * wrong generation.  We set the correct generation for these
 895         * at a slightly incorrect time (in bus_reset_work).
 896         */
 897        if (evt == OHCI1394_evt_bus_reset) {
 898                if (!(ohci->quirks & QUIRK_RESET_PACKET))
 899                        ohci->request_generation = (p.header[2] >> 16) & 0xff;
 900        } else if (ctx == &ohci->ar_request_ctx) {
 901                fw_core_handle_request(&ohci->card, &p);
 902        } else {
 903                fw_core_handle_response(&ohci->card, &p);
 904        }
 905
 906        return buffer + length + 1;
 907}
 908
 909static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 910{
 911        void *next;
 912
 913        while (p < end) {
 914                next = handle_ar_packet(ctx, p);
 915                if (!next)
 916                        return p;
 917                p = next;
 918        }
 919
 920        return p;
 921}
 922
 923static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
 924{
 925        unsigned int i;
 926
 927        i = ar_first_buffer_index(ctx);
 928        while (i != end_buffer) {
 929                dma_sync_single_for_device(ctx->ohci->card.device,
 930                                           ar_buffer_bus(ctx, i),
 931                                           PAGE_SIZE, DMA_FROM_DEVICE);
 932                ar_context_link_page(ctx, i);
 933                i = ar_next_buffer_index(i);
 934        }
 935}
 936
 937static void ar_context_tasklet(unsigned long data)
 938{
 939        struct ar_context *ctx = (struct ar_context *)data;
 940        unsigned int end_buffer_index, end_buffer_offset;
 941        void *p, *end;
 942
 943        p = ctx->pointer;
 944        if (!p)
 945                return;
 946
 947        end_buffer_index = ar_search_last_active_buffer(ctx,
 948                                                        &end_buffer_offset);
 949        ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
 950        end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
 951
 952        if (end_buffer_index < ar_first_buffer_index(ctx)) {
 953                /*
 954                 * The filled part of the overall buffer wraps around; handle
 955                 * all packets up to the buffer end here.  If the last packet
 956                 * wraps around, its tail will be visible after the buffer end
 957                 * because the buffer start pages are mapped there again.
 958                 */
 959                void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
 960                p = handle_ar_packets(ctx, p, buffer_end);
 961                if (p < buffer_end)
 962                        goto error;
 963                /* adjust p to point back into the actual buffer */
 964                p -= AR_BUFFERS * PAGE_SIZE;
 965        }
 966
 967        p = handle_ar_packets(ctx, p, end);
 968        if (p != end) {
 969                if (p > end)
 970                        ar_context_abort(ctx, "inconsistent descriptor");
 971                goto error;
 972        }
 973
 974        ctx->pointer = p;
 975        ar_recycle_buffers(ctx, end_buffer_index);
 976
 977        return;
 978
 979error:
 980        ctx->pointer = NULL;
 981}
 982
 983static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
 984                           unsigned int descriptors_offset, u32 regs)
 985{
 986        unsigned int i;
 987        dma_addr_t dma_addr;
 988        struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
 989        struct descriptor *d;
 990
 991        ctx->regs        = regs;
 992        ctx->ohci        = ohci;
 993        tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 994
 995        for (i = 0; i < AR_BUFFERS; i++) {
 996                ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
 997                if (!ctx->pages[i])
 998                        goto out_of_memory;
 999                dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
1000                                        0, PAGE_SIZE, DMA_FROM_DEVICE);
1001                if (dma_mapping_error(ohci->card.device, dma_addr)) {
1002                        __free_page(ctx->pages[i]);
1003                        ctx->pages[i] = NULL;
1004                        goto out_of_memory;
1005                }
1006                set_page_private(ctx->pages[i], dma_addr);
1007        }
1008
1009        for (i = 0; i < AR_BUFFERS; i++)
1010                pages[i]              = ctx->pages[i];
1011        for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1012                pages[AR_BUFFERS + i] = ctx->pages[i];
1013        ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
1014                                 -1, PAGE_KERNEL);
1015        if (!ctx->buffer)
1016                goto out_of_memory;
1017
1018        ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
1019        ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1020
1021        for (i = 0; i < AR_BUFFERS; i++) {
1022                d = &ctx->descriptors[i];
1023                d->req_count      = cpu_to_le16(PAGE_SIZE);
1024                d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1025                                                DESCRIPTOR_STATUS |
1026                                                DESCRIPTOR_BRANCH_ALWAYS);
1027                d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
1028                d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1029                        ar_next_buffer_index(i) * sizeof(struct descriptor));
1030        }
1031
1032        return 0;
1033
1034out_of_memory:
1035        ar_context_release(ctx);
1036
1037        return -ENOMEM;
1038}
1039
1040static void ar_context_run(struct ar_context *ctx)
1041{
1042        unsigned int i;
1043
1044        for (i = 0; i < AR_BUFFERS; i++)
1045                ar_context_link_page(ctx, i);
1046
1047        ctx->pointer = ctx->buffer;
1048
1049        reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1050        reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1051}
1052
1053static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1054{
1055        __le16 branch;
1056
1057        branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1058
1059        /* figure out which descriptor the branch address goes in */
1060        if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1061                return d;
1062        else
1063                return d + z - 1;
1064}
1065
1066static void context_tasklet(unsigned long data)
1067{
1068        struct context *ctx = (struct context *) data;
1069        struct descriptor *d, *last;
1070        u32 address;
1071        int z;
1072        struct descriptor_buffer *desc;
1073
1074        desc = list_entry(ctx->buffer_list.next,
1075                        struct descriptor_buffer, list);
1076        last = ctx->last;
1077        while (last->branch_address != 0) {
1078                struct descriptor_buffer *old_desc = desc;
1079                address = le32_to_cpu(last->branch_address);
1080                z = address & 0xf;
1081                address &= ~0xf;
1082                ctx->current_bus = address;
1083
1084                /* If the branch address points to a buffer outside of the
1085                 * current buffer, advance to the next buffer. */
1086                if (address < desc->buffer_bus ||
1087                                address >= desc->buffer_bus + desc->used)
1088                        desc = list_entry(desc->list.next,
1089                                        struct descriptor_buffer, list);
1090                d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1091                last = find_branch_descriptor(d, z);
1092
1093                if (!ctx->callback(ctx, d, last))
1094                        break;
1095
1096                if (old_desc != desc) {
1097                        /* If we've advanced to the next buffer, move the
1098                         * previous buffer to the free list. */
1099                        unsigned long flags;
1100                        old_desc->used = 0;
1101                        spin_lock_irqsave(&ctx->ohci->lock, flags);
1102                        list_move_tail(&old_desc->list, &ctx->buffer_list);
1103                        spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1104                }
1105                ctx->last = last;
1106        }
1107}
1108
1109/*
1110 * Allocate a new buffer and add it to the list of free buffers for this
1111 * context.  Must be called with ohci->lock held.
1112 */
1113static int context_add_buffer(struct context *ctx)
1114{
1115        struct descriptor_buffer *desc;
1116        dma_addr_t uninitialized_var(bus_addr);
1117        int offset;
1118
1119        /*
1120         * 16MB of descriptors should be far more than enough for any DMA
1121         * program.  This will catch run-away userspace or DoS attacks.
1122         */
1123        if (ctx->total_allocation >= 16*1024*1024)
1124                return -ENOMEM;
1125
1126        desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1127                        &bus_addr, GFP_ATOMIC);
1128        if (!desc)
1129                return -ENOMEM;
1130
1131        offset = (void *)&desc->buffer - (void *)desc;
1132        desc->buffer_size = PAGE_SIZE - offset;
1133        desc->buffer_bus = bus_addr + offset;
1134        desc->used = 0;
1135
1136        list_add_tail(&desc->list, &ctx->buffer_list);
1137        ctx->total_allocation += PAGE_SIZE;
1138
1139        return 0;
1140}
1141
1142static int context_init(struct context *ctx, struct fw_ohci *ohci,
1143                        u32 regs, descriptor_callback_t callback)
1144{
1145        ctx->ohci = ohci;
1146        ctx->regs = regs;
1147        ctx->total_allocation = 0;
1148
1149        INIT_LIST_HEAD(&ctx->buffer_list);
1150        if (context_add_buffer(ctx) < 0)
1151                return -ENOMEM;
1152
1153        ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1154                        struct descriptor_buffer, list);
1155
1156        tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1157        ctx->callback = callback;
1158
1159        /*
1160         * We put a dummy descriptor in the buffer that has a NULL
1161         * branch address and looks like it's been sent.  That way we
1162         * have a descriptor to append DMA programs to.
1163         */
1164        memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1165        ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1166        ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1167        ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1168        ctx->last = ctx->buffer_tail->buffer;
1169        ctx->prev = ctx->buffer_tail->buffer;
1170        ctx->prev_z = 1;
1171
1172        return 0;
1173}
1174
1175static void context_release(struct context *ctx)
1176{
1177        struct fw_card *card = &ctx->ohci->card;
1178        struct descriptor_buffer *desc, *tmp;
1179
1180        list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1181                dma_free_coherent(card->device, PAGE_SIZE, desc,
1182                        desc->buffer_bus -
1183                        ((void *)&desc->buffer - (void *)desc));
1184}
1185
1186/* Must be called with ohci->lock held */
1187static struct descriptor *context_get_descriptors(struct context *ctx,
1188                                                  int z, dma_addr_t *d_bus)
1189{
1190        struct descriptor *d = NULL;
1191        struct descriptor_buffer *desc = ctx->buffer_tail;
1192
1193        if (z * sizeof(*d) > desc->buffer_size)
1194                return NULL;
1195
1196        if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1197                /* No room for the descriptor in this buffer, so advance to the
1198                 * next one. */
1199
1200                if (desc->list.next == &ctx->buffer_list) {
1201                        /* If there is no free buffer next in the list,
1202                         * allocate one. */
1203                        if (context_add_buffer(ctx) < 0)
1204                                return NULL;
1205                }
1206                desc = list_entry(desc->list.next,
1207                                struct descriptor_buffer, list);
1208                ctx->buffer_tail = desc;
1209        }
1210
1211        d = desc->buffer + desc->used / sizeof(*d);
1212        memset(d, 0, z * sizeof(*d));
1213        *d_bus = desc->buffer_bus + desc->used;
1214
1215        return d;
1216}
1217
1218static void context_run(struct context *ctx, u32 extra)
1219{
1220        struct fw_ohci *ohci = ctx->ohci;
1221
1222        reg_write(ohci, COMMAND_PTR(ctx->regs),
1223                  le32_to_cpu(ctx->last->branch_address));
1224        reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1225        reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1226        ctx->running = true;
1227        flush_writes(ohci);
1228}
1229
1230static void context_append(struct context *ctx,
1231                           struct descriptor *d, int z, int extra)
1232{
1233        dma_addr_t d_bus;
1234        struct descriptor_buffer *desc = ctx->buffer_tail;
1235        struct descriptor *d_branch;
1236
1237        d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1238
1239        desc->used += (z + extra) * sizeof(*d);
1240
1241        wmb(); /* finish init of new descriptors before branch_address update */
1242
1243        d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
1244        d_branch->branch_address = cpu_to_le32(d_bus | z);
1245
1246        /*
1247         * VT6306 incorrectly checks only the single descriptor at the
1248         * CommandPtr when the wake bit is written, so if it's a
1249         * multi-descriptor block starting with an INPUT_MORE, put a copy of
1250         * the branch address in the first descriptor.
1251         *
1252         * Not doing this for transmit contexts since not sure how it interacts
1253         * with skip addresses.
1254         */
1255        if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
1256            d_branch != ctx->prev &&
1257            (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
1258             cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
1259                ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1260        }
1261
1262        ctx->prev = d;
1263        ctx->prev_z = z;
1264}
1265
1266static void context_stop(struct context *ctx)
1267{
1268        struct fw_ohci *ohci = ctx->ohci;
1269        u32 reg;
1270        int i;
1271
1272        reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1273        ctx->running = false;
1274
1275        for (i = 0; i < 1000; i++) {
1276                reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1277                if ((reg & CONTEXT_ACTIVE) == 0)
1278                        return;
1279
1280                if (i)
1281                        udelay(10);
1282        }
1283        ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
1284}
1285
1286struct driver_data {
1287        u8 inline_data[8];
1288        struct fw_packet *packet;
1289};
1290
1291/*
1292 * This function apppends a packet to the DMA queue for transmission.
1293 * Must always be called with the ochi->lock held to ensure proper
1294 * generation handling and locking around packet queue manipulation.
1295 */
1296static int at_context_queue_packet(struct context *ctx,
1297                                   struct fw_packet *packet)
1298{
1299        struct fw_ohci *ohci = ctx->ohci;
1300        dma_addr_t d_bus, uninitialized_var(payload_bus);
1301        struct driver_data *driver_data;
1302        struct descriptor *d, *last;
1303        __le32 *header;
1304        int z, tcode;
1305
1306        d = context_get_descriptors(ctx, 4, &d_bus);
1307        if (d == NULL) {
1308                packet->ack = RCODE_SEND_ERROR;
1309                return -1;
1310        }
1311
1312        d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1313        d[0].res_count = cpu_to_le16(packet->timestamp);
1314
1315        /*
1316         * The DMA format for asynchronous link packets is different
1317         * from the IEEE1394 layout, so shift the fields around
1318         * accordingly.
1319         */
1320
1321        tcode = (packet->header[0] >> 4) & 0x0f;
1322        header = (__le32 *) &d[1];
1323        switch (tcode) {
1324        case TCODE_WRITE_QUADLET_REQUEST:
1325        case TCODE_WRITE_BLOCK_REQUEST:
1326        case TCODE_WRITE_RESPONSE:
1327        case TCODE_READ_QUADLET_REQUEST:
1328        case TCODE_READ_BLOCK_REQUEST:
1329        case TCODE_READ_QUADLET_RESPONSE:
1330        case TCODE_READ_BLOCK_RESPONSE:
1331        case TCODE_LOCK_REQUEST:
1332        case TCODE_LOCK_RESPONSE:
1333                header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1334                                        (packet->speed << 16));
1335                header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1336                                        (packet->header[0] & 0xffff0000));
1337                header[2] = cpu_to_le32(packet->header[2]);
1338
1339                if (TCODE_IS_BLOCK_PACKET(tcode))
1340                        header[3] = cpu_to_le32(packet->header[3]);
1341                else
1342                        header[3] = (__force __le32) packet->header[3];
1343
1344                d[0].req_count = cpu_to_le16(packet->header_length);
1345                break;
1346
1347        case TCODE_LINK_INTERNAL:
1348                header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1349                                        (packet->speed << 16));
1350                header[1] = cpu_to_le32(packet->header[1]);
1351                header[2] = cpu_to_le32(packet->header[2]);
1352                d[0].req_count = cpu_to_le16(12);
1353
1354                if (is_ping_packet(&packet->header[1]))
1355                        d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1356                break;
1357
1358        case TCODE_STREAM_DATA:
1359                header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1360                                        (packet->speed << 16));
1361                header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1362                d[0].req_count = cpu_to_le16(8);
1363                break;
1364
1365        default:
1366                /* BUG(); */
1367                packet->ack = RCODE_SEND_ERROR;
1368                return -1;
1369        }
1370
1371        BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1372        driver_data = (struct driver_data *) &d[3];
1373        driver_data->packet = packet;
1374        packet->driver_data = driver_data;
1375
1376        if (packet->payload_length > 0) {
1377                if (packet->payload_length > sizeof(driver_data->inline_data)) {
1378                        payload_bus = dma_map_single(ohci->card.device,
1379                                                     packet->payload,
1380                                                     packet->payload_length,
1381                                                     DMA_TO_DEVICE);
1382                        if (dma_mapping_error(ohci->card.device, payload_bus)) {
1383                                packet->ack = RCODE_SEND_ERROR;
1384                                return -1;
1385                        }
1386                        packet->payload_bus     = payload_bus;
1387                        packet->payload_mapped  = true;
1388                } else {
1389                        memcpy(driver_data->inline_data, packet->payload,
1390                               packet->payload_length);
1391                        payload_bus = d_bus + 3 * sizeof(*d);
1392                }
1393
1394                d[2].req_count    = cpu_to_le16(packet->payload_length);
1395                d[2].data_address = cpu_to_le32(payload_bus);
1396                last = &d[2];
1397                z = 3;
1398        } else {
1399                last = &d[0];
1400                z = 2;
1401        }
1402
1403        last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1404                                     DESCRIPTOR_IRQ_ALWAYS |
1405                                     DESCRIPTOR_BRANCH_ALWAYS);
1406
1407        /* FIXME: Document how the locking works. */
1408        if (ohci->generation != packet->generation) {
1409                if (packet->payload_mapped)
1410                        dma_unmap_single(ohci->card.device, payload_bus,
1411                                         packet->payload_length, DMA_TO_DEVICE);
1412                packet->ack = RCODE_GENERATION;
1413                return -1;
1414        }
1415
1416        context_append(ctx, d, z, 4 - z);
1417
1418        if (ctx->running)
1419                reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1420        else
1421                context_run(ctx, 0);
1422
1423        return 0;
1424}
1425
1426static void at_context_flush(struct context *ctx)
1427{
1428        tasklet_disable(&ctx->tasklet);
1429
1430        ctx->flushing = true;
1431        context_tasklet((unsigned long)ctx);
1432        ctx->flushing = false;
1433
1434        tasklet_enable(&ctx->tasklet);
1435}
1436
1437static int handle_at_packet(struct context *context,
1438                            struct descriptor *d,
1439                            struct descriptor *last)
1440{
1441        struct driver_data *driver_data;
1442        struct fw_packet *packet;
1443        struct fw_ohci *ohci = context->ohci;
1444        int evt;
1445
1446        if (last->transfer_status == 0 && !context->flushing)
1447                /* This descriptor isn't done yet, stop iteration. */
1448                return 0;
1449
1450        driver_data = (struct driver_data *) &d[3];
1451        packet = driver_data->packet;
1452        if (packet == NULL)
1453                /* This packet was cancelled, just continue. */
1454                return 1;
1455
1456        if (packet->payload_mapped)
1457                dma_unmap_single(ohci->card.device, packet->payload_bus,
1458                                 packet->payload_length, DMA_TO_DEVICE);
1459
1460        evt = le16_to_cpu(last->transfer_status) & 0x1f;
1461        packet->timestamp = le16_to_cpu(last->res_count);
1462
1463        log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1464
1465        switch (evt) {
1466        case OHCI1394_evt_timeout:
1467                /* Async response transmit timed out. */
1468                packet->ack = RCODE_CANCELLED;
1469                break;
1470
1471        case OHCI1394_evt_flushed:
1472                /*
1473                 * The packet was flushed should give same error as
1474                 * when we try to use a stale generation count.
1475                 */
1476                packet->ack = RCODE_GENERATION;
1477                break;
1478
1479        case OHCI1394_evt_missing_ack:
1480                if (context->flushing)
1481                        packet->ack = RCODE_GENERATION;
1482                else {
1483                        /*
1484                         * Using a valid (current) generation count, but the
1485                         * node is not on the bus or not sending acks.
1486                         */
1487                        packet->ack = RCODE_NO_ACK;
1488                }
1489                break;
1490
1491        case ACK_COMPLETE + 0x10:
1492        case ACK_PENDING + 0x10:
1493        case ACK_BUSY_X + 0x10:
1494        case ACK_BUSY_A + 0x10:
1495        case ACK_BUSY_B + 0x10:
1496        case ACK_DATA_ERROR + 0x10:
1497        case ACK_TYPE_ERROR + 0x10:
1498                packet->ack = evt - 0x10;
1499                break;
1500
1501        case OHCI1394_evt_no_status:
1502                if (context->flushing) {
1503                        packet->ack = RCODE_GENERATION;
1504                        break;
1505                }
1506                /* fall through */
1507
1508        default:
1509                packet->ack = RCODE_SEND_ERROR;
1510                break;
1511        }
1512
1513        packet->callback(packet, &ohci->card, packet->ack);
1514
1515        return 1;
1516}
1517
1518#define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1519#define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1520#define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1521#define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1522#define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1523
1524static void handle_local_rom(struct fw_ohci *ohci,
1525                             struct fw_packet *packet, u32 csr)
1526{
1527        struct fw_packet response;
1528        int tcode, length, i;
1529
1530        tcode = HEADER_GET_TCODE(packet->header[0]);
1531        if (TCODE_IS_BLOCK_PACKET(tcode))
1532                length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1533        else
1534                length = 4;
1535
1536        i = csr - CSR_CONFIG_ROM;
1537        if (i + length > CONFIG_ROM_SIZE) {
1538                fw_fill_response(&response, packet->header,
1539                                 RCODE_ADDRESS_ERROR, NULL, 0);
1540        } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1541                fw_fill_response(&response, packet->header,
1542                                 RCODE_TYPE_ERROR, NULL, 0);
1543        } else {
1544                fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1545                                 (void *) ohci->config_rom + i, length);
1546        }
1547
1548        fw_core_handle_response(&ohci->card, &response);
1549}
1550
1551static void handle_local_lock(struct fw_ohci *ohci,
1552                              struct fw_packet *packet, u32 csr)
1553{
1554        struct fw_packet response;
1555        int tcode, length, ext_tcode, sel, try;
1556        __be32 *payload, lock_old;
1557        u32 lock_arg, lock_data;
1558
1559        tcode = HEADER_GET_TCODE(packet->header[0]);
1560        length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1561        payload = packet->payload;
1562        ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1563
1564        if (tcode == TCODE_LOCK_REQUEST &&
1565            ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1566                lock_arg = be32_to_cpu(payload[0]);
1567                lock_data = be32_to_cpu(payload[1]);
1568        } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1569                lock_arg = 0;
1570                lock_data = 0;
1571        } else {
1572                fw_fill_response(&response, packet->header,
1573                                 RCODE_TYPE_ERROR, NULL, 0);
1574                goto out;
1575        }
1576
1577        sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1578        reg_write(ohci, OHCI1394_CSRData, lock_data);
1579        reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1580        reg_write(ohci, OHCI1394_CSRControl, sel);
1581
1582        for (try = 0; try < 20; try++)
1583                if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1584                        lock_old = cpu_to_be32(reg_read(ohci,
1585                                                        OHCI1394_CSRData));
1586                        fw_fill_response(&response, packet->header,
1587                                         RCODE_COMPLETE,
1588                                         &lock_old, sizeof(lock_old));
1589                        goto out;
1590                }
1591
1592        ohci_err(ohci, "swap not done (CSR lock timeout)\n");
1593        fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1594
1595 out:
1596        fw_core_handle_response(&ohci->card, &response);
1597}
1598
1599static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1600{
1601        u64 offset, csr;
1602
1603        if (ctx == &ctx->ohci->at_request_ctx) {
1604                packet->ack = ACK_PENDING;
1605                packet->callback(packet, &ctx->ohci->card, packet->ack);
1606        }
1607
1608        offset =
1609                ((unsigned long long)
1610                 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1611                packet->header[2];
1612        csr = offset - CSR_REGISTER_BASE;
1613
1614        /* Handle config rom reads. */
1615        if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1616                handle_local_rom(ctx->ohci, packet, csr);
1617        else switch (csr) {
1618        case CSR_BUS_MANAGER_ID:
1619        case CSR_BANDWIDTH_AVAILABLE:
1620        case CSR_CHANNELS_AVAILABLE_HI:
1621        case CSR_CHANNELS_AVAILABLE_LO:
1622                handle_local_lock(ctx->ohci, packet, csr);
1623                break;
1624        default:
1625                if (ctx == &ctx->ohci->at_request_ctx)
1626                        fw_core_handle_request(&ctx->ohci->card, packet);
1627                else
1628                        fw_core_handle_response(&ctx->ohci->card, packet);
1629                break;
1630        }
1631
1632        if (ctx == &ctx->ohci->at_response_ctx) {
1633                packet->ack = ACK_COMPLETE;
1634                packet->callback(packet, &ctx->ohci->card, packet->ack);
1635        }
1636}
1637
1638static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1639{
1640        unsigned long flags;
1641        int ret;
1642
1643        spin_lock_irqsave(&ctx->ohci->lock, flags);
1644
1645        if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1646            ctx->ohci->generation == packet->generation) {
1647                spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1648                handle_local_request(ctx, packet);
1649                return;
1650        }
1651
1652        ret = at_context_queue_packet(ctx, packet);
1653        spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1654
1655        if (ret < 0)
1656                packet->callback(packet, &ctx->ohci->card, packet->ack);
1657
1658}
1659
1660static void detect_dead_context(struct fw_ohci *ohci,
1661                                const char *name, unsigned int regs)
1662{
1663        u32 ctl;
1664
1665        ctl = reg_read(ohci, CONTROL_SET(regs));
1666        if (ctl & CONTEXT_DEAD)
1667                ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
1668                        name, evts[ctl & 0x1f]);
1669}
1670
1671static void handle_dead_contexts(struct fw_ohci *ohci)
1672{
1673        unsigned int i;
1674        char name[8];
1675
1676        detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1677        detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1678        detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1679        detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1680        for (i = 0; i < 32; ++i) {
1681                if (!(ohci->it_context_support & (1 << i)))
1682                        continue;
1683                sprintf(name, "IT%u", i);
1684                detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1685        }
1686        for (i = 0; i < 32; ++i) {
1687                if (!(ohci->ir_context_support & (1 << i)))
1688                        continue;
1689                sprintf(name, "IR%u", i);
1690                detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1691        }
1692        /* TODO: maybe try to flush and restart the dead contexts */
1693}
1694
1695static u32 cycle_timer_ticks(u32 cycle_timer)
1696{
1697        u32 ticks;
1698
1699        ticks = cycle_timer & 0xfff;
1700        ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1701        ticks += (3072 * 8000) * (cycle_timer >> 25);
1702
1703        return ticks;
1704}
1705
1706/*
1707 * Some controllers exhibit one or more of the following bugs when updating the
1708 * iso cycle timer register:
1709 *  - When the lowest six bits are wrapping around to zero, a read that happens
1710 *    at the same time will return garbage in the lowest ten bits.
1711 *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1712 *    not incremented for about 60 ns.
1713 *  - Occasionally, the entire register reads zero.
1714 *
1715 * To catch these, we read the register three times and ensure that the
1716 * difference between each two consecutive reads is approximately the same, i.e.
1717 * less than twice the other.  Furthermore, any negative difference indicates an
1718 * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1719 * execute, so we have enough precision to compute the ratio of the differences.)
1720 */
1721static u32 get_cycle_time(struct fw_ohci *ohci)
1722{
1723        u32 c0, c1, c2;
1724        u32 t0, t1, t2;
1725        s32 diff01, diff12;
1726        int i;
1727
1728        c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1729
1730        if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1731                i = 0;
1732                c1 = c2;
1733                c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1734                do {
1735                        c0 = c1;
1736                        c1 = c2;
1737                        c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1738                        t0 = cycle_timer_ticks(c0);
1739                        t1 = cycle_timer_ticks(c1);
1740                        t2 = cycle_timer_ticks(c2);
1741                        diff01 = t1 - t0;
1742                        diff12 = t2 - t1;
1743                } while ((diff01 <= 0 || diff12 <= 0 ||
1744                          diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1745                         && i++ < 20);
1746        }
1747
1748        return c2;
1749}
1750
1751/*
1752 * This function has to be called at least every 64 seconds.  The bus_time
1753 * field stores not only the upper 25 bits of the BUS_TIME register but also
1754 * the most significant bit of the cycle timer in bit 6 so that we can detect
1755 * changes in this bit.
1756 */
1757static u32 update_bus_time(struct fw_ohci *ohci)
1758{
1759        u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1760
1761        if (unlikely(!ohci->bus_time_running)) {
1762                reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1763                ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) |
1764                                 (cycle_time_seconds & 0x40);
1765                ohci->bus_time_running = true;
1766        }
1767
1768        if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1769                ohci->bus_time += 0x40;
1770
1771        return ohci->bus_time | cycle_time_seconds;
1772}
1773
1774static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1775{
1776        int reg;
1777
1778        mutex_lock(&ohci->phy_reg_mutex);
1779        reg = write_phy_reg(ohci, 7, port_index);
1780        if (reg >= 0)
1781                reg = read_phy_reg(ohci, 8);
1782        mutex_unlock(&ohci->phy_reg_mutex);
1783        if (reg < 0)
1784                return reg;
1785
1786        switch (reg & 0x0f) {
1787        case 0x06:
1788                return 2;       /* is child node (connected to parent node) */
1789        case 0x0e:
1790                return 3;       /* is parent node (connected to child node) */
1791        }
1792        return 1;               /* not connected */
1793}
1794
1795static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1796        int self_id_count)
1797{
1798        int i;
1799        u32 entry;
1800
1801        for (i = 0; i < self_id_count; i++) {
1802                entry = ohci->self_id_buffer[i];
1803                if ((self_id & 0xff000000) == (entry & 0xff000000))
1804                        return -1;
1805                if ((self_id & 0xff000000) < (entry & 0xff000000))
1806                        return i;
1807        }
1808        return i;
1809}
1810
1811static int initiated_reset(struct fw_ohci *ohci)
1812{
1813        int reg;
1814        int ret = 0;
1815
1816        mutex_lock(&ohci->phy_reg_mutex);
1817        reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
1818        if (reg >= 0) {
1819                reg = read_phy_reg(ohci, 8);
1820                reg |= 0x40;
1821                reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
1822                if (reg >= 0) {
1823                        reg = read_phy_reg(ohci, 12); /* read register 12 */
1824                        if (reg >= 0) {
1825                                if ((reg & 0x08) == 0x08) {
1826                                        /* bit 3 indicates "initiated reset" */
1827                                        ret = 0x2;
1828                                }
1829                        }
1830                }
1831        }
1832        mutex_unlock(&ohci->phy_reg_mutex);
1833        return ret;
1834}
1835
1836/*
1837 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1838 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1839 * Construct the selfID from phy register contents.
1840 */
1841static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1842{
1843        int reg, i, pos, status;
1844        /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1845        u32 self_id = 0x8040c800;
1846
1847        reg = reg_read(ohci, OHCI1394_NodeID);
1848        if (!(reg & OHCI1394_NodeID_idValid)) {
1849                ohci_notice(ohci,
1850                            "node ID not valid, new bus reset in progress\n");
1851                return -EBUSY;
1852        }
1853        self_id |= ((reg & 0x3f) << 24); /* phy ID */
1854
1855        reg = ohci_read_phy_reg(&ohci->card, 4);
1856        if (reg < 0)
1857                return reg;
1858        self_id |= ((reg & 0x07) << 8); /* power class */
1859
1860        reg = ohci_read_phy_reg(&ohci->card, 1);
1861        if (reg < 0)
1862                return reg;
1863        self_id |= ((reg & 0x3f) << 16); /* gap count */
1864
1865        for (i = 0; i < 3; i++) {
1866                status = get_status_for_port(ohci, i);
1867                if (status < 0)
1868                        return status;
1869                self_id |= ((status & 0x3) << (6 - (i * 2)));
1870        }
1871
1872        self_id |= initiated_reset(ohci);
1873
1874        pos = get_self_id_pos(ohci, self_id, self_id_count);
1875        if (pos >= 0) {
1876                memmove(&(ohci->self_id_buffer[pos+1]),
1877                        &(ohci->self_id_buffer[pos]),
1878                        (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1879                ohci->self_id_buffer[pos] = self_id;
1880                self_id_count++;
1881        }
1882        return self_id_count;
1883}
1884
1885static void bus_reset_work(struct work_struct *work)
1886{
1887        struct fw_ohci *ohci =
1888                container_of(work, struct fw_ohci, bus_reset_work);
1889        int self_id_count, generation, new_generation, i, j;
1890        u32 reg;
1891        void *free_rom = NULL;
1892        dma_addr_t free_rom_bus = 0;
1893        bool is_new_root;
1894
1895        reg = reg_read(ohci, OHCI1394_NodeID);
1896        if (!(reg & OHCI1394_NodeID_idValid)) {
1897                ohci_notice(ohci,
1898                            "node ID not valid, new bus reset in progress\n");
1899                return;
1900        }
1901        if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1902                ohci_notice(ohci, "malconfigured bus\n");
1903                return;
1904        }
1905        ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1906                               OHCI1394_NodeID_nodeNumber);
1907
1908        is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1909        if (!(ohci->is_root && is_new_root))
1910                reg_write(ohci, OHCI1394_LinkControlSet,
1911                          OHCI1394_LinkControl_cycleMaster);
1912        ohci->is_root = is_new_root;
1913
1914        reg = reg_read(ohci, OHCI1394_SelfIDCount);
1915        if (reg & OHCI1394_SelfIDCount_selfIDError) {
1916                ohci_notice(ohci, "self ID receive error\n");
1917                return;
1918        }
1919        /*
1920         * The count in the SelfIDCount register is the number of
1921         * bytes in the self ID receive buffer.  Since we also receive
1922         * the inverted quadlets and a header quadlet, we shift one
1923         * bit extra to get the actual number of self IDs.
1924         */
1925        self_id_count = (reg >> 3) & 0xff;
1926
1927        if (self_id_count > 252) {
1928                ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
1929                return;
1930        }
1931
1932        generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1933        rmb();
1934
1935        for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1936                u32 id  = cond_le32_to_cpu(ohci->self_id_cpu[i]);
1937                u32 id2 = cond_le32_to_cpu(ohci->self_id_cpu[i + 1]);
1938
1939                if (id != ~id2) {
1940                        /*
1941                         * If the invalid data looks like a cycle start packet,
1942                         * it's likely to be the result of the cycle master
1943                         * having a wrong gap count.  In this case, the self IDs
1944                         * so far are valid and should be processed so that the
1945                         * bus manager can then correct the gap count.
1946                         */
1947                        if (id == 0xffff008f) {
1948                                ohci_notice(ohci, "ignoring spurious self IDs\n");
1949                                self_id_count = j;
1950                                break;
1951                        }
1952
1953                        ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
1954                                    j, self_id_count, id, id2);
1955                        return;
1956                }
1957                ohci->self_id_buffer[j] = id;
1958        }
1959
1960        if (ohci->quirks & QUIRK_TI_SLLZ059) {
1961                self_id_count = find_and_insert_self_id(ohci, self_id_count);
1962                if (self_id_count < 0) {
1963                        ohci_notice(ohci,
1964                                    "could not construct local self ID\n");
1965                        return;
1966                }
1967        }
1968
1969        if (self_id_count == 0) {
1970                ohci_notice(ohci, "no self IDs\n");
1971                return;
1972        }
1973        rmb();
1974
1975        /*
1976         * Check the consistency of the self IDs we just read.  The
1977         * problem we face is that a new bus reset can start while we
1978         * read out the self IDs from the DMA buffer. If this happens,
1979         * the DMA buffer will be overwritten with new self IDs and we
1980         * will read out inconsistent data.  The OHCI specification
1981         * (section 11.2) recommends a technique similar to
1982         * linux/seqlock.h, where we remember the generation of the
1983         * self IDs in the buffer before reading them out and compare
1984         * it to the current generation after reading them out.  If
1985         * the two generations match we know we have a consistent set
1986         * of self IDs.
1987         */
1988
1989        new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1990        if (new_generation != generation) {
1991                ohci_notice(ohci, "new bus reset, discarding self ids\n");
1992                return;
1993        }
1994
1995        /* FIXME: Document how the locking works. */
1996        spin_lock_irq(&ohci->lock);
1997
1998        ohci->generation = -1; /* prevent AT packet queueing */
1999        context_stop(&ohci->at_request_ctx);
2000        context_stop(&ohci->at_response_ctx);
2001
2002        spin_unlock_irq(&ohci->lock);
2003
2004        /*
2005         * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
2006         * packets in the AT queues and software needs to drain them.
2007         * Some OHCI 1.1 controllers (JMicron) apparently require this too.
2008         */
2009        at_context_flush(&ohci->at_request_ctx);
2010        at_context_flush(&ohci->at_response_ctx);
2011
2012        spin_lock_irq(&ohci->lock);
2013
2014        ohci->generation = generation;
2015        reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2016
2017        if (ohci->quirks & QUIRK_RESET_PACKET)
2018                ohci->request_generation = generation;
2019
2020        /*
2021         * This next bit is unrelated to the AT context stuff but we
2022         * have to do it under the spinlock also.  If a new config rom
2023         * was set up before this reset, the old one is now no longer
2024         * in use and we can free it. Update the config rom pointers
2025         * to point to the current config rom and clear the
2026         * next_config_rom pointer so a new update can take place.
2027         */
2028
2029        if (ohci->next_config_rom != NULL) {
2030                if (ohci->next_config_rom != ohci->config_rom) {
2031                        free_rom      = ohci->config_rom;
2032                        free_rom_bus  = ohci->config_rom_bus;
2033                }
2034                ohci->config_rom      = ohci->next_config_rom;
2035                ohci->config_rom_bus  = ohci->next_config_rom_bus;
2036                ohci->next_config_rom = NULL;
2037
2038                /*
2039                 * Restore config_rom image and manually update
2040                 * config_rom registers.  Writing the header quadlet
2041                 * will indicate that the config rom is ready, so we
2042                 * do that last.
2043                 */
2044                reg_write(ohci, OHCI1394_BusOptions,
2045                          be32_to_cpu(ohci->config_rom[2]));
2046                ohci->config_rom[0] = ohci->next_header;
2047                reg_write(ohci, OHCI1394_ConfigROMhdr,
2048                          be32_to_cpu(ohci->next_header));
2049        }
2050
2051#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2052        reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2053        reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2054#endif
2055
2056        spin_unlock_irq(&ohci->lock);
2057
2058        if (free_rom)
2059                dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2060                                  free_rom, free_rom_bus);
2061
2062        log_selfids(ohci, generation, self_id_count);
2063
2064        fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
2065                                 self_id_count, ohci->self_id_buffer,
2066                                 ohci->csr_state_setclear_abdicate);
2067        ohci->csr_state_setclear_abdicate = false;
2068}
2069
2070static irqreturn_t irq_handler(int irq, void *data)
2071{
2072        struct fw_ohci *ohci = data;
2073        u32 event, iso_event;
2074        int i;
2075
2076        event = reg_read(ohci, OHCI1394_IntEventClear);
2077
2078        if (!event || !~event)
2079                return IRQ_NONE;
2080
2081        /*
2082         * busReset and postedWriteErr must not be cleared yet
2083         * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2084         */
2085        reg_write(ohci, OHCI1394_IntEventClear,
2086                  event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2087        log_irqs(ohci, event);
2088
2089        if (event & OHCI1394_selfIDComplete)
2090                queue_work(fw_workqueue, &ohci->bus_reset_work);
2091
2092        if (event & OHCI1394_RQPkt)
2093                tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2094
2095        if (event & OHCI1394_RSPkt)
2096                tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2097
2098        if (event & OHCI1394_reqTxComplete)
2099                tasklet_schedule(&ohci->at_request_ctx.tasklet);
2100
2101        if (event & OHCI1394_respTxComplete)
2102                tasklet_schedule(&ohci->at_response_ctx.tasklet);
2103
2104        if (event & OHCI1394_isochRx) {
2105                iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2106                reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2107
2108                while (iso_event) {
2109                        i = ffs(iso_event) - 1;
2110                        tasklet_schedule(
2111                                &ohci->ir_context_list[i].context.tasklet);
2112                        iso_event &= ~(1 << i);
2113                }
2114        }
2115
2116        if (event & OHCI1394_isochTx) {
2117                iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2118                reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2119
2120                while (iso_event) {
2121                        i = ffs(iso_event) - 1;
2122                        tasklet_schedule(
2123                                &ohci->it_context_list[i].context.tasklet);
2124                        iso_event &= ~(1 << i);
2125                }
2126        }
2127
2128        if (unlikely(event & OHCI1394_regAccessFail))
2129                ohci_err(ohci, "register access failure\n");
2130
2131        if (unlikely(event & OHCI1394_postedWriteErr)) {
2132                reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2133                reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2134                reg_write(ohci, OHCI1394_IntEventClear,
2135                          OHCI1394_postedWriteErr);
2136                if (printk_ratelimit())
2137                        ohci_err(ohci, "PCI posted write error\n");
2138        }
2139
2140        if (unlikely(event & OHCI1394_cycleTooLong)) {
2141                if (printk_ratelimit())
2142                        ohci_notice(ohci, "isochronous cycle too long\n");
2143                reg_write(ohci, OHCI1394_LinkControlSet,
2144                          OHCI1394_LinkControl_cycleMaster);
2145        }
2146
2147        if (unlikely(event & OHCI1394_cycleInconsistent)) {
2148                /*
2149                 * We need to clear this event bit in order to make
2150                 * cycleMatch isochronous I/O work.  In theory we should
2151                 * stop active cycleMatch iso contexts now and restart
2152                 * them at least two cycles later.  (FIXME?)
2153                 */
2154                if (printk_ratelimit())
2155                        ohci_notice(ohci, "isochronous cycle inconsistent\n");
2156        }
2157
2158        if (unlikely(event & OHCI1394_unrecoverableError))
2159                handle_dead_contexts(ohci);
2160
2161        if (event & OHCI1394_cycle64Seconds) {
2162                spin_lock(&ohci->lock);
2163                update_bus_time(ohci);
2164                spin_unlock(&ohci->lock);
2165        } else
2166                flush_writes(ohci);
2167
2168        return IRQ_HANDLED;
2169}
2170
2171static int software_reset(struct fw_ohci *ohci)
2172{
2173        u32 val;
2174        int i;
2175
2176        reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2177        for (i = 0; i < 500; i++) {
2178                val = reg_read(ohci, OHCI1394_HCControlSet);
2179                if (!~val)
2180                        return -ENODEV; /* Card was ejected. */
2181
2182                if (!(val & OHCI1394_HCControl_softReset))
2183                        return 0;
2184
2185                msleep(1);
2186        }
2187
2188        return -EBUSY;
2189}
2190
2191static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2192{
2193        size_t size = length * 4;
2194
2195        memcpy(dest, src, size);
2196        if (size < CONFIG_ROM_SIZE)
2197                memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2198}
2199
2200static int configure_1394a_enhancements(struct fw_ohci *ohci)
2201{
2202        bool enable_1394a;
2203        int ret, clear, set, offset;
2204
2205        /* Check if the driver should configure link and PHY. */
2206        if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2207              OHCI1394_HCControl_programPhyEnable))
2208                return 0;
2209
2210        /* Paranoia: check whether the PHY supports 1394a, too. */
2211        enable_1394a = false;
2212        ret = read_phy_reg(ohci, 2);
2213        if (ret < 0)
2214                return ret;
2215        if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2216                ret = read_paged_phy_reg(ohci, 1, 8);
2217                if (ret < 0)
2218                        return ret;
2219                if (ret >= 1)
2220                        enable_1394a = true;
2221        }
2222
2223        if (ohci->quirks & QUIRK_NO_1394A)
2224                enable_1394a = false;
2225
2226        /* Configure PHY and link consistently. */
2227        if (enable_1394a) {
2228                clear = 0;
2229                set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2230        } else {
2231                clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2232                set = 0;
2233        }
2234        ret = update_phy_reg(ohci, 5, clear, set);
2235        if (ret < 0)
2236                return ret;
2237
2238        if (enable_1394a)
2239                offset = OHCI1394_HCControlSet;
2240        else
2241                offset = OHCI1394_HCControlClear;
2242        reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2243
2244        /* Clean up: configuration has been taken care of. */
2245        reg_write(ohci, OHCI1394_HCControlClear,
2246                  OHCI1394_HCControl_programPhyEnable);
2247
2248        return 0;
2249}
2250
2251static int probe_tsb41ba3d(struct fw_ohci *ohci)
2252{
2253        /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2254        static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2255        int reg, i;
2256
2257        reg = read_phy_reg(ohci, 2);
2258        if (reg < 0)
2259                return reg;
2260        if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2261                return 0;
2262
2263        for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2264                reg = read_paged_phy_reg(ohci, 1, i + 10);
2265                if (reg < 0)
2266                        return reg;
2267                if (reg != id[i])
2268                        return 0;
2269        }
2270        return 1;
2271}
2272
2273static int ohci_enable(struct fw_card *card,
2274                       const __be32 *config_rom, size_t length)
2275{
2276        struct fw_ohci *ohci = fw_ohci(card);
2277        u32 lps, version, irqs;
2278        int i, ret;
2279
2280        if (software_reset(ohci)) {
2281                ohci_err(ohci, "failed to reset ohci card\n");
2282                return -EBUSY;
2283        }
2284
2285        /*
2286         * Now enable LPS, which we need in order to start accessing
2287         * most of the registers.  In fact, on some cards (ALI M5251),
2288         * accessing registers in the SClk domain without LPS enabled
2289         * will lock up the machine.  Wait 50msec to make sure we have
2290         * full link enabled.  However, with some cards (well, at least
2291         * a JMicron PCIe card), we have to try again sometimes.
2292         *
2293         * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
2294         * cannot actually use the phy at that time.  These need tens of
2295         * millisecods pause between LPS write and first phy access too.
2296         *
2297         * But do not wait for 50msec on Agere/LSI cards.  Their phy
2298         * arbitration state machine may time out during such a long wait.
2299         */
2300
2301        reg_write(ohci, OHCI1394_HCControlSet,
2302                  OHCI1394_HCControl_LPS |
2303                  OHCI1394_HCControl_postedWriteEnable);
2304        flush_writes(ohci);
2305
2306        if (!(ohci->quirks & QUIRK_PHY_LCTRL_TIMEOUT))
2307                msleep(50);
2308
2309        for (lps = 0, i = 0; !lps && i < 150; i++) {
2310                msleep(1);
2311                lps = reg_read(ohci, OHCI1394_HCControlSet) &
2312                      OHCI1394_HCControl_LPS;
2313        }
2314
2315        if (!lps) {
2316                ohci_err(ohci, "failed to set Link Power Status\n");
2317                return -EIO;
2318        }
2319
2320        if (ohci->quirks & QUIRK_TI_SLLZ059) {
2321                ret = probe_tsb41ba3d(ohci);
2322                if (ret < 0)
2323                        return ret;
2324                if (ret)
2325                        ohci_notice(ohci, "local TSB41BA3D phy\n");
2326                else
2327                        ohci->quirks &= ~QUIRK_TI_SLLZ059;
2328        }
2329
2330        reg_write(ohci, OHCI1394_HCControlClear,
2331                  OHCI1394_HCControl_noByteSwapData);
2332
2333        reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2334        reg_write(ohci, OHCI1394_LinkControlSet,
2335                  OHCI1394_LinkControl_cycleTimerEnable |
2336                  OHCI1394_LinkControl_cycleMaster);
2337
2338        reg_write(ohci, OHCI1394_ATRetries,
2339                  OHCI1394_MAX_AT_REQ_RETRIES |
2340                  (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2341                  (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2342                  (200 << 16));
2343
2344        ohci->bus_time_running = false;
2345
2346        for (i = 0; i < 32; i++)
2347                if (ohci->ir_context_support & (1 << i))
2348                        reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2349                                  IR_CONTEXT_MULTI_CHANNEL_MODE);
2350
2351        version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2352        if (version >= OHCI_VERSION_1_1) {
2353                reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2354                          0xfffffffe);
2355                card->broadcast_channel_auto_allocated = true;
2356        }
2357
2358        /* Get implemented bits of the priority arbitration request counter. */
2359        reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2360        ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2361        reg_write(ohci, OHCI1394_FairnessControl, 0);
2362        card->priority_budget_implemented = ohci->pri_req_max != 0;
2363
2364        reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2365        reg_write(ohci, OHCI1394_IntEventClear, ~0);
2366        reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2367
2368        ret = configure_1394a_enhancements(ohci);
2369        if (ret < 0)
2370                return ret;
2371
2372        /* Activate link_on bit and contender bit in our self ID packets.*/
2373        ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2374        if (ret < 0)
2375                return ret;
2376
2377        /*
2378         * When the link is not yet enabled, the atomic config rom
2379         * update mechanism described below in ohci_set_config_rom()
2380         * is not active.  We have to update ConfigRomHeader and
2381         * BusOptions manually, and the write to ConfigROMmap takes
2382         * effect immediately.  We tie this to the enabling of the
2383         * link, so we have a valid config rom before enabling - the
2384         * OHCI requires that ConfigROMhdr and BusOptions have valid
2385         * values before enabling.
2386         *
2387         * However, when the ConfigROMmap is written, some controllers
2388         * always read back quadlets 0 and 2 from the config rom to
2389         * the ConfigRomHeader and BusOptions registers on bus reset.
2390         * They shouldn't do that in this initial case where the link
2391         * isn't enabled.  This means we have to use the same
2392         * workaround here, setting the bus header to 0 and then write
2393         * the right values in the bus reset tasklet.
2394         */
2395
2396        if (config_rom) {
2397                ohci->next_config_rom =
2398                        dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2399                                           &ohci->next_config_rom_bus,
2400                                           GFP_KERNEL);
2401                if (ohci->next_config_rom == NULL)
2402                        return -ENOMEM;
2403
2404                copy_config_rom(ohci->next_config_rom, config_rom, length);
2405        } else {
2406                /*
2407                 * In the suspend case, config_rom is NULL, which
2408                 * means that we just reuse the old config rom.
2409                 */
2410                ohci->next_config_rom = ohci->config_rom;
2411                ohci->next_config_rom_bus = ohci->config_rom_bus;
2412        }
2413
2414        ohci->next_header = ohci->next_config_rom[0];
2415        ohci->next_config_rom[0] = 0;
2416        reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2417        reg_write(ohci, OHCI1394_BusOptions,
2418                  be32_to_cpu(ohci->next_config_rom[2]));
2419        reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2420
2421        reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2422
2423        irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2424                OHCI1394_RQPkt | OHCI1394_RSPkt |
2425                OHCI1394_isochTx | OHCI1394_isochRx |
2426                OHCI1394_postedWriteErr |
2427                OHCI1394_selfIDComplete |
2428                OHCI1394_regAccessFail |
2429                OHCI1394_cycleInconsistent |
2430                OHCI1394_unrecoverableError |
2431                OHCI1394_cycleTooLong |
2432                OHCI1394_masterIntEnable;
2433        if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2434                irqs |= OHCI1394_busReset;
2435        reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2436
2437        reg_write(ohci, OHCI1394_HCControlSet,
2438                  OHCI1394_HCControl_linkEnable |
2439                  OHCI1394_HCControl_BIBimageValid);
2440
2441        reg_write(ohci, OHCI1394_LinkControlSet,
2442                  OHCI1394_LinkControl_rcvSelfID |
2443                  OHCI1394_LinkControl_rcvPhyPkt);
2444
2445        ar_context_run(&ohci->ar_request_ctx);
2446        ar_context_run(&ohci->ar_response_ctx);
2447
2448        flush_writes(ohci);
2449
2450        /* We are ready to go, reset bus to finish initialization. */
2451        fw_schedule_bus_reset(&ohci->card, false, true);
2452
2453        return 0;
2454}
2455
2456static int ohci_set_config_rom(struct fw_card *card,
2457                               const __be32 *config_rom, size_t length)
2458{
2459        struct fw_ohci *ohci;
2460        __be32 *next_config_rom;
2461        dma_addr_t uninitialized_var(next_config_rom_bus);
2462
2463        ohci = fw_ohci(card);
2464
2465        /*
2466         * When the OHCI controller is enabled, the config rom update
2467         * mechanism is a bit tricky, but easy enough to use.  See
2468         * section 5.5.6 in the OHCI specification.
2469         *
2470         * The OHCI controller caches the new config rom address in a
2471         * shadow register (ConfigROMmapNext) and needs a bus reset
2472         * for the changes to take place.  When the bus reset is
2473         * detected, the controller loads the new values for the
2474         * ConfigRomHeader and BusOptions registers from the specified
2475         * config rom and loads ConfigROMmap from the ConfigROMmapNext
2476         * shadow register. All automatically and atomically.
2477         *
2478         * Now, there's a twist to this story.  The automatic load of
2479         * ConfigRomHeader and BusOptions doesn't honor the
2480         * noByteSwapData bit, so with a be32 config rom, the
2481         * controller will load be32 values in to these registers
2482         * during the atomic update, even on litte endian
2483         * architectures.  The workaround we use is to put a 0 in the
2484         * header quadlet; 0 is endian agnostic and means that the
2485         * config rom isn't ready yet.  In the bus reset tasklet we
2486         * then set up the real values for the two registers.
2487         *
2488         * We use ohci->lock to avoid racing with the code that sets
2489         * ohci->next_config_rom to NULL (see bus_reset_work).
2490         */
2491
2492        next_config_rom =
2493                dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2494                                   &next_config_rom_bus, GFP_KERNEL);
2495        if (next_config_rom == NULL)
2496                return -ENOMEM;
2497
2498        spin_lock_irq(&ohci->lock);
2499
2500        /*
2501         * If there is not an already pending config_rom update,
2502         * push our new allocation into the ohci->next_config_rom
2503         * and then mark the local variable as null so that we
2504         * won't deallocate the new buffer.
2505         *
2506         * OTOH, if there is a pending config_rom update, just
2507         * use that buffer with the new config_rom data, and
2508         * let this routine free the unused DMA allocation.
2509         */
2510
2511        if (ohci->next_config_rom == NULL) {
2512                ohci->next_config_rom = next_config_rom;
2513                ohci->next_config_rom_bus = next_config_rom_bus;
2514                next_config_rom = NULL;
2515        }
2516
2517        copy_config_rom(ohci->next_config_rom, config_rom, length);
2518
2519        ohci->next_header = config_rom[0];
2520        ohci->next_config_rom[0] = 0;
2521
2522        reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2523
2524        spin_unlock_irq(&ohci->lock);
2525
2526        /* If we didn't use the DMA allocation, delete it. */
2527        if (next_config_rom != NULL)
2528                dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2529                                  next_config_rom, next_config_rom_bus);
2530
2531        /*
2532         * Now initiate a bus reset to have the changes take
2533         * effect. We clean up the old config rom memory and DMA
2534         * mappings in the bus reset tasklet, since the OHCI
2535         * controller could need to access it before the bus reset
2536         * takes effect.
2537         */
2538
2539        fw_schedule_bus_reset(&ohci->card, true, true);
2540
2541        return 0;
2542}
2543
2544static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2545{
2546        struct fw_ohci *ohci = fw_ohci(card);
2547
2548        at_context_transmit(&ohci->at_request_ctx, packet);
2549}
2550
2551static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2552{
2553        struct fw_ohci *ohci = fw_ohci(card);
2554
2555        at_context_transmit(&ohci->at_response_ctx, packet);
2556}
2557
2558static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2559{
2560        struct fw_ohci *ohci = fw_ohci(card);
2561        struct context *ctx = &ohci->at_request_ctx;
2562        struct driver_data *driver_data = packet->driver_data;
2563        int ret = -ENOENT;
2564
2565        tasklet_disable(&ctx->tasklet);
2566
2567        if (packet->ack != 0)
2568                goto out;
2569
2570        if (packet->payload_mapped)
2571                dma_unmap_single(ohci->card.device, packet->payload_bus,
2572                                 packet->payload_length, DMA_TO_DEVICE);
2573
2574        log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2575        driver_data->packet = NULL;
2576        packet->ack = RCODE_CANCELLED;
2577        packet->callback(packet, &ohci->card, packet->ack);
2578        ret = 0;
2579 out:
2580        tasklet_enable(&ctx->tasklet);
2581
2582        return ret;
2583}
2584
2585static int ohci_enable_phys_dma(struct fw_card *card,
2586                                int node_id, int generation)
2587{
2588#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2589        return 0;
2590#else
2591        struct fw_ohci *ohci = fw_ohci(card);
2592        unsigned long flags;
2593        int n, ret = 0;
2594
2595        /*
2596         * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2597         * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2598         */
2599
2600        spin_lock_irqsave(&ohci->lock, flags);
2601
2602        if (ohci->generation != generation) {
2603                ret = -ESTALE;
2604                goto out;
2605        }
2606
2607        /*
2608         * Note, if the node ID contains a non-local bus ID, physical DMA is
2609         * enabled for _all_ nodes on remote buses.
2610         */
2611
2612        n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2613        if (n < 32)
2614                reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2615        else
2616                reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2617
2618        flush_writes(ohci);
2619 out:
2620        spin_unlock_irqrestore(&ohci->lock, flags);
2621
2622        return ret;
2623#endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2624}
2625
2626static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2627{
2628        struct fw_ohci *ohci = fw_ohci(card);
2629        unsigned long flags;
2630        u32 value;
2631
2632        switch (csr_offset) {
2633        case CSR_STATE_CLEAR:
2634        case CSR_STATE_SET:
2635                if (ohci->is_root &&
2636                    (reg_read(ohci, OHCI1394_LinkControlSet) &
2637                     OHCI1394_LinkControl_cycleMaster))
2638                        value = CSR_STATE_BIT_CMSTR;
2639                else
2640                        value = 0;
2641                if (ohci->csr_state_setclear_abdicate)
2642                        value |= CSR_STATE_BIT_ABDICATE;
2643
2644                return value;
2645
2646        case CSR_NODE_IDS:
2647                return reg_read(ohci, OHCI1394_NodeID) << 16;
2648
2649        case CSR_CYCLE_TIME:
2650                return get_cycle_time(ohci);
2651
2652        case CSR_BUS_TIME:
2653                /*
2654                 * We might be called just after the cycle timer has wrapped
2655                 * around but just before the cycle64Seconds handler, so we
2656                 * better check here, too, if the bus time needs to be updated.
2657                 */
2658                spin_lock_irqsave(&ohci->lock, flags);
2659                value = update_bus_time(ohci);
2660                spin_unlock_irqrestore(&ohci->lock, flags);
2661                return value;
2662
2663        case CSR_BUSY_TIMEOUT:
2664                value = reg_read(ohci, OHCI1394_ATRetries);
2665                return (value >> 4) & 0x0ffff00f;
2666
2667        case CSR_PRIORITY_BUDGET:
2668                return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2669                        (ohci->pri_req_max << 8);
2670
2671        default:
2672                WARN_ON(1);
2673                return 0;
2674        }
2675}
2676
2677static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2678{
2679        struct fw_ohci *ohci = fw_ohci(card);
2680        unsigned long flags;
2681
2682        switch (csr_offset) {
2683        case CSR_STATE_CLEAR:
2684                if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2685                        reg_write(ohci, OHCI1394_LinkControlClear,
2686                                  OHCI1394_LinkControl_cycleMaster);
2687                        flush_writes(ohci);
2688                }
2689                if (value & CSR_STATE_BIT_ABDICATE)
2690                        ohci->csr_state_setclear_abdicate = false;
2691                break;
2692
2693        case CSR_STATE_SET:
2694                if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2695                        reg_write(ohci, OHCI1394_LinkControlSet,
2696                                  OHCI1394_LinkControl_cycleMaster);
2697                        flush_writes(ohci);
2698                }
2699                if (value & CSR_STATE_BIT_ABDICATE)
2700                        ohci->csr_state_setclear_abdicate = true;
2701                break;
2702
2703        case CSR_NODE_IDS:
2704                reg_write(ohci, OHCI1394_NodeID, value >> 16);
2705                flush_writes(ohci);
2706                break;
2707
2708        case CSR_CYCLE_TIME:
2709                reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2710                reg_write(ohci, OHCI1394_IntEventSet,
2711                          OHCI1394_cycleInconsistent);
2712                flush_writes(ohci);
2713                break;
2714
2715        case CSR_BUS_TIME:
2716                spin_lock_irqsave(&ohci->lock, flags);
2717                ohci->bus_time = (update_bus_time(ohci) & 0x40) |
2718                                 (value & ~0x7f);
2719                spin_unlock_irqrestore(&ohci->lock, flags);
2720                break;
2721
2722        case CSR_BUSY_TIMEOUT:
2723                value = (value & 0xf) | ((value & 0xf) << 4) |
2724                        ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2725                reg_write(ohci, OHCI1394_ATRetries, value);
2726                flush_writes(ohci);
2727                break;
2728
2729        case CSR_PRIORITY_BUDGET:
2730                reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2731                flush_writes(ohci);
2732                break;
2733
2734        default:
2735                WARN_ON(1);
2736                break;
2737        }
2738}
2739
2740static void flush_iso_completions(struct iso_context *ctx)
2741{
2742        ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2743                              ctx->header_length, ctx->header,
2744                              ctx->base.callback_data);
2745        ctx->header_length = 0;
2746}
2747
2748static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2749{
2750        u32 *ctx_hdr;
2751
2752        if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) {
2753                if (ctx->base.drop_overflow_headers)
2754                        return;
2755                flush_iso_completions(ctx);
2756        }
2757
2758        ctx_hdr = ctx->header + ctx->header_length;
2759        ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2760
2761        /*
2762         * The two iso header quadlets are byteswapped to little
2763         * endian by the controller, but we want to present them
2764         * as big endian for consistency with the bus endianness.
2765         */
2766        if (ctx->base.header_size > 0)
2767                ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2768        if (ctx->base.header_size > 4)
2769                ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2770        if (ctx->base.header_size > 8)
2771                memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2772        ctx->header_length += ctx->base.header_size;
2773}
2774
2775static int handle_ir_packet_per_buffer(struct context *context,
2776                                       struct descriptor *d,
2777                                       struct descriptor *last)
2778{
2779        struct iso_context *ctx =
2780                container_of(context, struct iso_context, context);
2781        struct descriptor *pd;
2782        u32 buffer_dma;
2783
2784        for (pd = d; pd <= last; pd++)
2785                if (pd->transfer_status)
2786                        break;
2787        if (pd > last)
2788                /* Descriptor(s) not done yet, stop iteration */
2789                return 0;
2790
2791        while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2792                d++;
2793                buffer_dma = le32_to_cpu(d->data_address);
2794                dma_sync_single_range_for_cpu(context->ohci->card.device,
2795                                              buffer_dma & PAGE_MASK,
2796                                              buffer_dma & ~PAGE_MASK,
2797                                              le16_to_cpu(d->req_count),
2798                                              DMA_FROM_DEVICE);
2799        }
2800
2801        copy_iso_headers(ctx, (u32 *) (last + 1));
2802
2803        if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2804                flush_iso_completions(ctx);
2805
2806        return 1;
2807}
2808
2809/* d == last because each descriptor block is only a single descriptor. */
2810static int handle_ir_buffer_fill(struct context *context,
2811                                 struct descriptor *d,
2812                                 struct descriptor *last)
2813{
2814        struct iso_context *ctx =
2815                container_of(context, struct iso_context, context);
2816        unsigned int req_count, res_count, completed;
2817        u32 buffer_dma;
2818
2819        req_count = le16_to_cpu(last->req_count);
2820        res_count = le16_to_cpu(ACCESS_ONCE(last->res_count));
2821        completed = req_count - res_count;
2822        buffer_dma = le32_to_cpu(last->data_address);
2823
2824        if (completed > 0) {
2825                ctx->mc_buffer_bus = buffer_dma;
2826                ctx->mc_completed = completed;
2827        }
2828
2829        if (res_count != 0)
2830                /* Descriptor(s) not done yet, stop iteration */
2831                return 0;
2832
2833        dma_sync_single_range_for_cpu(context->ohci->card.device,
2834                                      buffer_dma & PAGE_MASK,
2835                                      buffer_dma & ~PAGE_MASK,
2836                                      completed, DMA_FROM_DEVICE);
2837
2838        if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
2839                ctx->base.callback.mc(&ctx->base,
2840                                      buffer_dma + completed,
2841                                      ctx->base.callback_data);
2842                ctx->mc_completed = 0;
2843        }
2844
2845        return 1;
2846}
2847
2848static void flush_ir_buffer_fill(struct iso_context *ctx)
2849{
2850        dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2851                                      ctx->mc_buffer_bus & PAGE_MASK,
2852                                      ctx->mc_buffer_bus & ~PAGE_MASK,
2853                                      ctx->mc_completed, DMA_FROM_DEVICE);
2854
2855        ctx->base.callback.mc(&ctx->base,
2856                              ctx->mc_buffer_bus + ctx->mc_completed,
2857                              ctx->base.callback_data);
2858        ctx->mc_completed = 0;
2859}
2860
2861static inline void sync_it_packet_for_cpu(struct context *context,
2862                                          struct descriptor *pd)
2863{
2864        __le16 control;
2865        u32 buffer_dma;
2866
2867        /* only packets beginning with OUTPUT_MORE* have data buffers */
2868        if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2869                return;
2870
2871        /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2872        pd += 2;
2873
2874        /*
2875         * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2876         * data buffer is in the context program's coherent page and must not
2877         * be synced.
2878         */
2879        if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2880            (context->current_bus          & PAGE_MASK)) {
2881                if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2882                        return;
2883                pd++;
2884        }
2885
2886        do {
2887                buffer_dma = le32_to_cpu(pd->data_address);
2888                dma_sync_single_range_for_cpu(context->ohci->card.device,
2889                                              buffer_dma & PAGE_MASK,
2890                                              buffer_dma & ~PAGE_MASK,
2891                                              le16_to_cpu(pd->req_count),
2892                                              DMA_TO_DEVICE);
2893                control = pd->control;
2894                pd++;
2895        } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2896}
2897
2898static int handle_it_packet(struct context *context,
2899                            struct descriptor *d,
2900                            struct descriptor *last)
2901{
2902        struct iso_context *ctx =
2903                container_of(context, struct iso_context, context);
2904        struct descriptor *pd;
2905        __be32 *ctx_hdr;
2906
2907        for (pd = d; pd <= last; pd++)
2908                if (pd->transfer_status)
2909                        break;
2910        if (pd > last)
2911                /* Descriptor(s) not done yet, stop iteration */
2912                return 0;
2913
2914        sync_it_packet_for_cpu(context, d);
2915
2916        if (ctx->header_length + 4 > PAGE_SIZE) {
2917                if (ctx->base.drop_overflow_headers)
2918                        return 1;
2919                flush_iso_completions(ctx);
2920        }
2921
2922        ctx_hdr = ctx->header + ctx->header_length;
2923        ctx->last_timestamp = le16_to_cpu(last->res_count);
2924        /* Present this value as big-endian to match the receive code */
2925        *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2926                               le16_to_cpu(pd->res_count));
2927        ctx->header_length += 4;
2928
2929        if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2930                flush_iso_completions(ctx);
2931
2932        return 1;
2933}
2934
2935static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2936{
2937        u32 hi = channels >> 32, lo = channels;
2938
2939        reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2940        reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2941        reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2942        reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2943        mmiowb();
2944        ohci->mc_channels = channels;
2945}
2946
2947static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2948                                int type, int channel, size_t header_size)
2949{
2950        struct fw_ohci *ohci = fw_ohci(card);
2951        struct iso_context *uninitialized_var(ctx);
2952        descriptor_callback_t uninitialized_var(callback);
2953        u64 *uninitialized_var(channels);
2954        u32 *uninitialized_var(mask), uninitialized_var(regs);
2955        int index, ret = -EBUSY;
2956
2957        spin_lock_irq(&ohci->lock);
2958
2959        switch (type) {
2960        case FW_ISO_CONTEXT_TRANSMIT:
2961                mask     = &ohci->it_context_mask;
2962                callback = handle_it_packet;
2963                index    = ffs(*mask) - 1;
2964                if (index >= 0) {
2965                        *mask &= ~(1 << index);
2966                        regs = OHCI1394_IsoXmitContextBase(index);
2967                        ctx  = &ohci->it_context_list[index];
2968                }
2969                break;
2970
2971        case FW_ISO_CONTEXT_RECEIVE:
2972                channels = &ohci->ir_context_channels;
2973                mask     = &ohci->ir_context_mask;
2974                callback = handle_ir_packet_per_buffer;
2975                index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2976                if (index >= 0) {
2977                        *channels &= ~(1ULL << channel);
2978                        *mask     &= ~(1 << index);
2979                        regs = OHCI1394_IsoRcvContextBase(index);
2980                        ctx  = &ohci->ir_context_list[index];
2981                }
2982                break;
2983
2984        case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2985                mask     = &ohci->ir_context_mask;
2986                callback = handle_ir_buffer_fill;
2987                index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2988                if (index >= 0) {
2989                        ohci->mc_allocated = true;
2990                        *mask &= ~(1 << index);
2991                        regs = OHCI1394_IsoRcvContextBase(index);
2992                        ctx  = &ohci->ir_context_list[index];
2993                }
2994                break;
2995
2996        default:
2997                index = -1;
2998                ret = -ENOSYS;
2999        }
3000
3001        spin_unlock_irq(&ohci->lock);
3002
3003        if (index < 0)
3004                return ERR_PTR(ret);
3005
3006        memset(ctx, 0, sizeof(*ctx));
3007        ctx->header_length = 0;
3008        ctx->header = (void *) __get_free_page(GFP_KERNEL);
3009        if (ctx->header == NULL) {
3010                ret = -ENOMEM;
3011                goto out;
3012        }
3013        ret = context_init(&ctx->context, ohci, regs, callback);
3014        if (ret < 0)
3015                goto out_with_header;
3016
3017        if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
3018                set_multichannel_mask(ohci, 0);
3019                ctx->mc_completed = 0;
3020        }
3021
3022        return &ctx->base;
3023
3024 out_with_header:
3025        free_page((unsigned long)ctx->header);
3026 out:
3027        spin_lock_irq(&ohci->lock);
3028
3029        switch (type) {
3030        case FW_ISO_CONTEXT_RECEIVE:
3031                *channels |= 1ULL << channel;
3032                break;
3033
3034        case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3035                ohci->mc_allocated = false;
3036                break;
3037        }
3038        *mask |= 1 << index;
3039
3040        spin_unlock_irq(&ohci->lock);
3041
3042        return ERR_PTR(ret);
3043}
3044
3045static int ohci_start_iso(struct fw_iso_context *base,
3046                          s32 cycle, u32 sync, u32 tags)
3047{
3048        struct iso_context *ctx = container_of(base, struct iso_context, base);
3049        struct fw_ohci *ohci = ctx->context.ohci;
3050        u32 control = IR_CONTEXT_ISOCH_HEADER, match;
3051        int index;
3052
3053        /* the controller cannot start without any queued packets */
3054        if (ctx->context.last->branch_address == 0)
3055                return -ENODATA;
3056
3057        switch (ctx->base.type) {
3058        case FW_ISO_CONTEXT_TRANSMIT:
3059                index = ctx - ohci->it_context_list;
3060                match = 0;
3061                if (cycle >= 0)
3062                        match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
3063                                (cycle & 0x7fff) << 16;
3064
3065                reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3066                reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3067                context_run(&ctx->context, match);
3068                break;
3069
3070        case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3071                control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3072                /* fall through */
3073        case FW_ISO_CONTEXT_RECEIVE:
3074                index = ctx - ohci->ir_context_list;
3075                match = (tags << 28) | (sync << 8) | ctx->base.channel;
3076                if (cycle >= 0) {
3077                        match |= (cycle & 0x07fff) << 12;
3078                        control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3079                }
3080
3081                reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3082                reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3083                reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3084                context_run(&ctx->context, control);
3085
3086                ctx->sync = sync;
3087                ctx->tags = tags;
3088
3089                break;
3090        }
3091
3092        return 0;
3093}
3094
3095static int ohci_stop_iso(struct fw_iso_context *base)
3096{
3097        struct fw_ohci *ohci = fw_ohci(base->card);
3098        struct iso_context *ctx = container_of(base, struct iso_context, base);
3099        int index;
3100
3101        switch (ctx->base.type) {
3102        case FW_ISO_CONTEXT_TRANSMIT:
3103                index = ctx - ohci->it_context_list;
3104                reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3105                break;
3106
3107        case FW_ISO_CONTEXT_RECEIVE:
3108        case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3109                index = ctx - ohci->ir_context_list;
3110                reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3111                break;
3112        }
3113        flush_writes(ohci);
3114        context_stop(&ctx->context);
3115        tasklet_kill(&ctx->context.tasklet);
3116
3117        return 0;
3118}
3119
3120static void ohci_free_iso_context(struct fw_iso_context *base)
3121{
3122        struct fw_ohci *ohci = fw_ohci(base->card);
3123        struct iso_context *ctx = container_of(base, struct iso_context, base);
3124        unsigned long flags;
3125        int index;
3126
3127        ohci_stop_iso(base);
3128        context_release(&ctx->context);
3129        free_page((unsigned long)ctx->header);
3130
3131        spin_lock_irqsave(&ohci->lock, flags);
3132
3133        switch (base->type) {
3134        case FW_ISO_CONTEXT_TRANSMIT:
3135                index = ctx - ohci->it_context_list;
3136                ohci->it_context_mask |= 1 << index;
3137                break;
3138
3139        case FW_ISO_CONTEXT_RECEIVE:
3140                index = ctx - ohci->ir_context_list;
3141                ohci->ir_context_mask |= 1 << index;
3142                ohci->ir_context_channels |= 1ULL << base->channel;
3143                break;
3144
3145        case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3146                index = ctx - ohci->ir_context_list;
3147                ohci->ir_context_mask |= 1 << index;
3148                ohci->ir_context_channels |= ohci->mc_channels;
3149                ohci->mc_channels = 0;
3150                ohci->mc_allocated = false;
3151                break;
3152        }
3153
3154        spin_unlock_irqrestore(&ohci->lock, flags);
3155}
3156
3157static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3158{
3159        struct fw_ohci *ohci = fw_ohci(base->card);
3160        unsigned long flags;
3161        int ret;
3162
3163        switch (base->type) {
3164        case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3165
3166                spin_lock_irqsave(&ohci->lock, flags);
3167
3168                /* Don't allow multichannel to grab other contexts' channels. */
3169                if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3170                        *channels = ohci->ir_context_channels;
3171                        ret = -EBUSY;
3172                } else {
3173                        set_multichannel_mask(ohci, *channels);
3174                        ret = 0;
3175                }
3176
3177                spin_unlock_irqrestore(&ohci->lock, flags);
3178
3179                break;
3180        default:
3181                ret = -EINVAL;
3182        }
3183
3184        return ret;
3185}
3186
3187#ifdef CONFIG_PM
3188static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3189{
3190        int i;
3191        struct iso_context *ctx;
3192
3193        for (i = 0 ; i < ohci->n_ir ; i++) {
3194                ctx = &ohci->ir_context_list[i];
3195                if (ctx->context.running)
3196                        ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3197        }
3198
3199        for (i = 0 ; i < ohci->n_it ; i++) {
3200                ctx = &ohci->it_context_list[i];
3201                if (ctx->context.running)
3202                        ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3203        }
3204}
3205#endif
3206
3207static int queue_iso_transmit(struct iso_context *ctx,
3208                              struct fw_iso_packet *packet,
3209                              struct fw_iso_buffer *buffer,
3210                              unsigned long payload)
3211{
3212        struct descriptor *d, *last, *pd;
3213        struct fw_iso_packet *p;
3214        __le32 *header;
3215        dma_addr_t d_bus, page_bus;
3216        u32 z, header_z, payload_z, irq;
3217        u32 payload_index, payload_end_index, next_page_index;
3218        int page, end_page, i, length, offset;
3219
3220        p = packet;
3221        payload_index = payload;
3222
3223        if (p->skip)
3224                z = 1;
3225        else
3226                z = 2;
3227        if (p->header_length > 0)
3228                z++;
3229
3230        /* Determine the first page the payload isn't contained in. */
3231        end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3232        if (p->payload_length > 0)
3233                payload_z = end_page - (payload_index >> PAGE_SHIFT);
3234        else
3235                payload_z = 0;
3236
3237        z += payload_z;
3238
3239        /* Get header size in number of descriptors. */
3240        header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3241
3242        d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3243        if (d == NULL)
3244                return -ENOMEM;
3245
3246        if (!p->skip) {
3247                d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3248                d[0].req_count = cpu_to_le16(8);
3249                /*
3250                 * Link the skip address to this descriptor itself.  This causes
3251                 * a context to skip a cycle whenever lost cycles or FIFO
3252                 * overruns occur, without dropping the data.  The application
3253                 * should then decide whether this is an error condition or not.
3254                 * FIXME:  Make the context's cycle-lost behaviour configurable?
3255                 */
3256                d[0].branch_address = cpu_to_le32(d_bus | z);
3257
3258                header = (__le32 *) &d[1];
3259                header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3260                                        IT_HEADER_TAG(p->tag) |
3261                                        IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3262                                        IT_HEADER_CHANNEL(ctx->base.channel) |
3263                                        IT_HEADER_SPEED(ctx->base.speed));
3264                header[1] =
3265                        cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3266                                                          p->payload_length));
3267        }
3268
3269        if (p->header_length > 0) {
3270                d[2].req_count    = cpu_to_le16(p->header_length);
3271                d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3272                memcpy(&d[z], p->header, p->header_length);
3273        }
3274
3275        pd = d + z - payload_z;
3276        payload_end_index = payload_index + p->payload_length;
3277        for (i = 0; i < payload_z; i++) {
3278                page               = payload_index >> PAGE_SHIFT;
3279                offset             = payload_index & ~PAGE_MASK;
3280                next_page_index    = (page + 1) << PAGE_SHIFT;
3281                length             =
3282                        min(next_page_index, payload_end_index) - payload_index;
3283                pd[i].req_count    = cpu_to_le16(length);
3284
3285                page_bus = page_private(buffer->pages[page]);
3286                pd[i].data_address = cpu_to_le32(page_bus + offset);
3287
3288                dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3289                                                 page_bus, offset, length,
3290                                                 DMA_TO_DEVICE);
3291
3292                payload_index += length;
3293        }
3294
3295        if (p->interrupt)
3296                irq = DESCRIPTOR_IRQ_ALWAYS;
3297        else
3298                irq = DESCRIPTOR_NO_IRQ;
3299
3300        last = z == 2 ? d : d + z - 1;
3301        last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3302                                     DESCRIPTOR_STATUS |
3303                                     DESCRIPTOR_BRANCH_ALWAYS |
3304                                     irq);
3305
3306        context_append(&ctx->context, d, z, header_z);
3307
3308        return 0;
3309}
3310
3311static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3312                                       struct fw_iso_packet *packet,
3313                                       struct fw_iso_buffer *buffer,
3314                                       unsigned long payload)
3315{
3316        struct device *device = ctx->context.ohci->card.device;
3317        struct descriptor *d, *pd;
3318        dma_addr_t d_bus, page_bus;
3319        u32 z, header_z, rest;
3320        int i, j, length;
3321        int page, offset, packet_count, header_size, payload_per_buffer;
3322
3323        /*
3324         * The OHCI controller puts the isochronous header and trailer in the
3325         * buffer, so we need at least 8 bytes.
3326         */
3327        packet_count = packet->header_length / ctx->base.header_size;
3328        header_size  = max(ctx->base.header_size, (size_t)8);
3329
3330        /* Get header size in number of descriptors. */
3331        header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3332        page     = payload >> PAGE_SHIFT;
3333        offset   = payload & ~PAGE_MASK;
3334        payload_per_buffer = packet->payload_length / packet_count;
3335
3336        for (i = 0; i < packet_count; i++) {
3337                /* d points to the header descriptor */
3338                z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3339                d = context_get_descriptors(&ctx->context,
3340                                z + header_z, &d_bus);
3341                if (d == NULL)
3342                        return -ENOMEM;
3343
3344                d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
3345                                              DESCRIPTOR_INPUT_MORE);
3346                if (packet->skip && i == 0)
3347                        d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3348                d->req_count    = cpu_to_le16(header_size);
3349                d->res_count    = d->req_count;
3350                d->transfer_status = 0;
3351                d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3352
3353                rest = payload_per_buffer;
3354                pd = d;
3355                for (j = 1; j < z; j++) {
3356                        pd++;
3357                        pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3358                                                  DESCRIPTOR_INPUT_MORE);
3359
3360                        if (offset + rest < PAGE_SIZE)
3361                                length = rest;
3362                        else
3363                                length = PAGE_SIZE - offset;
3364                        pd->req_count = cpu_to_le16(length);
3365                        pd->res_count = pd->req_count;
3366                        pd->transfer_status = 0;
3367
3368                        page_bus = page_private(buffer->pages[page]);
3369                        pd->data_address = cpu_to_le32(page_bus + offset);
3370
3371                        dma_sync_single_range_for_device(device, page_bus,
3372                                                         offset, length,
3373                                                         DMA_FROM_DEVICE);
3374
3375                        offset = (offset + length) & ~PAGE_MASK;
3376                        rest -= length;
3377                        if (offset == 0)
3378                                page++;
3379                }
3380                pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3381                                          DESCRIPTOR_INPUT_LAST |
3382                                          DESCRIPTOR_BRANCH_ALWAYS);
3383                if (packet->interrupt && i == packet_count - 1)
3384                        pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3385
3386                context_append(&ctx->context, d, z, header_z);
3387        }
3388
3389        return 0;
3390}
3391
3392static int queue_iso_buffer_fill(struct iso_context *ctx,
3393                                 struct fw_iso_packet *packet,
3394                                 struct fw_iso_buffer *buffer,
3395                                 unsigned long payload)
3396{
3397        struct descriptor *d;
3398        dma_addr_t d_bus, page_bus;
3399        int page, offset, rest, z, i, length;
3400
3401        page   = payload >> PAGE_SHIFT;
3402        offset = payload & ~PAGE_MASK;
3403        rest   = packet->payload_length;
3404
3405        /* We need one descriptor for each page in the buffer. */
3406        z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3407
3408        if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3409                return -EFAULT;
3410
3411        for (i = 0; i < z; i++) {
3412                d = context_get_descriptors(&ctx->context, 1, &d_bus);
3413                if (d == NULL)
3414                        return -ENOMEM;
3415
3416                d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3417                                         DESCRIPTOR_BRANCH_ALWAYS);
3418                if (packet->skip && i == 0)
3419                        d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3420                if (packet->interrupt && i == z - 1)
3421                        d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3422
3423                if (offset + rest < PAGE_SIZE)
3424                        length = rest;
3425                else
3426                        length = PAGE_SIZE - offset;
3427                d->req_count = cpu_to_le16(length);
3428                d->res_count = d->req_count;
3429                d->transfer_status = 0;
3430
3431                page_bus = page_private(buffer->pages[page]);
3432                d->data_address = cpu_to_le32(page_bus + offset);
3433
3434                dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3435                                                 page_bus, offset, length,
3436                                                 DMA_FROM_DEVICE);
3437
3438                rest -= length;
3439                offset = 0;
3440                page++;
3441
3442                context_append(&ctx->context, d, 1, 0);
3443        }
3444
3445        return 0;
3446}
3447
3448static int ohci_queue_iso(struct fw_iso_context *base,
3449                          struct fw_iso_packet *packet,
3450                          struct fw_iso_buffer *buffer,
3451                          unsigned long payload)
3452{
3453        struct iso_context *ctx = container_of(base, struct iso_context, base);
3454        unsigned long flags;
3455        int ret = -ENOSYS;
3456
3457        spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3458        switch (base->type) {
3459        case FW_ISO_CONTEXT_TRANSMIT:
3460                ret = queue_iso_transmit(ctx, packet, buffer, payload);
3461                break;
3462        case FW_ISO_CONTEXT_RECEIVE:
3463                ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3464                break;
3465        case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3466                ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3467                break;
3468        }
3469        spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3470
3471        return ret;
3472}
3473
3474static void ohci_flush_queue_iso(struct fw_iso_context *base)
3475{
3476        struct context *ctx =
3477                        &container_of(base, struct iso_context, base)->context;
3478
3479        reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3480}
3481
3482static int ohci_flush_iso_completions(struct fw_iso_context *base)
3483{
3484        struct iso_context *ctx = container_of(base, struct iso_context, base);
3485        int ret = 0;
3486
3487        tasklet_disable(&ctx->context.tasklet);
3488
3489        if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3490                context_tasklet((unsigned long)&ctx->context);
3491
3492                switch (base->type) {
3493                case FW_ISO_CONTEXT_TRANSMIT:
3494                case FW_ISO_CONTEXT_RECEIVE:
3495                        if (ctx->header_length != 0)
3496                                flush_iso_completions(ctx);
3497                        break;
3498                case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3499                        if (ctx->mc_completed != 0)
3500                                flush_ir_buffer_fill(ctx);
3501                        break;
3502                default:
3503                        ret = -ENOSYS;
3504                }
3505
3506                clear_bit_unlock(0, &ctx->flushing_completions);
3507                smp_mb__after_clear_bit();
3508        }
3509
3510        tasklet_enable(&ctx->context.tasklet);
3511
3512        return ret;
3513}
3514
3515static const struct fw_card_driver ohci_driver = {
3516        .enable                 = ohci_enable,
3517        .read_phy_reg           = ohci_read_phy_reg,
3518        .update_phy_reg         = ohci_update_phy_reg,
3519        .set_config_rom         = ohci_set_config_rom,
3520        .send_request           = ohci_send_request,
3521        .send_response          = ohci_send_response,
3522        .cancel_packet          = ohci_cancel_packet,
3523        .enable_phys_dma        = ohci_enable_phys_dma,
3524        .read_csr               = ohci_read_csr,
3525        .write_csr              = ohci_write_csr,
3526
3527        .allocate_iso_context   = ohci_allocate_iso_context,
3528        .free_iso_context       = ohci_free_iso_context,
3529        .set_iso_channels       = ohci_set_iso_channels,
3530        .queue_iso              = ohci_queue_iso,
3531        .flush_queue_iso        = ohci_flush_queue_iso,
3532        .flush_iso_completions  = ohci_flush_iso_completions,
3533        .start_iso              = ohci_start_iso,
3534        .stop_iso               = ohci_stop_iso,
3535};
3536
3537#ifdef CONFIG_PPC_PMAC
3538static void pmac_ohci_on(struct pci_dev *dev)
3539{
3540        if (machine_is(powermac)) {
3541                struct device_node *ofn = pci_device_to_OF_node(dev);
3542
3543                if (ofn) {
3544                        pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3545                        pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3546                }
3547        }
3548}
3549
3550static void pmac_ohci_off(struct pci_dev *dev)
3551{
3552        if (machine_is(powermac)) {
3553                struct device_node *ofn = pci_device_to_OF_node(dev);
3554
3555                if (ofn) {
3556                        pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3557                        pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3558                }
3559        }
3560}
3561#else
3562static inline void pmac_ohci_on(struct pci_dev *dev) {}
3563static inline void pmac_ohci_off(struct pci_dev *dev) {}
3564#endif /* CONFIG_PPC_PMAC */
3565
3566static int pci_probe(struct pci_dev *dev,
3567                               const struct pci_device_id *ent)
3568{
3569        struct fw_ohci *ohci;
3570        u32 bus_options, max_receive, link_speed, version;
3571        u64 guid;
3572        int i, err;
3573        size_t size;
3574
3575        if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3576                dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3577                return -ENOSYS;
3578        }
3579
3580        ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3581        if (ohci == NULL) {
3582                err = -ENOMEM;
3583                goto fail;
3584        }
3585
3586        fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3587
3588        pmac_ohci_on(dev);
3589
3590        err = pci_enable_device(dev);
3591        if (err) {
3592                dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3593                goto fail_free;
3594        }
3595
3596        pci_set_master(dev);
3597        pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3598        pci_set_drvdata(dev, ohci);
3599
3600        spin_lock_init(&ohci->lock);
3601        mutex_init(&ohci->phy_reg_mutex);
3602
3603        INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3604
3605        if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
3606            pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
3607                ohci_err(ohci, "invalid MMIO resource\n");
3608                err = -ENXIO;
3609                goto fail_disable;
3610        }
3611
3612        err = pci_request_region(dev, 0, ohci_driver_name);
3613        if (err) {
3614                ohci_err(ohci, "MMIO resource unavailable\n");
3615                goto fail_disable;
3616        }
3617
3618        ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3619        if (ohci->registers == NULL) {
3620                ohci_err(ohci, "failed to remap registers\n");
3621                err = -ENXIO;
3622                goto fail_iomem;
3623        }
3624
3625        for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3626                if ((ohci_quirks[i].vendor == dev->vendor) &&
3627                    (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3628                     ohci_quirks[i].device == dev->device) &&
3629                    (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3630                     ohci_quirks[i].revision >= dev->revision)) {
3631                        ohci->quirks = ohci_quirks[i].flags;
3632                        break;
3633                }
3634        if (param_quirks)
3635                ohci->quirks = param_quirks;
3636
3637        /*
3638         * Because dma_alloc_coherent() allocates at least one page,
3639         * we save space by using a common buffer for the AR request/
3640         * response descriptors and the self IDs buffer.
3641         */
3642        BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3643        BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3644        ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3645                                               PAGE_SIZE,
3646                                               &ohci->misc_buffer_bus,
3647                                               GFP_KERNEL);
3648        if (!ohci->misc_buffer) {
3649                err = -ENOMEM;
3650                goto fail_iounmap;
3651        }
3652
3653        err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3654                              OHCI1394_AsReqRcvContextControlSet);
3655        if (err < 0)
3656                goto fail_misc_buf;
3657
3658        err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3659                              OHCI1394_AsRspRcvContextControlSet);
3660        if (err < 0)
3661                goto fail_arreq_ctx;
3662
3663        err = context_init(&ohci->at_request_ctx, ohci,
3664                           OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3665        if (err < 0)
3666                goto fail_arrsp_ctx;
3667
3668        err = context_init(&ohci->at_response_ctx, ohci,
3669                           OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3670        if (err < 0)
3671                goto fail_atreq_ctx;
3672
3673        reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3674        ohci->ir_context_channels = ~0ULL;
3675        ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3676        reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3677        ohci->ir_context_mask = ohci->ir_context_support;
3678        ohci->n_ir = hweight32(ohci->ir_context_mask);
3679        size = sizeof(struct iso_context) * ohci->n_ir;
3680        ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3681
3682        reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3683        ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3684        reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3685        ohci->it_context_mask = ohci->it_context_support;
3686        ohci->n_it = hweight32(ohci->it_context_mask);
3687        size = sizeof(struct iso_context) * ohci->n_it;
3688        ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3689
3690        if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3691                err = -ENOMEM;
3692                goto fail_contexts;
3693        }
3694
3695        ohci->self_id_cpu = ohci->misc_buffer     + PAGE_SIZE/2;
3696        ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3697
3698        bus_options = reg_read(ohci, OHCI1394_BusOptions);
3699        max_receive = (bus_options >> 12) & 0xf;
3700        link_speed = bus_options & 0x7;
3701        guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3702                reg_read(ohci, OHCI1394_GUIDLo);
3703
3704        if (!(ohci->quirks & QUIRK_NO_MSI))
3705                pci_enable_msi(dev);
3706        if (request_irq(dev->irq, irq_handler,
3707                        pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
3708                        ohci_driver_name, ohci)) {
3709                ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq);
3710                err = -EIO;
3711                goto fail_msi;
3712        }
3713
3714        err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3715        if (err)
3716                goto fail_irq;
3717
3718        version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3719        ohci_notice(ohci,
3720                    "added OHCI v%x.%x device as card %d, "
3721                    "%d IR + %d IT contexts, quirks 0x%x\n",
3722                    version >> 16, version & 0xff, ohci->card.index,
3723                    ohci->n_ir, ohci->n_it, ohci->quirks);
3724
3725        return 0;
3726
3727 fail_irq:
3728        free_irq(dev->irq, ohci);
3729 fail_msi:
3730        pci_disable_msi(dev);
3731 fail_contexts:
3732        kfree(ohci->ir_context_list);
3733        kfree(ohci->it_context_list);
3734        context_release(&ohci->at_response_ctx);
3735 fail_atreq_ctx:
3736        context_release(&ohci->at_request_ctx);
3737 fail_arrsp_ctx:
3738        ar_context_release(&ohci->ar_response_ctx);
3739 fail_arreq_ctx:
3740        ar_context_release(&ohci->ar_request_ctx);
3741 fail_misc_buf:
3742        dma_free_coherent(ohci->card.device, PAGE_SIZE,
3743                          ohci->misc_buffer, ohci->misc_buffer_bus);
3744 fail_iounmap:
3745        pci_iounmap(dev, ohci->registers);
3746 fail_iomem:
3747        pci_release_region(dev, 0);
3748 fail_disable:
3749        pci_disable_device(dev);
3750 fail_free:
3751        kfree(ohci);
3752        pmac_ohci_off(dev);
3753 fail:
3754        return err;
3755}
3756
3757static void pci_remove(struct pci_dev *dev)
3758{
3759        struct fw_ohci *ohci = pci_get_drvdata(dev);
3760
3761        /*
3762         * If the removal is happening from the suspend state, LPS won't be
3763         * enabled and host registers (eg., IntMaskClear) won't be accessible.
3764         */
3765        if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
3766                reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3767                flush_writes(ohci);
3768        }
3769        cancel_work_sync(&ohci->bus_reset_work);
3770        fw_core_remove_card(&ohci->card);
3771
3772        /*
3773         * FIXME: Fail all pending packets here, now that the upper
3774         * layers can't queue any more.
3775         */
3776
3777        software_reset(ohci);
3778        free_irq(dev->irq, ohci);
3779
3780        if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3781                dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3782                                  ohci->next_config_rom, ohci->next_config_rom_bus);
3783        if (ohci->config_rom)
3784                dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3785                                  ohci->config_rom, ohci->config_rom_bus);
3786        ar_context_release(&ohci->ar_request_ctx);
3787        ar_context_release(&ohci->ar_response_ctx);
3788        dma_free_coherent(ohci->card.device, PAGE_SIZE,
3789                          ohci->misc_buffer, ohci->misc_buffer_bus);
3790        context_release(&ohci->at_request_ctx);
3791        context_release(&ohci->at_response_ctx);
3792        kfree(ohci->it_context_list);
3793        kfree(ohci->ir_context_list);
3794        pci_disable_msi(dev);
3795        pci_iounmap(dev, ohci->registers);
3796        pci_release_region(dev, 0);
3797        pci_disable_device(dev);
3798        kfree(ohci);
3799        pmac_ohci_off(dev);
3800
3801        dev_notice(&dev->dev, "removed fw-ohci device\n");
3802}
3803
3804#ifdef CONFIG_PM
3805static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3806{
3807        struct fw_ohci *ohci = pci_get_drvdata(dev);
3808        int err;
3809
3810        software_reset(ohci);
3811        err = pci_save_state(dev);
3812        if (err) {
3813                ohci_err(ohci, "pci_save_state failed\n");
3814                return err;
3815        }
3816        err = pci_set_power_state(dev, pci_choose_state(dev, state));
3817        if (err)
3818                ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
3819        pmac_ohci_off(dev);
3820
3821        return 0;
3822}
3823
3824static int pci_resume(struct pci_dev *dev)
3825{
3826        struct fw_ohci *ohci = pci_get_drvdata(dev);
3827        int err;
3828
3829        pmac_ohci_on(dev);
3830        pci_set_power_state(dev, PCI_D0);
3831        pci_restore_state(dev);
3832        err = pci_enable_device(dev);
3833        if (err) {
3834                ohci_err(ohci, "pci_enable_device failed\n");
3835                return err;
3836        }
3837
3838        /* Some systems don't setup GUID register on resume from ram  */
3839        if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3840                                        !reg_read(ohci, OHCI1394_GUIDHi)) {
3841                reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3842                reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3843        }
3844
3845        err = ohci_enable(&ohci->card, NULL, 0);
3846        if (err)
3847                return err;
3848
3849        ohci_resume_iso_dma(ohci);
3850
3851        return 0;
3852}
3853#endif
3854
3855static const struct pci_device_id pci_table[] = {
3856        { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3857        { }
3858};
3859
3860MODULE_DEVICE_TABLE(pci, pci_table);
3861
3862static struct pci_driver fw_ohci_pci_driver = {
3863        .name           = ohci_driver_name,
3864        .id_table       = pci_table,
3865        .probe          = pci_probe,
3866        .remove         = pci_remove,
3867#ifdef CONFIG_PM
3868        .resume         = pci_resume,
3869        .suspend        = pci_suspend,
3870#endif
3871};
3872
3873module_pci_driver(fw_ohci_pci_driver);
3874
3875MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3876MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3877MODULE_LICENSE("GPL");
3878
3879/* Provide a module alias so root-on-sbp2 initrds don't break. */
3880MODULE_ALIAS("ohci1394");
3881
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