linux/drivers/edac/i82443bxgx_edac.c
<<
ptio6.2/spae=" 6.2/form=" 6.2a ptio6. href="../linux+vopti.2/drivers/edac/i82443bxgx_edac.c">ptio6.2img src="../.static/gfx/right.png" alt=">>">pt2/spae="pt2spae class="lxr_search">ptioptio6.2input typ v2hidden" nam v2navtarget" > v2">ptio6.2input typ v2text" nam v2search" idv2search">ptio6.2butt typ v2submit">Searchptio6.Prefs" 6.2/a>pt2/spae="io6. .2/div="io6. .2form acalue="ajax+*" method="post" onsubmit="return false;">pt2input typ v2hidden" nam v2ajax_lookup" idv2ajax_lookup" > v2">pio6. .2/form="pio6. .2div class="headingbott m">" 2div idv2file_contents"=
. .12/a>2spae class="comment">/*2/spae=". .22/a>2spae class="comment"> * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel2/spae=". .32/a>2spae class="comment"> * module (C) 2006 Tim Small2/spae=". .42/a>2spae class="comment"> *2/spae=". .52/a>2spae class="comment"> * This file may be distributed under the terms of the GNU General2/spae=". .62/a>2spae class="comment"> * Public License.2/spae=". .72/a>2spae class="comment"> *2/spae=". .82/a>2spae class="comment"> * Written by Tim Small <tim@buttersideup.com>, based 
	 work by Linux2/spae=". .92/a>2spae class="comment"> * Networx, Thayne Harbaugh, Dae Hollis <goemon at anime dot net> and2/spae=". tiona>2spae class="comment"> * others.2/spae=". 112/a>2spae class="comment"> *2/spae=". 122/a>2spae class="comment"> * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.2/spae=". 132/a>2spae class="comment"> *2/spae=". 142/a>2spae class="comment"> * Written with reference to 82443BX Host Bridge Datasheet:2/spae=". 152/a>2spae class="comment"> * http://download.intel.com/design/chipsets/datashts/29063301.pdf2/spae=". 162/a>2spae class="comment"> * references to this document given in [].2/spae=". 172/a>2spae class="comment"> *2/spae=". 182/a>2spae class="comment"> * This module doesn't support the 440LX, but it may be possible to2/spae=". 192/a>2spae class="comment"> * make it do so (the 440LX's register definialues are different, but2/spae=". 2iona>2spae class="comment"> * not completely so - I haven't studied them in enough detail to know2/spae=". 212/a>2spae class="comment"> * how easy this would be).2/spae=". 222/a>2spae class="comment"> */2/spae=". 232/a>". 242/a>#include <linux/module.h2/a>>". 252/a>#include <linux/inia.h2/a>>". 262/a>". 272/a>#include <linux/pci.h2/a>>". 282/a>#include <linux/pci_ids.h2/a>>". 292/a>". 302/a>". 312/a>#include <linux/edac.h2/a>>". 322/a>#include "edac_core.h2/a>"". 332/a>". 342/a>#define.2a href="+code=I82443_REVISION" class="sref">I82443_REVISION2/a> 2spae class="string">"0.1". 352/a>". 362/a>#define.2a href="+code=EDAC_MOD_STR" class="sref">EDAC_MOD_STR2/a> . .2spae class="string">"i82443bxgx_edac". 372/a>". 382/a>2spae class="comment">/* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory. 392/a>2spae class="comment"> * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory. 4iona>2spae class="comment"> * rows" "The 82443BX supports multiple-bit error detecalue and2/spae=". 412/a>2spae class="comment"> * single-bit error correcalue when ECC mode is enabled and2/spae=". 422/a>2spae class="comment"> * single/multi-bit error detecalue when correcalue is disabled.2/spae=". 432/a>2spae class="comment"> * During writes to the DRAM, the 82443BX generates ECC for the data2/spae=". 442/a>2spae class="comment"> * ue a QWord basis. Partial QWord writes require a read-modify-write2/spae=". 452/a>2spae class="comment"> * cycle when ECC is enabled.". 462/a>2spae class="comment">*/2/spae=". 472/a>". 482/a>2spae class="comment">/* "Addialueally, the 82443BX ensures that the data is correcaed in2/spae=". 492/a>2spae class="comment"> * main memory so that accumulaalue of errors is prevented. Another2/spae=". 5iona>2spae class="comment"> * error within the sam  QWord would result in a double-bit error2/spae=". 512/a>2spae class="comment"> * which is unrecoverable. This is known as hardware scrubbing since2/spae=". 522/a>2spae class="comment"> * it requires no software interventlue to correca the data in memory.". 532/a>2spae class="comment"> */2/spae=". 542/a>". 552/a>2spae class="comment">/* [Also see page 100 (secalue 4.3), "DRAM Interface"]2/spae=". 562/a>2spae class="comment"> * [Also see page 112 (secalue 4.6.1.4), ECC]2/spae=". 572/a>2spae class="comment"> */2/spae=". 582/a>". 592/a>#define.2a href="+code=I82443BXGX_NR_CSROWS" class="sref">I82443BXGX_NR_CSROWS2/a> 8". 602/a>#define.2a href="+code=I82443BXGX_NR_CHANS" class="sref">I82443BXGX_NR_CHANS2/a> .1". 612/a>#define.2a href="+code=I82443BXGX_NR_DIMMS" class="sref">I82443BXGX_NR_DIMMS2/a> .4". 622/a>". 632/a>2spae class="comment">/* 82443 PCI Device 0 */2/spae=". 642/a>#define.2a href="+code=I82443BXGX_NBXCFG" class="sref">I82443BXGX_NBXCFG2/a> 0x50 .2spae class="comment">/* 32bit register starting at this PCI2/spae=". 652/a>2spae class="comment">                                 * config space offset */2/spae=". 662/a>#define.2a href="+code=I82443BXGX_NBXCFG_OFFSET_NON_ECCROW" class="sref">I82443BXGX_NBXCFG_OFFSET_NON_ECCROW2/a> 24 .2spae class="comment">/* Array of bits, zero if2/spae=". 672/a>2spae class="comment">                                                 * row is non-ECC */2/spae=". 682/a>#define.2a href="+code=I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ" class="sref">I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ2/a> 12  .2spae class="comment">/* 2 bits,00=100MHz,10=66 MHz */2/spae=". 692/a>". 702/a>#define.2a href="+code=I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY" class="sref">I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY2/a> 7       2spae class="comment">/* 2 bits:       */2/spae=". 712/a>#define.2a href="+code=I82443BXGX_NBXCFG_INTEGRITY_NONE" class="sref">I82443BXGX_NBXCFG_INTEGRITY_NONE2/a> . 0x0 .2spae class="comment">/* 00 = Non-ECC */2/spae=". 722/a>#define.2a href="+code=I82443BXGX_NBXCFG_INTEGRITY_EC" class="sref">I82443BXGX_NBXCFG_INTEGRITY_EC2/a> . . 0x1 .2spae class="comment">/* 01 = EC (only) */2/spae=". 732/a>#define.2a href="+code=I82443BXGX_NBXCFG_INTEGRITY_ECC" class="sref">I82443BXGX_NBXCFG_INTEGRITY_ECC2/a> . .0x2 .2spae class="comment">/* 10 = ECC */2/spae=". 742/a>#define.2a href="+code=I82443BXGX_NBXCFG_INTEGRITY_SCRUB" class="sref">I82443BXGX_NBXCFG_INTEGRITY_SCRUB2/a> .0x3 .2spae class="comment">/* 11 = ECC + HW Scrub */2/spae=". 752/a>". 762/a>#define.2a href="+code=I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE" class="sref">I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE2/a> .6". 772/a>". 782/a>2spae class="comment">/* 82443 PCI Device 0 */2/spae=". 792/a>#define.2a href="+code=I82443BXGX_EAP" class="sref">I82443BXGX_EAP2/a> . 0x80   2spae class="comment">/* 32bit register starting at this PCI2/spae=". 8iona>2spae class="comment">                                 * config space offset, Error Address2/spae=". 812/a>2spae class="comment">                                 * Pointer Register */2/spae=". 822/a>#define.2a href="+code=I82443BXGX_EAP_OFFSET_EAP" class="sref">I82443BXGX_EAP_OFFSET_EAP2/a> .12  .2spae class="comment">/* High 20 bits of error address */2/spae=". 832/a>#define.2a href="+code=I82443BXGX_EAP_OFFSET_MBE" class="sref">I82443BXGX_EAP_OFFSET_MBE2/a> .2a href="+code=BIT" class="sref">BIT2/a>(1)       2spae class="comment">/* Err at EAP was multi-bit (W1TC) */2/spae=". 842/a>#define.2a href="+code=I82443BXGX_EAP_OFFSET_SBE" class="sref">I82443BXGX_EAP_OFFSET_SBE2/a> .2a href="+code=BIT" class="sref">BIT2/a>(0)       2spae class="comment">/* Err at EAP was single-bit (W1TC) */2/spae=". 852/a>". 862/a>#define.2a href="+code=I82443BXGX_ERRCMD" class="sref">I82443BXGX_ERRCMD2/a> .0x90 2spae class="comment">/* 8bit register starting at this PCI2/spae=". 872/a>2spae class="comment">                                 * config space offset. */2/spae=". 882/a>#define.2a href="+code=I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE" class="sref">I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE2/a> 2a href="+code=BIT" class="sref">BIT2/a>(1)     2spae class="comment">/* 1 = enable */2/spae=". 892/a>#define.2a href="+code=I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE" class="sref">I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE2/a> 2a href="+code=BIT" class="sref">BIT2/a>(0)     2spae class="comment">/* 1 = enable */2/spae=". 902/a>". 912/a>#define.2a href="+code=I82443BXGX_ERRSTS" class="sref">I82443BXGX_ERRSTS2/a> .0x91 2spae class="comment">/* 16bit register starting at this PCI2/spae=". 922/a>2spae class="comment">                                 * config space offset. */2/spae=". 932/a>#define.2a href="+code=I82443BXGX_ERRSTS_OFFSET_MBFRE" class="sref">I82443BXGX_ERRSTS_OFFSET_MBFRE2/a> 5        2spae class="comment">/* 3 bits - first err row multibit */2/spae=". 942/a>#define.2a href="+code=I82443BXGX_ERRSTS_OFFSET_MEF" class="sref">I82443BXGX_ERRSTS_OFFSET_MEF2/a> . 2a href="+code=BIT" class="sref">BIT2/a>(4)   2spae class="comment">/* 1 = MBE occurred */2/spae=". 952/a>#define.2a href="+code=I82443BXGX_ERRSTS_OFFSET_SBFRE" class="sref">I82443BXGX_ERRSTS_OFFSET_SBFRE2/a> 1        2spae class="comment">/* 3 bits - first err row singlebit */2/spae=". 962/a>#define.2a href="+code=I82443BXGX_ERRSTS_OFFSET_SEF" class="sref">I82443BXGX_ERRSTS_OFFSET_SEF2/a> . 2a href="+code=BIT" class="sref">BIT2/a>(0)   2spae class="comment">/* 1 = SBE occurred */2/spae=". 972/a>". 982/a>#define.2a href="+code=I82443BXGX_DRAMC" class="sref">I82443BXGX_DRAMC2/a> 0x57   2spae class="comment">/* 8bit register starting at this PCI2/spae=". 992/a>2spae class="comment">                                 * config space offset. */2/spae=".1002/a>#define.2a href="+code=I82443BXGX_DRAMC_OFFSET_DT" class="sref">I82443BXGX_DRAMC_OFFSET_DT2/a> 3    2spae class="comment">/* 2 bits, DRAM Type */2/spae=".1012/a>#define.2a href="+code=I82443BXGX_DRAMC_DRAM_IS_EDO" class="sref">I82443BXGX_DRAMC_DRAM_IS_EDO2/a> 0 .2spae class="comment">/* 00 = EDO */2/spae=".1022/a>#define.2a href="+code=I82443BXGX_DRAMC_DRAM_IS_SDRAM" class="sref">I82443BXGX_DRAMC_DRAM_IS_SDRAM2/a> 1        2spae class="comment">/* 01 = SDRAM */2/spae=".1032/a>#define.2a href="+code=I82443BXGX_DRAMC_DRAM_IS_RSDRAM" class="sref">I82443BXGX_DRAMC_DRAM_IS_RSDRAM2/a> 2       2spae class="comment">/* 10 = Registered SDRAM */2/spae=".1042/a>".1052/a>#define.2a href="+code=I82443BXGX_DRB" class="sref">I82443BXGX_DRB2/a> 0x60     2spae class="comment">/* 8x 8bit registers starting at this PCI2/spae=".1062/a>2spae class="comment">                                 * config space offset. */2/spae=".1072/a>".1082/a>2spae class="comment">/* FIXME - don't poll when ECC disabled? */2/spae=".1092/a>".1tiona>struct.2a href="+code=i82443bxgx_edacmc_error_info" class="sref">i82443bxgx_edacmc_error_info2/a> {".1112/a>        2a href="+code=u32" class="sref">u322/a> 2a href="+code=eap" class="sref">eap2/a>;".1122/a>};".1132/a>".1142/a>static struct.2a href="+code=edac_pci_ctl_info" class="sref">edac_pci_ctl_info2/a> *2a href="+code=i82443bxgx_pci" class="sref">i82443bxgx_pci2/a>;".1152/a>".1162/a>static struct.2a href="+code=pci_dev" class="sref">pci_dev2/a> *2a href="+code=mci_pdev" class="sref">mci_pdev2/a>;        2spae class="comment">/* inia dev: in case that AGP code has2/spae=".1172/a>2spae class="comment">                                         * already registered driver2/spae=".1182/a>2spae class="comment">                                         */2/spae=".1192/a>".1202/a>static int.2a href="+code=i82443bxgx_registered" class="sref">i82443bxgx_registered2/a> = 1;".1212/a>".1222/a>static void.2a href="+code=i82443bxgx_edacmc_get_error_info" class="sref">i82443bxgx_edacmc_get_error_info2/a>(struct.2a href="+code=mem_ctl_info" class="sref">mem_ctl_info2/a> *2a href="+code=mci" class="sref">mci2/a>,".1232/a>                                struct.2a href="+code=i82443bxgx_edacmc_error_info" class="sref">i82443bxgx_edacmc_error_info2/a>".1242/a>                                *2a href="+code=info" class="sref">info2/a>)".1252/a>{".1262/a>        struct.2a href="+code=pci_dev" class="sref">pci_dev2/a> *2a href="+code=pdev" class="sref">pdev2/a>;".1272/a>        2a href="+code=pdev" class="sref">pdev2/a> = 2a href="+code=to_pci_dev" class="sref">to_pci_dev2/a>(2a href="+code=mci" class="sref">mci2/a>->2a href="+code=pdev" class="sref">pdev2/a>);".1282/a>        2a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword2/a>(2a href="+code=pdev" class="sref">pdev2/a>,.2a href="+code=I82443BXGX_EAP" class="sref">I82443BXGX_EAP2/a>, &2a href="+code=info" class="sref">info2/a>->2a href="+code=eap" class="sref">eap2/a>);".1292/a>        if (2a href="+code=info" class="sref">info2/a>->2a href="+code=eap" class="sref">eap2/a> &.2a href="+code=I82443BXGX_EAP_OFFSET_SBE" class="sref">I82443BXGX_EAP_OFFSET_SBE2/a>)".1302/a>                2spae class="comment">/* Clear error to allow next error to be reported [p.61] */2/spae=".1312/a>                2a href="+code=pci_write_bits32" class="sref">pci_write_bits322/a>(2a href="+code=pdev" class="sref">pdev2/a>,.2a href="+code=I82443BXGX_EAP" class="sref">I82443BXGX_EAP2/a>,".1322/a>                                 2a href="+code=I82443BXGX_EAP_OFFSET_SBE" class="sref">I82443BXGX_EAP_OFFSET_SBE2/a>,".1332/a>                                .2a href="+code=I82443BXGX_EAP_OFFSET_SBE" class="sref">I82443BXGX_EAP_OFFSET_SBE2/a>);".1342/a>".1352/a>        if (2a href="+code=info" class="sref">info2/a>->2a href="+code=eap" class="sref">eap2/a> &.2a href="+code=I82443BXGX_EAP_OFFSET_MBE" class="sref">I82443BXGX_EAP_OFFSET_MBE2/a>)".1362/a>                2spae class="comment">/* Clear error to allow next error to be reported [p.61] */2/spae=".1372/a>                2a href="+code=pci_write_bits32" class="sref">pci_write_bits322/a>(2a href="+code=pdev" class="sref">pdev2/a>,.2a href="+code=I82443BXGX_EAP" class="sref">I82443BXGX_EAP2/a>,".1382/a>                                .2a href="+code=I82443BXGX_EAP_OFFSET_MBE" class="sref">I82443BXGX_EAP_OFFSET_MBE2/a>,".1392/a>                                .2a href="+code=I82443BXGX_EAP_OFFSET_MBE" class="sref">I82443BXGX_EAP_OFFSET_MBE2/a>);".14iona>}".1412/a>".1422/a>static int.2a href="+code=i82443bxgx_edacmc_process_error_info" class="sref">i82443bxgx_edacmc_process_error_info2/a>(struct.2a href="+code=mem_ctl_info" class="sref">mem_ctl_info2/a> *2a href="+code=mci" class="sref">mci2/a>,".1432/a>                                ................struct".1442/a>                                               .2a href="+code=i82443bxgx_edacmc_error_info" class="sref">i82443bxgx_edacmc_error_info2/a>".1452/a>                                               .*2a href="+code=info" class="sref">info2/a>, int.2a href="+code=handle_errors" class="sref">handle_errors2/a>)".1462/a>{".1472/a>        int.2a href="+code=error_found" class="sref">error_found2/a> = 0;".1482/a>        2a href="+code=u32" class="sref">u322/a> 2a href="+code=eapaddr" class="sref">eapaddr2/a>,.2a href="+code=page" class="sref">page2/a>,.2a href="+code=pageoffset" class="sref">pageoffset2/a>;".1492/a>".1502/a>        2spae class="comment">/* bits 30:12 hold the 4kb block in which the error occurred2/spae=".1512/a>2spae class="comment">        .* [p.61] */2/spae=".1522/a>        2a href="+code=eapaddr" class="sref">eapaddr2/a> = (2a href="+code=info" class="sref">info2/a>->2a href="+code=eap" class="sref">eap2/a> &.0xfffff000);".1532/a>        2a href="+code=page" class="sref">page2/a> = 2a href="+code=eapaddr" class="sref">eapaddr2/a> >> 2a href="+code=PAGE_SHIFT" class="sref">PAGE_SHIFT2/a>;".1542/a>        2a href="+code=pageoffset" class="sref">pageoffset2/a> = 2a href="+code=eapaddr" class="sref">eapaddr2/a> - (2a href="+code=page" class="sref">page2/a> << 2a href="+code=PAGE_SHIFT" class="sref">PAGE_SHIFT2/a>);".1552/a>".1562/a>        if (2a href="+code=info" class="sref">info2/a>->2a href="+code=eap" class="sref">eap2/a> &.2a href="+code=I82443BXGX_EAP_OFFSET_SBE" class="sref">I82443BXGX_EAP_OFFSET_SBE2/a>) {".1572/a>                2a href="+code=error_found" class="sref">error_found2/a> = 1;".1582/a>                if (2a href="+code=handle_errors" class="sref">handle_errors2/a>)".1592/a>                        2a href="+code=edac_mc_handle_error" class="sref">edac_mc_handle_error2/a>(2a href="+code=HW_EVENT_ERR_CORRECTED" class="sref">HW_EVENT_ERR_CORRECTED2/a>,.2a href="+code=mci" class="sref">mci2/a>, 1,".1602/a>                                             2a href="+code=page" class="sref">page2/a>,.2a href="+code=pageoffset" class="sref">pageoffset2/a>, 0,".1612/a>                                             2a href="+code=edac_mc_find_csrow_by_page" class="sref">edac_mc_find_csrow_by_page2/a>(2a href="+code=mci" class="sref">mci2/a>,.2a href="+code=page" class="sref">page2/a>),".1622/a>                                             0, -1,.2a href="+code=mci" class="sref">mci2/a>->2a href="+code=ctl_nam " class="sref">ctl_nam 2/a>,.2spae class="string">"".1632/a>        }".1642/a>".1652/a>        if (2a href="+code=info" class="sref">info2/a>->2a href="+code=eap" class="sref">eap2/a> &.2a href="+code=I82443BXGX_EAP_OFFSET_MBE" class="sref">I82443BXGX_EAP_OFFSET_MBE2/a>) {".1662/a>                2a href="+code=error_found" class="sref">error_found2/a> = 1;".1672/a>                if (2a href="+code=handle_errors" class="sref">handle_errors2/a>)".1682/a>                        2a href="+code=edac_mc_handle_error" class="sref">edac_mc_handle_error2/a>(2a href="+code=HW_EVENT_ERR_UNCORRECTED" class="sref">HW_EVENT_ERR_UNCORRECTED2/a>,.2a href="+code=mci" class="sref">mci2/a>, 1,".1692/a>                                .            2a href="+code=page" class="sref">page2/a>,.2a href="+code=pageoffset" class="sref">pageoffset2/a>, 0,".1702/a>                                             2a href="+code=edac_mc_find_csrow_by_page" class="sref">edac_mc_find_csrow_by_page2/a>(2a href="+code=mci" class="sref">mci2/a>,.2a href="+code=page" class="sref">page2/a>),".1712/a>                                             0, -1,.2a href="+code=mci" class="sref">mci2/a>->2a href="+code=ctl_nam " class="sref">ctl_nam 2/a>,.2spae class="string">"".1722/a>        }".1732/a>".1742/a>        return 2a href="+code=error_found" class="sref">error_found2/a>;".1752/a>}".1762/a>".1772/a>static void.2a href="+code=i82443bxgx_edacmc_check" class="sref">i82443bxgx_edacmc_check2/a>(struct.2a href="+code=mem_ctl_info" class="sref">mem_ctl_info2/a> *2a href="+code=mci" class="sref">mci2/a>)".1782/a>{".1792/a>        struct.2a href="+code=i82443bxgx_edacmc_error_info" class="sref">i82443bxgx_edacmc_error_info2/a> 2a href="+code=info" class="sref">info2/a>;".1802/a>".1812/a>        2a href="+code=edac_dbg" class="sref">edac_dbg2/a>(1,.2spae class="string">"MC%d\n"mci2/a>->2a href="+code=mc_idx" class="sref">mc_idx2/a>);".1822/a>        2a href="+code=i82443bxgx_edacmc_get_error_info" class="sref">i82443bxgx_edacmc_get_error_info2/a>(2a href="+code=mci" class="sref">mci2/a>,.&2a href="+code=info" class="sref">info2/a>);".1832/a>        2a href="+code=i82443bxgx_edacmc_process_error_info" class="sref">i82443bxgx_edacmc_process_error_info2/a>(2a href="+code=mci" class="sref">mci2/a>,.&2a href="+code=info" class="sref">info2/a>, 1);".1842/a>}".1852/a>".1862/a>static void.2a href="+code=i82443bxgx_inia_csrows" class="sref">i82443bxgx_inia_csrows2/a>(struct.2a href="+code=mem_ctl_info" class="sref">mem_ctl_info2/a> *2a href="+code=mci" class="sref">mci2/a>,".1872/a>                                struct.2a href="+code=pci_dev" class="sref">pci_dev2/a> *2a href="+code=pdev" class="sref">pdev2/a>,".1882/a>                                enum 2a href="+code=edac_type" class="sref">edac_type2/a> 2a href="+code=edac_mode" class="sref">edac_mode2/a>,".1892/a>                                enum 2a href="+code=mem_type" class="sref">mem_type2/a> 2a href="+code=mtype" class="sref">mtype2/a>)".1902/a>{".1912/a>        struct.2a href="+code=csrow_info" class="sref">csrow_info2/a> *2a href="+code=csrow" class="sref">csrow2/a>;".1922/a>        struct.2a href="+code=dimm_info" class="sref">dimm_info2/a> *2a href="+code=dimm" class="sref">dimm2/a>;".1932/a>        int.2a href="+code=index" class="sref">index2/a>;".1942/a>        2a href="+code=u8" class="sref">u82/a> 2a href="+code=drbar" class="sref">drbar2/a>,.2a href="+code=dramc" class="sref">dramc2/a>;".1952/a>        2a href="+code=u32" class="sref">u322/a> 2a href="+code=row_base" class="sref">row_base2/a>,.2a href="+code=row_high_limit" class="sref">row_high_limit2/a>,.2a href="+code=row_high_limit_last" class="sref">row_high_limit_last2/a>;".1962/a>".1972/a>        2a href="+code=pci_read_config_byte" class="sref">pci_read_config_byte2/a>(2a href="+code=pdev" class="sref">pdev2/a>,.2a href="+code=I82443BXGX_DRAMC" class="sref">I82443BXGX_DRAMC2/a>,.&2a href="+code=dramc" class="sref">dramc2/a>);".1982/a>        2a href="+code=row_high_limit_last" class="sref">row_high_limit_last2/a> = 0;".1992/a>        for (2a href="+code=index" class="sref">index2/a> = 0;.2a href="+code=index" class="sref">index2/a> < 2a href="+code=mci" class="sref">mci2/a>->2a href="+code=nr_csrows" class="sref">nr_csrows2/a>;.2a href="+code=index" class="sref">index2/a>++) {".2002/a>                2a href="+code=csrow" class="sref">csrow2/a> = 2a href="+code=mci" class="sref">mci2/a>->2a href="+code=csrows" class="sref">csrows2/a>[2a href="+code=index" class="sref">index2/a>];".2012/a>                2a href="+code=dimm" class="sref">dimm2/a> = 2a href="+code=csrow" class="sref">csrow2/a>->2a href="+code=channels" class="sref">channels2/a>[0]->2a href="+code=dimm" class="sref">dimm2/a>;".2022/a>".2032/a>                2a href="+code=pci_read_config_byte" class="sref">pci_read_config_byte2/a>(2a href="+code=pdev" class="sref">pdev2/a>,.2a href="+code=I82443BXGX_DRB" class="sref">I82443BXGX_DRB2/a> +.2a href="+code=index" class="sref">index2/a>,.&2a href="+code=drbar" class="sref">drbar2/a>);".2042/a>                2a href="+code=edac_dbg" class="sref">edac_dbg2/a>(1,.2spae class="string">"MC%d: Row=%d DRB = %#0x\n".2052/a>                         2a href="+code=mci" class="sref">mci2/a>->2a href="+code=mc_idx" class="sref">mc_idx2/a>,.2a href="+code=index" class="sref">index2/a>,.2a href="+code=drbar" class="sref">drbar2/a>);".2062/a>                2a href="+code=row_high_limit" class="sref">row_high_limit2/a> = ((2a href="+code=u32" class="sref">u322/a>).2a href="+code=drbar" class="sref">drbar2/a> << 23);".2072/a>                2spae class="comment">/* find the DRAM Chip Seleca Base address and mask */2/spae=".2082/a>                2a href="+code=edac_dbg" class="sref">edac_dbg2/a>(1,.2spae class="string">"MC%d: Row=%d, Boundary Address=%#0x, Last = %#0x\n".2092/a>                         2a href="+code=mci" class="sref">mci2/a>->2a href="+code=mc_idx" class="sref">mc_idx2/a>,.2a href="+code=index" class="sref">index2/a>,.2a href="+code=row_high_limit" class="sref">row_high_limit2/a>,".2102/a>                         2a href="+code=row_high_limit_last" class="sref">row_high_limit_last2/a>);".2112/a>".2122/a>                2spae class="comment">/* 440GX goes to 2GB, represented with a DRB of 0. */2/spae=".2132/a>                if (2a href="+code=row_high_limit_last" class="sref">row_high_limit_last2/a> &&.!2a href="+code=row_high_limit" class="sref">row_high_limit2/a>)".2142/a>                        2a href="+code=row_high_limit" class="sref">row_high_limit2/a> = 1UL << 31;".2152/a>".2162/a>                2spae class="comment">/* This row is empty [p.49] */2/spae=".2172/a>                if (2a href="+code=row_high_limit" class="sref">row_high_limit2/a> == 2a href="+code=row_high_limit_last" class="sref">row_high_limit_last2/a>)".2182/a>                        continue;".2192/a>                2a href="+code=row_base" class="sref">row_base2/a> = 2a href="+code=row_high_limit_last" class="sref">row_high_limit_last2/a>;".2202/a>                2a href="+code=csrow" class="sref">csrow2/a>->2a href="+code=first_page" class="sref">first_page2/a> = 2a href="+code=row_base" class="sref">row_base2/a> >> 2a href="+code=PAGE_SHIFT" class="sref">PAGE_SHIFT2/a>;".2212/a>                2a href="+code=csrow" class="sref">csrow2/a>->2a href="+code=last_page" class="sref">last_page2/a> = (2a href="+code=row_high_limit" class="sref">row_high_limit2/a> >> 2a href="+code=PAGE_SHIFT" class="sref">PAGE_SHIFT2/a>) - 1;".2222/a>                2a href="+code=dimm" class="sref">dimm2/a>->2a href="+code=nr_pages" class="sref">nr_pages2/a> = 2a href="+code=csrow" class="sref">csrow2/a>->2a href="+code=last_page" class="sref">last_page2/a> - 2a href="+code=csrow" class="sref">csrow2/a>->2a href="+code=first_page" class="sref">first_page2/a> + 1;".2232/a>                2spae class="comment">/* EAP reports in 4kilobyte granularity [61] */2/spae=".2242/a>                2a href="+code=dimm" class="sref">dimm2/a>->2a href="+code=grain" class="sref">grain2/a> = 1 << 12;".2252/a>                2a href="+code=dimm" class="sref">dimm2/a>->2a href="+code=mtype" class="sref">mtype2/a> = 2a href="+code=mtype" class="sref">mtype2/a>;".2262/a>                2spae class="comment">/* I don't think 440BX cae tell you device type? FIXME? */2/spae=".2272/a>                2a href="+code=dimm" class="sref">dimm2/a>->2a href="+code=dtype" class="sref">dtype2/a> = 2a href="+code=DEV_UNKNOWN" class="sref">DEV_UNKNOWN2/a>;".2282/a>                2spae class="comment">/* Mode is global to all rows on 440BX */2/spae=".2292/a>                2a href="+code=dimm" class="sref">dimm2/a>->2a href="+code=edac_mode" class="sref">edac_mode2/a> = 2a href="+code=edac_mode" class="sref">edac_mode2/a>;".2302/a>                2a href="+code=row_high_limit_last" class="sref">row_high_limit_last2/a> = 2a href="+code=row_high_limit" class="sref">row_high_limit2/a>;".2312/a>        }".2322/a>}".2332/a>".2342/a>static int.2a href="+code=i82443bxgx_edacmc_probe1" class="sref">i82443bxgx_edacmc_probe12/a>(struct.2a href="+code=pci_dev" class="sref">pci_dev2/a> *2a href="+code=pdev" class="sref">pdev2/a>, int.2a href="+code=dev_idx" class="sref">dev_idx2/a>)".2352/a>{".2362/a>        struct.2a href="+code=mem_ctl_info" class="sref">mem_ctl_info2/a> *2a href="+code=mci" class="sref">mci2/a>;".2372/a>        struct.2a href="+code=edac_mc_layer" class="sref">edac_mc_layer2/a> 2a href="+code=layers" class="sref">layers2/a>[2];".2382/a>        2a href="+code=u8" class="sref">u82/a> 2a href="+code=dramc" class="sref">dramc2/a>;".2392/a>        2a href="+code=u32" class="sref">u322/a> 2a href="+code=nbxcfg" class="sref">nbxcfg2/a>,.2a href="+code=ecc_mode" class="sref">ecc_mode2/a>;".2402/a>        enum 2a href="+code=mem_type" class="sref">mem_type2/a> 2a href="+code=mtype" class="sref">mtype2/a>;".2412/a>        enum 2a href="+code=edac_type" class="sref">edac_type2/a> 2a href="+code=edac_mode" class="sref">edac_mode2/a>;".2422/a>".2432/a>        2a href="+code=edac_dbg" class="sref">edac_dbg2/a>(0,.2spae class="string">"MC:\n".2442/a>".2452/a>        2spae class="comment">/* Something is really hosed if PCI config space reads from2/spae=".2462/a>2spae class="comment">         * the MC aren't working.2/spae=".2472/a>2spae class="comment">         */2/spae=".2482/a>        if (2a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword2/a>(2a href="+code=pdev" class="sref">pdev2/a>,.2a href="+code=I82443BXGX_NBXCFG" class="sref">I82443BXGX_NBXCFG2/a>,.&2a href="+code=nbxcfg" class="sref">nbxcfg2/a>))".2492/a>                return -2a href="+code=EIO" class="sref">EIO2/a>;".2502/a>".2512/a>        2a href="+code=layers" class="sref">layers2/a>[0].2a href="+code=type" class="sref">type2/a> = 2a href="+code=EDAC_MC_LAYER_CHIP_SELECT" class="sref">EDAC_MC_LAYER_CHIP_SELECT2/a>;".2522/a>        2a href="+code=layers" class="sref">layers2/a>[0].2a href="+code=size" class="sref">size2/a> = 2a href="+code=I82443BXGX_NR_CSROWS" class="sref">I82443BXGX_NR_CSROWS2/a>;".2532/a>        2a href="+code=layers" class="sref">layers2/a>[0].2a href="+code=is_vira_csrow" class="sref">is_vira_csrow2/a> = 2a href="+code=true" class="sref">true2/a>;".2542/a>        2a href="+code=layers" class="sref">layers2/a>[1].2a href="+code=type" class="sref">type2/a> = 2a href="+code=EDAC_MC_LAYER_CHANNEL" class="sref">EDAC_MC_LAYER_CHANNEL2/a>;".2552/a>        2a href="+code=layers" class="sref">layers2/a>[1].2a href="+code=size" class="sref">size2/a> = 2a href="+code=I82443BXGX_NR_CHANS" class="sref">I82443BXGX_NR_CHANS2/a>;".2562/a>        2a href="+code=layers" class="sref">layers2/a>[1].2a href="+code=is_vira_csrow" class="sref">is_vira_csrow2/a> = 2a href="+code=false" class="sref">false2/a>;".2572/a>        2a href="+code=mci" class="sref">mci2/a> = 2a href="+code=edac_mc_alloc" class="sref">edac_mc_alloc2/a>(0,.2a href="+code=ARRAY_SIZE" class="sref">ARRAY_SIZE2/a>(2a href="+code=layers" class="sref">layers2/a>),.2a href="+code=layers" class="sref">layers2/a>, 0);".2582/a>        if (2a href="+code=mci" class="sref">mci2/a> == 2a href="+code=NULL" class="sref">NULL2/a>)".2592/a>                return -2a href="+code=ENOMEM" class="sref">ENOMEM2/a>;".2602/a>".2612/a>        2a href="+code=edac_dbg" class="sref">edac_dbg2/a>(0,.2spae class="string">"MC: mci = %p\n"mci2/a>);".2622/a>        2a href="+code=mci" class="sref">mci2/a>->2a href="+code=pdev" class="sref">pdev2/a> = &2a href="+code=pdev" class="sref">pdev2/a>->2a href="+code=dev" class="sref">dev2/a>;".2632/a>        2a href="+code=mci" class="sref">mci2/a>->2a href="+code=mtype_cap" class="sref">mtype_cap2/a> = 2a href="+code=MEM_FLAG_EDO" class="sref">MEM_FLAG_EDO2/a> | 2a href="+code=MEM_FLAG_SDR" class="sref">MEM_FLAG_SDR2/a> | 2a href="+code=MEM_FLAG_RDR" class="sref">MEM_FLAG_RDR2/a>;".2642/a>        2a href="+code=mci" class="sref">mci2/a>->2a href="+code=edac_ctl_cap" class="sref">edac_ctl_cap2/a> = 2a href="+code=EDAC_FLAG_NONE" class="sref">EDAC_FLAG_NONE2/a> | 2a href="+code=EDAC_FLAG_EC" class="sref">EDAC_FLAG_EC2/a> | 2a href="+code=EDAC_FLAG_SECDED" class="sref">EDAC_FLAG_SECDED2/a>;".2652/a>        2a href="+code=pci_read_config_byte" class="sref">pci_read_config_byte2/a>(2a href="+code=pdev" class="sref">pdev2/a>,.2a href="+code=I82443BXGX_DRAMC" class="sref">I82443BXGX_DRAMC2/a>,.&2a href="+code=dramc" class="sref">dramc2/a>);".2662/a>        switch ((2a href="+code=dramc" class="sref">dramc2/a> >> 2a href="+code=I82443BXGX_DRAMC_OFFSET_DT" class="sref">I82443BXGX_DRAMC_OFFSET_DT2/a>) &.(2a href="+code=BIT" class="sref">BIT2/a>(0) | 2a href="+code=BIT" class="sref">BIT2/a>(1))) {".2672/a>        case 2a href="+code=I82443BXGX_DRAMC_DRAM_IS_EDO" class="sref">I82443BXGX_DRAMC_DRAM_IS_EDO2/a>:".2682/a>                2a href="+code=mtype" class="sref">mtype2/a> = 2a href="+code=MEM_EDO" class="sref">MEM_EDO2/a>;".2692/a>                break;".2702/a>        case 2a href="+code=I82443BXGX_DRAMC_DRAM_IS_SDRAM" class="sref">I82443BXGX_DRAMC_DRAM_IS_SDRAM2/a>:".2712/a>                2a href="+code=mtype" class="sref">mtype2/a> = 2a href="+code=MEM_SDR" class="sref">MEM_SDR2/a>;".2722/a>                break;".2732/a>        case 2a href="+code=I82443BXGX_DRAMC_DRAM_IS_RSDRAM" class="sref">I82443BXGX_DRAMC_DRAM_IS_RSDRAM2/a>:".2742/a>                2a href="+code=mtype" class="sref">mtype2/a> = 2a href="+code=MEM_RDR" class="sref">MEM_RDR2/a>;".2752/a>                break;".2762/a>        default:".2772/a>                2a href="+code=edac_dbg" class="sref">edac_dbg2/a>(0,.2spae class="string">"Unknown/reserved DRAM type value in DRAMC register!\n".2782/a>                2a href="+code=mtype" class="sref">mtype2/a> = -2a href="+code=MEM_UNKNOWN" class="sref">MEM_UNKNOWN2/a>;".2792/a>        }".2802/a>".2812/a>        if ((2a href="+code=mtype" class="sref">mtype2/a> == 2a href="+code=MEM_SDR" class="sref">MEM_SDR2/a>) || (2a href="+code=mtype" class="sref">mtype2/a> == 2a href="+code=MEM_RDR" class="sref">MEM_RDR2/a>))".2822/a>                2a href="+code=mci" class="sref">mci2/a>->2a href="+code=edac_cap" class="sref">edac_cap2/a> = 2a href="+code=mci" class="sref">mci2/a>->2a href="+code=edac_ctl_cap" class="sref">edac_ctl_cap2/a>;".2832/a>        else".2842/a>                2a href="+code=mci" class="sref">mci2/a>->2a href="+code=edac_cap" class="sref">edac_cap2/a> = 2a href="+code=EDAC_FLAG_NONE" class="sref">EDAC_FLAG_NONE2/a>;".2852/a>".2862/a>        2a href="+code=mci" class="sref">mci2/a>->2a href="+code=scrub_cap" class="sref">scrub_cap2/a> = 2a href="+code=SCRUB_FLAG_HW_SRC" class="sref">SCRUB_FLAG_HW_SRC2/a>;".2872/a>        2a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword2/a>(2a href="+code=pdev" class="sref">pdev2/a>,.2a href="+code=I82443BXGX_NBXCFG" class="sref">I82443BXGX_NBXCFG2/a>,.&2a href="+code=nbxcfg" class="sref">nbxcfg2/a>);".2882/a>        2a href="+code=ecc_mode" class="sref">ecc_mode2/a> = ((2a href="+code=nbxcfg" class="sref">nbxcfg2/a> >> 2a href="+code=I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY" class="sref">I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY2/a>) &".2892/a>                (2a href="+code=BIT" class="sref">BIT2/a>(0) | 2a href="+code=BIT" class="sref">BIT2/a>(1)));".2902/a>".2912/a>        2a href="+code=mci" class="sref">mci2/a>->2a href="+code=scrub_mode" class="sref">scrub_mode2/a> = (2a href="+code=ecc_mode" class="sref">ecc_mode2/a> == 2a href="+code=I82443BXGX_NBXCFG_INTEGRITY_SCRUB" class="sref">I82443BXGX_NBXCFG_INTEGRITY_SCRUB2/a>)".2922/a>                ? 2a href="+code=SCRUB_HW_SRC" class="sref">SCRUB_HW_SRC2/a> : 2a href="+code=SCRUB_NONE" class="sref">SCRUB_NONE2/a>;".2932/a>".2942/a>        switch (2a href="+code=ecc_mode" class="sref">ecc_mode2/a>) {".2952/a>        case 2a href="+code=I82443BXGX_NBXCFG_INTEGRITY_NONE" class="sref">I82443BXGX_NBXCFG_INTEGRITY_NONE2/a>:".2962/a>                2a href="+code=edac_mode" class="sref">edac_mode2/a> = 2a href="+code=EDAC_NONE" class="sref">EDAC_NONE2/a>;".2972/a>                break;".2982/a>        case 2a href="+code=I82443BXGX_NBXCFG_INTEGRITY_EC" class="sref">I82443BXGX_NBXCFG_INTEGRITY_EC2/a>:".2992/a>                2a href="+code=edac_mode" class="sref">edac_mode2/a> = 2a href="+code=EDAC_EC" class="sref">EDAC_EC2/a>;".3002/a>                break;".3012/a>        case 2a href="+code=I82443BXGX_NBXCFG_INTEGRITY_ECC" class="sref">I82443BXGX_NBXCFG_INTEGRITY_ECC2/a>:".3022/a>        case 2a href="+code=I82443BXGX_NBXCFG_INTEGRITY_SCRUB" class="sref">I82443BXGX_NBXCFG_INTEGRITY_SCRUB2/a>:".3032/a>                2a href="+code=edac_mode" class="sref">edac_mode2/a> = 2a href="+code=EDAC_SECDED" class="sref">EDAC_SECDED2/a>;".3042/a>                break;".3052/a>        default:".3062/a>                2a href="+code=edac_dbg" class="sref">edac_dbg2/a>(0,.2spae class="string">"Unknown/reserved ECC state in NBXCFG register!\n".3072/a>                2a href="+code=edac_mode" class="sref">edac_mode2/a> = 2a href="+code=EDAC_UNKNOWN" class="sref">EDAC_UNKNOWN2/a>;".3082/a>                break;".3092/a>        }".3102/a>".3112/a>        2a href="+code=i82443bxgx_inia_csrows" class="sref">i82443bxgx_inia_csrows2/a>(2a href="+code=mci" class="sref">mci2/a>,.2a href="+code=pdev" class="sref">pdev2/a>,.2a href="+code=edac_mode" class="sref">edac_mode2/a>,.2a href="+code=mtype" class="sref">mtype2/a>);".3122/a>".3132/a>        2spae class="comment">/* Many BIOSes don't clear error flags on boot, so do this2/spae=".3142/a>2spae class="comment">         * here, or we get "phantom" errors occurring at module-load2/spae=".3152/a>2spae class="comment">         * time. */2/spae=".3162/a>        2a href="+code=pci_write_bits32" class="sref">pci_write_bits322/a>(2a href="+code=pdev" class="sref">pdev2/a>,.2a href="+code=I82443BXGX_EAP" class="sref">I82443BXGX_EAP2/a>,".3172/a>                        (2a href="+code=I82443BXGX_EAP_OFFSET_SBE" class="sref">I82443BXGX_EAP_OFFSET_SBE2/a> |".3182/a>                                2a href="+code=I82443BXGX_EAP_OFFSET_MBE" class="sref">I82443BXGX_EAP_OFFSET_MBE2/a>),".3192/a>                        (2a href="+code=I82443BXGX_EAP_OFFSET_SBE" class="sref">I82443BXGX_EAP_OFFSET_SBE2/a> |".3202/a>                                2a href="+code=I82443BXGX_EAP_OFFSET_MBE" class="sref">I82443BXGX_EAP_OFFSET_MBE2/a>));".3212/a>".3222/a>        2a href="+code=mci" class="sref">mci2/a>->2a href="+code=mod_nam " class="sref">mod_nam 2/a> = 2a href="+code=EDAC_MOD_STR" class="sref">EDAC_MOD_STR2/a>;".3232/a>        2a href="+code=mci" class="sref">mci2/a>->2a href="+code=mod_ver" class="sref">mod_ver2/a> = 2a href="+code=I82443_REVISION" class="sref">I82443_REVISION2/a>;".3242/a>        2a href="+code=mci" class="sref">mci2/a>->2a href="+code=ctl_nam " class="sref">ctl_nam 2/a> = 2spae class="string">"I82443BXGX".3252/a>        2a href="+code=mci" class="sref">mci2/a>->2a href="+code=dev_nam " class="sref">dev_nam 2/a> = 2a href="+code=pci_nam " class="sref">pci_nam 2/a>(2a href="+code=pdev" class="sref">pdev2/a>);".3262/a>        2a href="+code=mci" class="sref">mci2/a>->2a href="+code=edac_check" class="sref">edac_check2/a> = 2a href="+code=i82443bxgx_edacmc_check" class="sref">i82443bxgx_edacmc_check2/a>;".3272/a>        2a href="+code=mci" class="sref">mci2/a>->2a href="+code=ctl_page_to_phys" class="sref">ctl_page_to_phys2/a> = 2a href="+code=NULL" class="sref">NULL2/a>;".3282/a>".3292/a>        if (2a href="+code=edac_mc_add_mc" class="sref">edac_mc_add_mc2/a>(2a href="+code=mci" class="sref">mci2/a>)) {".3302/a>                2a href="+code=edac_dbg" class="sref">edac_dbg2/a>(3,.2spae class="string">"failed edac_mc_add_mc()\n".3312/a>                goto 2a href="+code=fail" class="sref">fail2/a>;".3322/a>        }".3332/a>".3342/a>        2spae class="comment">/* allocating generic PCI control info */2/spae=".3352/a>        2a href="+code=i82443bxgx_pci" class="sref">i82443bxgx_pci2/a> = 2a href="+code=edac_pci_create_generic_ctl" class="sref">edac_pci_create_generic_ctl2/a>(&2a href="+code=pdev" class="sref">pdev2/a>->2a href="+code=dev" class="sref">dev2/a>,.2a href="+code=EDAC_MOD_STR" class="sref">EDAC_MOD_STR2/a>);".3362/a>        if (!2a href="+code=i82443bxgx_pci" class="sref">i82443bxgx_pci2/a>) {".3372/a>                2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_WARNING" class="sref">KERN_WARNING2/a>".3382/a>                        2spae class="string">"%s(): Unable to create PCI control\n".3392/a>                        2a href="+code=__func__" class="sref">__func__2/a>);".3402/a>                2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_WARNING" class="sref">KERN_WARNING2/a>".3412/a>                        2spae class="string">"%s(): PCI error report via EDAC not setup\n".3422/a>                        2a href="+code=__func__" class="sref">__func__2/a>);".3432/a>        e=);"2L244" class="line"3Y_NONtv2L3">92ype2/a> = 2a href="+code=MEM_EDO" class="sref">22a href="+code=MEM_EDO" class="sref">2mci2/a>->2a href)C)".2463/a>2spae class="comment"3     3482443bxgx_pciss="srex_edac.c#L199" idv2L199" class="line" nam v23247">.2473/a>2spae class="comment"3     3   */2edac.c#L199" idv2L199" class="line" nam v23238">.3382/a>        if (2a href="3code=3ci_reafail2/a>;".2493/a>                retur3 -2a 3ref="+code=EIOss="sref">edac_mc_add_mfrehref="+code=mtype" cla_mfrehef">mci2/a>)) {".2503/a>"ENOMEM2/a>;".2513/a>        2a href="+cod3=laye3s" claxgx_edac.c44" idv2L3" idv2L244" class="line"252">.2523/a>        2a href="+cod3=laye35bxgx_edac.c#L313" idv2L313" class="line" nam v2L253">.2533/a>        2a href="+cod3=laye3s" cla">ENOMEM2/a>;";"mci2/a>)) {"        2a href="+cod3=laye35L3">92ype2/a> = 2a href="+code=MEM_EDO" class="s255">.2553/a>        2a href="+cod3=laye35  * time. */2/spae="d= 0)rors neg/spvef="dquot;<2443bxgx_edac.c#L335" idv2L335" class="line" nam v2L256">.2563/a>        2a href="+cod3=laye3s" clagx_edacmc_probe1" class="sref">i82443bxgx_ed" claonhref="+code=mtypref">i82443bxgx_ed" claonhef">mss="sref">pci_dev2/a> *2a href="+code=pdev" class="sref">pdev2/a>, int.2a href="+code=dev_idx" classedac.c#L335" idv2L335" class="line" nam v2L247">.2473/a>        2a href="+cod3=mci"35ref="+code=I82443BXGX_EAP_OFFFFFFFFFFFFFFFFrivster" class="sref">edac_mclass="ice_iord2/a>(2a href="+cos="ice_iosref">pdev2/a>, int.2 hreef="+code=mtypen3bxgx_edac.c#L218" idv2L218" class="line" nam v23258">.2583/a>        if (2a href="3code=3ci" cl_edac.c#L337" idv2L337" class="line" nam v2L259">.2593/a>                retur3 -2a 3ref="+code=ENOmc_probe1" class="sr(2a href="+code=r3bxgx_edac.c#L239" idv2L239" class="line" nam v23260">.2603/a>".2613/a>        2a href="+cod3=edac3dbg" class="sref">edac_dbg2/a>(0,.2spae class="string">"MC: mci = %p\n".2623/a>        2a href="+cod3=mci"36bxgx_edac.c#L313" idv2L313" class="line" nam v2L263">.2633/a>        2a href="+cod3=mci"36>/* Many BIOSes don't clear error t, so do tneedae=,"f="d"+coe;.2643/a>        2a href="+cod3=mci"3class="sref">mci2/a>->2a hr(2a href="+code=r3bxgxc_check" class="sref">i82443bxgx_edaacmc_probe12/a>(struct.2a href="+code=pci_dev" clapdev2/a>,.2a href="+code=edac_mode" class="sref">edac_mode2/hreef="+code=mtypen3bxgxef">dev2/a>,.2a href=" idv_datacode=EDAC_MOD_ST" idv_data" clx_edac.c#L199" idv2L199" class="line" nam v23265">.2653/a>        2a href="+cod3=pci_36bxgx_edac.c#L286" idv2L286" class="line" nam v23266">.2663/a>        switch ((2a h3ef="+3682443bxgx_pci" clci2/a>)) {"NULL2/a>)".2673/a>        case 2a href=3+code36e=printk" class="sref">printk2/a>(2aref_ef="+code=edac_moderef_ef="bxgxc_ss="sref">edac_mclass="_gereef="+code=mtypclass="_gerref">pdev2/a>);".2683/a>                2a hr3f="+c36bxgx_edac.c#L329" idv2L329" class="line" nam v2L269">.2693/a>                break3".2703/a>        case 2a href=3+code3I82443xgx_edac.c44" idv2L3" idv2L244" class="line"271">.2713/a>                2a hr3f="+c37bxgx_edac.c#L322" idv2L322" class="line" nam v2L272">.2723/a>                break3"i82443bxgx_edaremoveaonhref="+code=mtypref">i82443bxgx_edremoveaonhef">mss="sref">pci_dev2/a> *2a href="+code=pdev" class="sref">pdev2/a>, int.2a href="+code=dev_idx" clas_edac.c#L259" idv2L259" class="line" nam v23273">.2733/a>        case 2a href=3+code3I82443_edac.c#L337" idv2L337" class="line" nam v2L274">.2743/a>                2a hr3f="+c3de=mtype" clas" class="sref">mem_ctl_info2/a> *2a href="+code=mci" class="sref">mci2/a>;".2753/a>                break3".2763/a>        default:"mci2/a>->2a h>(0,.2spae class="string">"MC: mci = %p\n".2773/a>                2a hr3f="+c37  */2edac.c#L199" idv2L199" class="line" nam v23278">.2783/a>                2a hr3f="+c37i" class="sref">mci2/a> == 2a hr3bxgx_pci2/a>) {".2693/a>        }"edac_mode2/a> ="+codeleasci_create_generic_ctl2/a>(&2a hredeleasci_create_genef">mci2/a>)) {".2803/a>".2813/a>        if ((2a href=3+code3mtype" class="sref">mtype2/a> == 2a="+code=edac_mc_alloc" class="sref">edac_mc_alloc2dela>(2a href="+code=mci" cladela>(ss="sref">pdev2/a>->2a href="+code=dev" class="sref">dev2/a>,.2a href="+code=EDAC_MOD_STR" cla))c_">NULL2/a>)".2823/a>                2a hr3f="+c3de=mci" class="sref">mss="sr_edac.c#L331" idv2L331" class="line" nam v2L273">.2733/a>        else".2843/a>                2a hr3f="+c38lass="sref">mci2/a>->2a hmc_add_mfrehref="+code=mtype" cla_mfrehef">mci2/a>)) {".2853/a>".2863/a>        2a href="+cod3=mci"3class=gx_edac.c44" idv2L3" idv2L244" class="line"277">.2773/a>        2a href="+cod3=pci_3ead_co">ENOMEM2/a>;";"mci2/a>)) {"i82443bxgx_edremoveaonhef">x_edac.c#L199" idv2L199" class="line" nam v23278">.2783/a>        2a href="+cod3=ecc_38bxgx_edac.c#L329" idv2L329" class="line" nam v2L289">.2893/a>                (2a h3ef="+3ode=BIgx_edacci2/a>)) {"));"mci2/a>)) {")_tbn43bxgx=x_edac.c#L337" idv2L337" class="line" nam v2L290">.2903/a>"(&aPCI_DEVICEef">mci2/a>)) {";"edac_mode2PCI_DEVICE_IDvers/N_rivers/_0eric_ctl2/a>(&aPCI_DEVICE_IDvers/N_rivers/_043bxg}sedac.c#L335" idv2L335" class="line" nam v2L291">.2913/a>        2a href="+cod3=mci"3class="sref">m{ci2/a>)) {"(&aPCI_DEVICEef">mci2/a>)) {";"edac_mode2PCI_DEVICE_IDvers/N_rivers/_a>(2a href="+codPCI_DEVICE_IDvers/N_rivers/_a43bxg}sedac.c#L335" idv2L335" class="line" nam v2L282">.2823/a>                ? 2a 3ref="3code=SCRUB_HW_{ci2/a>)) {"(&aPCI_DEVICEef">mci2/a>)) {";"edac_mode2PCI_DEVICE_IDvers/N_riverG/_0eric_ctl2/a>(&aPCI_DEVICE_IDvers/N_riverG/_043bxg}sedac.c#L335" idv2L335" class="line" nam v2L273">.2733/a>"(&aPCI_DEVICEef">mci2/a>)) {";"edac_mode2PCI_DEVICE_IDvers/N_riverG/_a>(2a href="+codPCI_DEVICE_IDvers/N_riverG/_a43bxg}sedac.c#L335" idv2L335" class="line" nam v2L284">.2843/a>        switch (2a hr3f="+c3de=ecc_mode" c{0,}" class="sref">mf">mcs don't clear error 0 terminated listi82443bxgx_edac.c#L316" idv2L316" class="line" nam v2L295">.2953/a>        case 2a href=3+code3I82443}_edac.c#L199" idv2L199" class="line" nam v23296">.2963/a>                2a hr3f="+c39lass=gx_edac.c44" idv2L3" idv2L244" class="line"297">.2973/a>                break3"ENOMEM2/a>;"));"pdev2/a>);"pdev2/a>,.2a href="driversa>)_tbneric_ctl2/a>(&aef="driversa>)_tbn43bxg_edac.c#L199" idv2L199" class="line" nam v23278">.2783/a>        case 2a href=3+code39bxgx_edac.c#L329" idv2L329" class="line" nam v2L299">.2993/a>                2a hr3f="+c39de=BIgx_edacss="sref">pci_dev2/a> *2a h" idvf="+code=pdev" class" idv=ecc_ci2/a>)) {".3004/a>                break4"is_vir href="+code=pdev" _STR" class="sref">EDAC_MOD_STR2/a>;".3014/a>        case 2a href=4+code4I82443BXGX_NBXss="sref">is_virci_de"+code=KERN_WARNI_debxgxc_check" class="sref">i82443bxgx_eda" claonhref="+code=mtypref">i82443bxgx_ed" claonhef">sedac.c#L335" idv2L335" class="line" nam v24321">.3014/a>                ? 2a 4+code4I82443BXGX_NBXss="sref">is_virremove2a href="+code=removebxgxc_check" class="sref">i82443bxgx_edaremoveaonhref="+code=mtypref">i82443bxgx_edremoveaonhef">sedac.c#L335" idv2L335" class="line" nam v24331">.3014/a>"is_virad_ti82443ba>)_tbneric_ctl2/a>(&aef="driversa>)_tbn43bxsedac.c#L335" idv2L335" class="line" nam v24341">.3014/a>        switch (2a hr4".3054/a>        default:".3064/a>                2a hr4f="+c40" clagx_edacmc_probe1" class="s_d" cleric_ctl2/a>(&a_d" cl=ecc_ci2/a>)) {"(&aef="drivers/edac/i" clref">void_edac.c#L259" idv2L259" class="line" nam v24307">.3074/a>                2a hr4f="+c4de=eda_edac.c#L337" idv2L337" class="line" nam v24387">.3074/a>        case 2a href=4".3094/a>        }".3104/a>"(&aop/spaei" clref">g_edac.c#L199" idv2L199" class="line" nam v24311">.3114/a>        2a href="+cod4=i82441bxgx_edac.c#L322" idv2L322" class="line" nam v24312">.3124/a>"mci2/a>->2a h hred(2a href="+code= hred(bxgxc_ss="sref">edac_mclas="driver h" idvf="+code=pdev" clas="driver h" idvss="sref">pdev2/a>->2aef="drivers/edac/ih" idvf="+code=pdev" ef="drivers/edac/ih" idvc" cg_edac.c#L199" idv2L199" class="line" nam v24331">.3014/a>        2spae class="4ommen4">/* Many BIOS_dword" class="sref">pci(2a href="+code= hred(bxgxc< 0_edac.c#L259" idv2L259" class="line" nam v24314">.3144/a>2spae class="comment"4     41f="drivers/edac/i8244ref">fail2/a>;".3154/a>2spae class="comment"4     41bxgx_edac.c#L286" idv2L286" class="line" nam v24316">.3164/a>        2a href="+cod4=pci_4182443bxgx_pci" clci2/a>)) {"NULL2/a>)".3174/a>                     4  (2a4href="+code=I82443BXGXrivster" class="sref">edac_mclass="ice_iord2/a>(2a href="+cos="ice_iosref">pdev2/a>, int.2iord2/a>(2a href=iosref""sref">pdev2/a>->2aef">i82443ba>)_tbneric_ctl2/a>(&aef="driversa>)_tbn43bx[0]_edac.c#L237" idv2L237" class="line" nam v24387">.3074/a>                     4     4    2a href="+code=I82mc_probe1" class="sreric_ctl2/a>(&aesref""sx_edac.c#L199" idv2L199" class="line" nam v24319">.3194/a>                     4  (2a4href="+code=I82443BXGXpdev2/a>->2aef">i82443b="drivereord2/a>(2a href=if">i82443b="drivereosref""sx_edac.c#L199" idv2L199" class="line" nam v24320">.3204/a>                     4     42bxgx_edac.c#L281" idv2L281" class="line" nam v24321">.3214/a>""whileclci2/a>)) {"NULL2/a>)"sref">pdev2/a>, int.2iord2/a>(2a href=iosrefef">dev2/a>,.2a hrefvendovf="+code=pdev" vendovbxgxs!= 0)s_edac.c#L337" idv2L337" class="line" nam v24322">.3224/a>        2a href="+cod4=mci"42ef="+code=__func__" class="sref">__func__2/aref_ef="+code=edac_moderef_ef="bxgxc_ss="sref">edac_mclasgetos="icerd2/a>(2a href="+cogetos="iceef">mci2/a>)) {"(2a href=iosrefef">dev2/a>,.2a hrefvendovf="+code=pdev" vendovbxgxsedac.c#L335" idv2L335" class="line" nam v24323">.3234/a>        2a href="+cod4=mci"42e=edac_mode" class="scode=__func__" class="sref">__func__2/aeord2/a>(2a href=iosrefef">dev2/a>,.2a hrefs="icerd2/a>(2a href=s="iceef">">pdev2/a>,.2a href="drivers/edac/i82443bxgx__edac.c#L199" idv2L199" class="line" nam v24314">.3144/a>        2a href="+cod4=mci"42f="drivers/edac/i8244lass="sref">__func__2/aeeric_ctl2/a>(&aesref++_edac.c#L199" idv2L199" class="line" nam v24315">.3154/a>        2a href="+cod4=mci"4class="sref">munc__" class="sref">__func__2/aeord2/a>(2a href=iosref""sref">pdev2/a>->2aef">i82443ba>)_tbneric_ctl2/a>(&aef="driversa>)_tbn43bx[ef">__func__2/aeeric_ctl2/a>(&aesref]_edac.c#L237" idv2L237" class="line" nam v24326">.3264/a>        2a href="+cod4=mci"42e=edac_dbg" class="srxgx_edac.c44" idv2L3" idv2L244" class="line4327">.3274/a>        2a href="+cod4=mci"42ref="+code=I82443BXGX" class="sref">i8244ref_ef="+code=edac_moderef_ef="bxgx)s_edac.c#L337" idv2L337" class="line" nam v24387">.3074/a>""%s()i2/a>->2a h>(0,.2spae class="string">"MC: mci = %p\n".3294/a>        if (2a href="4code=42ef="+code=__func__" class="sref">__func__2/a hred(2a href="+code= hred(bxgxc_sf">ENOMEM2/a>;".3304/a>                2a hr4f="+c4de=edac_dbg" class="srrrrrrrrrref">fail2/a>;".3214/a>                goto 4a hre4="+code=fail" class="sxgx_edac.c44" idv2L3" idv2L244" class="line4332">.3324/a>        }".3334/a>"edac_mode2 hred(2a href="+code= hred(bxgxc_ss="sref">edac_mref">i82443bxgx_ed" claonhref="+code=mtypref">i82443bxgx_ed" claonhef">mss="sref">i8244ref_ef="+code=edac_moderef_ef="bxgx">pdev2/a>,.2a href="driversa>)_tbneric_ctl2/a>(&aef="driversa>)_tbn43bxg_edac.c#L199" idv2L199" class="line" nam v24334">.3344/a>        2spae class="4ommen43L3">92ype2/a> = 2a href="+code=MEM_EDO" class="4335">.3354/a>        2a href="+cod4=i82443lass="sref">munc__" c_dword" class="sref">pci(2a href="+code= hred(bxgxc< 0_s_edac.c#L337" idv2L337" class="line" nam v24336">.3364/a>        if (!2a href=4+code43e=edac_dbg" class="sr;%s()i2/a>->2a h>(0,.2spae class="string">"MC: mci = %p\n".3374/a>                2a hr4f="+c4de=printk" class="sreflass="sref">__func__2/a hred(2a href="+code= hred(bxgxc_sf">ENOMEM2/a>;".3074/a>                     4  2sp4e class="string">"%s(ref">fail2/a>;".3294/a>                     4  2a 4ref="+code=__func__" cxgx_edac.c44" idv2L3" idv2L244" class="line4340">.3404/a>                2a hr4f="+c4de=printk" claxgx_edac.c44" idv2L3" idv2L244" class="line4321">.3214/a>                     4  2sp44bxgx_edac.c#L322" idv2L322" class="line" nam v24432">.33244a>        }".3434/a>        e=);"2L244" class="line"34_NONt42L3">9fail2/a>;"22a 4ref="+code=MEM_EDO" clas4="sre4">2mci2/a>->2a href)C)"pdev2/a>->2aef="drivers/edac/ih" idvf="+code=pdev" ef="drivers/edac/ih" idvc" cg_edac.c#L199" idv2L199" class="line" nam v24246">.2464/a>2spae class="comment"4     44lass=gx_edac.c44" idv2L3" idv2L244" class="line4247">.2474/a>2spae class="comment"4     44ad_co">ENOMEM2/a>;"(&aef="0bxgx_edac.c#L306" idv2L306" class="line" nam v24r87">.3074/a>        if (2a href="4code=44i" class="sref">mci2/a> == 2a hrref_ef="+code=edac_moderef_ef="bxgxc!">NULL2/a>)".2494/a>                retur4 -2a 44ref="+code=I82443BXGXpdev2/a>->2aclass="_pureef="+code=mtypclass="_puref">mss="sref">i8244ref_ef="+code=edac_moderef_ef="bxgxg_edac.c#L199" idv2L199" class="line" nam v24250">.2504/a>".2514/a>        2a href="+cod4=laye451f="+code=__fss="srerobe1" class="s hred(2a href="+code= hred(bxgx_edac.c#L237" idv2L237" class="line" nam v24252">.2524/a>        2a href="+cod4=laye45bxgx_xgx_edac.c44" idv2L3" idv2L244" class="line4253">.2534/a>        2a href="+cod4=laye45bxgx_edac.c#L334" idv2L334" class="line" nam v242Y_NONtv24/a>        2a href="+cod4=laye45L3">9gx_edacvoidcheck" class="sr__excleric_ctl2/a>(&a_dexcl=ecc_ci2/a>)) {"void_edac.c#L259" idv2L259" class="line" nam v24255">.2554/a>        2a href="+cod4=laye45  * t_edac.c#L337" idv2L337" class="line" nam v24256">.2564/a>        2a href="+cod4=laye45ite_bits32" class="sref">pci_wriun="driver h" idvf="+code=pdev" clasun="driver h" idvss="sref">pdev2/a>->2aef="drivers/edac/ih" idvf="+code=pdev" ef="drivers/edac/ih" idvc" cg_edac.c#L199" idv2L199" class="line" nam v24247">.2474/a>        2a href="+cod4=mci"45  */2edac.c#L199" idv2L199" class="line" nam v24258">.2584/a>        if (2a href="4code=45i" class="sref">mass="sref">i82443bxgx_pci2/="drivereord2/a>(2a href=if">i82443b="drivereosref_edac.c#L259" idv2L259" class="line" nam v24249">.2494/a>                retur4 -2a 45ref="+code=I82443BXGXpdev2/a>->2aef">i82443b/edac/iremoveaonhref="+code=mtypref">i82443bxgx_edremoveaonhef">mss="sref">i8244ref_ef="+code=edac_moderef_ef="bxgxg_edac.c#L199" idv2L199" class="line" nam v24260">.2604/a>".2614/a>        2a href="+cod4=edac46type" class="srefss="sref">i8244ref_ef="+code=edac_moderef_ef="bxgxgedac.c#L261" idv2L261" class="line" nam v24252">.2524/a>        2a href="+cod4=mci"46e=mci" class="sref">mci2/a>->2a hclass="_pureef="+code=mtypclass="_puref">mss="sref">i8244ref_ef="+code=edac_moderef_ef="bxgxg_edac.c#L199" idv2L199" class="line" nam v24263">.2634/a>        2a href="+cod4=mci"46>/* Mxgx_edac.c44" idv2L3" idv2L244" class="line4264">.2644/a>        2a href="+cod4=mci"46L3">92ype2/a> = 2a href="+code=MEM_EDO" class="4265">.2654/a>        2a href="+cod4=pci_46bxgx_ss="sref">i8244r/edaci" cleric_ctl2/a>(&ar/edaci" clef">mci2/a>)) {"(&aef="drivers/edac/i" clref"g_edac.c#L199" idv2L199" class="line" nam v24256">.2564/a>        switch ((2a h4ef="+4682443ss="sref">i8244r/edaciexcleric_ctl2/a>(&ar/edaciexclef">mci2/a>)) {".2474/a>        case 2a href=4+code46  */2edac.c#L199" idv2L199" class="line" nam v24268">.2684/a>                2a hr4f="+c46i_reafail2/a>;"));"mc= %p\n".2694/a>                break4"mc= %p\n".2704/a>        case 2a href=4+code4I82443fail2/a>;";"mc= %p\n".2614/a>                2a hr4f="+c47bxgx_edac.c#L322" idv2L322" class="line" nam v24272">.2724/a>                break4"i8244r/edaciparameric_ctl2/a>(&ar/edaciparamef">mci2/a>)) {"&qop_/spaeae class="string">&qop_/spaebxgx">int, 0444x_edac.c#L331" idv2L331" class="line" nam v24263">.2634/a>        case 2a href=4+code47" cla">ENOMEM2/a>;"mci2/a>)) {"&qop_/spaeae class="string">&qop_/spaebxgx">c= %p\n".2644/a>                2a hr4f="+c4de=mty


The original LXR software by"LXR cleau clybxgx">i824 experiar eal idv2i="dryhdac.c#L33mailto:lxr@ ux.no">lxr@ ux.nobxgx.
lxr. ux.no kindly hosted ryhdac.c#L33http://www.reopill- pro.no">Reopill L pro ASbxgx">provider of L uxXrivsul=pae=and oper_edivs r!\nices rince 1995.