linux/drivers/dma/coh901318.c
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   1/*
   2 * driver/dma/coh901318.c
   3 *
   4 * Copyright (C) 2007-2009 ST-Ericsson
   5 * License terms: GNU General Public License (GPL) version 2
   6 * DMA driver for COH 901 318
   7 * Author: Per Friden <per.friden@stericsson.com>
   8 */
   9
  10#include <linux/init.h>
  11#include <linux/module.h>
  12#include <linux/kernel.h> /* printk() */
  13#include <linux/fs.h> /* everything... */
  14#include <linux/scatterlist.h>
  15#include <linux/slab.h> /* kmalloc() */
  16#include <linux/dmaengine.h>
  17#include <linux/platform_device.h>
  18#include <linux/device.h>
  19#include <linux/irqreturn.h>
  20#include <linux/interrupt.h>
  21#include <linux/io.h>
  22#include <linux/uaccess.h>
  23#include <linux/debugfs.h>
  24#include <linux/platform_data/dma-coh901318.h>
  25#include <linux/of_dma.h>
  26
  27#include "coh901318.h"
  28#include "dmaengine.h"
  29
  30#define COH901318_MOD32_MASK                                    (0x1F)
  31#define COH901318_WORD_MASK                                     (0xFFFFFFFF)
  32/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
  33#define COH901318_INT_STATUS1                                   (0x0000)
  34#define COH901318_INT_STATUS2                                   (0x0004)
  35/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
  36#define COH901318_TC_INT_STATUS1                                (0x0008)
  37#define COH901318_TC_INT_STATUS2                                (0x000C)
  38/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
  39#define COH901318_TC_INT_CLEAR1                                 (0x0010)
  40#define COH901318_TC_INT_CLEAR2                                 (0x0014)
  41/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
  42#define COH901318_RAW_TC_INT_STATUS1                            (0x0018)
  43#define COH901318_RAW_TC_INT_STATUS2                            (0x001C)
  44/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
  45#define COH901318_BE_INT_STATUS1                                (0x0020)
  46#define COH901318_BE_INT_STATUS2                                (0x0024)
  47/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
  48#define COH901318_BE_INT_CLEAR1                                 (0x0028)
  49#define COH901318_BE_INT_CLEAR2                                 (0x002C)
  50/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
  51#define COH901318_RAW_BE_INT_STATUS1                            (0x0030)
  52#define COH901318_RAW_BE_INT_STATUS2                            (0x0034)
  53
  54/*
  55 * CX_CFG - Channel Configuration Registers 32bit (R/W)
  56 */
  57#define COH901318_CX_CFG                                        (0x0100)
  58#define COH901318_CX_CFG_SPACING                                (0x04)
  59/* Channel enable activates tha dma job */
  60#define COH901318_CX_CFG_CH_ENABLE                              (0x00000001)
  61#define COH901318_CX_CFG_CH_DISABLE                             (0x00000000)
  62/* Request Mode */
  63#define COH901318_CX_CFG_RM_MASK                                (0x00000006)
  64#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY                    (0x0 << 1)
  65#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY                   (0x1 << 1)
  66#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY                   (0x1 << 1)
  67#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY                (0x3 << 1)
  68#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY                (0x3 << 1)
  69/* Linked channel request field. RM must == 11 */
  70#define COH901318_CX_CFG_LCRF_SHIFT                             3
  71#define COH901318_CX_CFG_LCRF_MASK                              (0x000001F8)
  72#define COH901318_CX_CFG_LCR_DISABLE                            (0x00000000)
  73/* Terminal Counter Interrupt Request Mask */
  74#define COH901318_CX_CFG_TC_IRQ_ENABLE                          (0x00000200)
  75#define COH901318_CX_CFG_TC_IRQ_DISABLE                         (0x00000000)
  76/* Bus Error interrupt Mask */
  77#define COH901318_CX_CFG_BE_IRQ_ENABLE                          (0x00000400)
  78#define COH901318_CX_CFG_BE_IRQ_DISABLE                         (0x00000000)
  79
  80/*
  81 * CX_STAT - Channel Status Registers 32bit (R/-)
  82 */
  83#define COH901318_CX_STAT                                       (0x0200)
  84#define COH901318_CX_STAT_SPACING                               (0x04)
  85#define COH901318_CX_STAT_RBE_IRQ_IND                           (0x00000008)
  86#define COH901318_CX_STAT_RTC_IRQ_IND                           (0x00000004)
  87#define COH901318_CX_STAT_ACTIVE                                (0x00000002)
  88#define COH901318_CX_STAT_ENABLED                               (0x00000001)
  89
  90/*
  91 * CX_CTRL - Channel Control Registers 32bit (R/W)
  92 */
  93#define COH901318_CX_CTRL                                       (0x0400)
  94#define COH901318_CX_CTRL_SPACING                               (0x10)
  95/* Transfer Count Enable */
  96#define COH901318_CX_CTRL_TC_ENABLE                             (0x00001000)
  97#define COH901318_CX_CTRL_TC_DISABLE                            (0x00000000)
  98/* Transfer Count Value 0 - 4095 */
  99#define COH901318_CX_CTRL_TC_VALUE_MASK                         (0x00000FFF)
 100/* Burst count */
 101#define COH901318_CX_CTRL_BURST_COUNT_MASK                      (0x0000E000)
 102#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES                  (0x7 << 13)
 103#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES                  (0x6 << 13)
 104#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES                  (0x5 << 13)
 105#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES                  (0x4 << 13)
 106#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES                   (0x3 << 13)
 107#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES                   (0x2 << 13)
 108#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES                   (0x1 << 13)
 109#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE                    (0x0 << 13)
 110/* Source bus size  */
 111#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK                     (0x00030000)
 112#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS                  (0x2 << 16)
 113#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS                  (0x1 << 16)
 114#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS                   (0x0 << 16)
 115/* Source address increment */
 116#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE                   (0x00040000)
 117#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE                  (0x00000000)
 118/* Destination Bus Size */
 119#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK                     (0x00180000)
 120#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS                  (0x2 << 19)
 121#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS                  (0x1 << 19)
 122#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS                   (0x0 << 19)
 123/* Destination address increment */
 124#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE                   (0x00200000)
 125#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE                  (0x00000000)
 126/* Master Mode (Master2 is only connected to MSL) */
 127#define COH901318_CX_CTRL_MASTER_MODE_MASK                      (0x00C00000)
 128#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W                   (0x3 << 22)
 129#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W                   (0x2 << 22)
 130#define COH901318_CX_CTRL_MASTER_MODE_M2RW                      (0x1 << 22)
 131#define COH901318_CX_CTRL_MASTER_MODE_M1RW                      (0x0 << 22)
 132/* Terminal Count flag to PER enable */
 133#define COH901318_CX_CTRL_TCP_ENABLE                            (0x01000000)
 134#define COH901318_CX_CTRL_TCP_DISABLE                           (0x00000000)
 135/* Terminal Count flags to CPU enable */
 136#define COH901318_CX_CTRL_TC_IRQ_ENABLE                         (0x02000000)
 137#define COH901318_CX_CTRL_TC_IRQ_DISABLE                        (0x00000000)
 138/* Hand shake to peripheral */
 139#define COH901318_CX_CTRL_HSP_ENABLE                            (0x04000000)
 140#define COH901318_CX_CTRL_HSP_DISABLE                           (0x00000000)
 141#define COH901318_CX_CTRL_HSS_ENABLE                            (0x08000000)
 142#define COH901318_CX_CTRL_HSS_DISABLE                           (0x00000000)
 143/* DMA mode */
 144#define COH901318_CX_CTRL_DDMA_MASK                             (0x30000000)
 145#define COH901318_CX_CTRL_DDMA_LEGACY                           (0x0 << 28)
 146#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1                      (0x1 << 28)
 147#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2                      (0x2 << 28)
 148/* Primary Request Data Destination */
 149#define COH901318_CX_CTRL_PRDD_MASK                             (0x40000000)
 150#define COH901318_CX_CTRL_PRDD_DEST                             (0x1 << 30)
 151#define COH901318_CX_CTRL_PRDD_SOURCE                           (0x0 << 30)
 152
 153/*
 154 * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
 155 */
 156#define COH901318_CX_SRC_ADDR                                   (0x0404)
 157#define COH901318_CX_SRC_ADDR_SPACING                           (0x10)
 158
 159/*
 160 * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
 161 */
 162#define COH901318_CX_DST_ADDR                                   (0x0408)
 163#define COH901318_CX_DST_ADDR_SPACING                           (0x10)
 164
 165/*
 166 * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
 167 */
 168#define COH901318_CX_LNK_ADDR                                   (0x040C)
 169#define COH901318_CX_LNK_ADDR_SPACING                           (0x10)
 170#define COH901318_CX_LNK_LINK_IMMEDIATE                         (0x00000001)
 171
 172/**
 173 * struct coh901318_params - parameters for DMAC configuration
 174 * @config: DMA config register
 175 * @ctrl_lli_last: DMA control register for the last lli in the list
 176 * @ctrl_lli: DMA control register for an lli
 177 * @ctrl_lli_chained: DMA control register for a chained lli
 178 */
 179struct coh901318_params {
 180        u32 config;
 181        u32 ctrl_lli_last;
 182        u32 ctrl_lli;
 183        u32 ctrl_lli_chained;
 184};
 185
 186/**
 187 * struct coh_dma_channel - dma channel base
 188 * @name: ascii name of dma channel
 189 * @number: channel id number
 190 * @desc_nbr_max: number of preallocated descriptors
 191 * @priority_high: prio of channel, 0 low otherwise high.
 192 * @param: configuration parameters
 193 */
 194struct coh_dma_channel {
 195        const char name[32];
 196        const int number;
 197        const int desc_nbr_max;
 198        const int priority_high;
 199        const struct coh901318_params param;
 200};
 201
 202/**
 203 * struct powersave - DMA power save structure
 204 * @lock: lock protecting data in this struct
 205 * @started_channels: bit mask indicating active dma channels
 206 */
 207struct powersave {
 208        spinlock_t lock;
 209        u64 started_channels;
 210};
 211
 212/* points out all dma slave channels.
 213 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 214 * Select all channels from A to B, end of list is marked with -1,-1
 215 */
 216static int dma_slave_channels[] = {
 217        U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
 218        U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
 219
 220/* points out all dma memcpy channels. */
 221static int dma_memcpy_channels[] = {
 222        U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 223
 224#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
 225                        COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
 226                        COH901318_CX_CFG_LCR_DISABLE | \
 227                        COH901318_CX_CFG_TC_IRQ_ENABLE | \
 228                        COH901318_CX_CFG_BE_IRQ_ENABLE)
 229#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
 230                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 231                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 232                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 233                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 234                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 235                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 236                        COH901318_CX_CTRL_TCP_DISABLE | \
 237                        COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 238                        COH901318_CX_CTRL_HSP_DISABLE | \
 239                        COH901318_CX_CTRL_HSS_DISABLE | \
 240                        COH901318_CX_CTRL_DDMA_LEGACY | \
 241                        COH901318_CX_CTRL_PRDD_SOURCE)
 242#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
 243                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 244                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 245                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 246                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 247                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 248                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 249                        COH901318_CX_CTRL_TCP_DISABLE | \
 250                        COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 251                        COH901318_CX_CTRL_HSP_DISABLE | \
 252                        COH901318_CX_CTRL_HSS_DISABLE | \
 253                        COH901318_CX_CTRL_DDMA_LEGACY | \
 254                        COH901318_CX_CTRL_PRDD_SOURCE)
 255#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
 256                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 257                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 258                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 259                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 260                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 261                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 262                        COH901318_CX_CTRL_TCP_DISABLE | \
 263                        COH901318_CX_CTRL_TC_IRQ_ENABLE | \
 264                        COH901318_CX_CTRL_HSP_DISABLE | \
 265                        COH901318_CX_CTRL_HSS_DISABLE | \
 266                        COH901318_CX_CTRL_DDMA_LEGACY | \
 267                        COH901318_CX_CTRL_PRDD_SOURCE)
 268
 269const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 270        {
 271                .number = U300_DMA_MSL_TX_0,
 272                .name = "MSL TX 0",
 273                .priority_high = 0,
 274        },
 275        {
 276                .number = U300_DMA_MSL_TX_1,
 277                .name = "MSL TX 1",
 278                .priority_high = 0,
 279                .param.config = COH901318_CX_CFG_CH_DISABLE |
 280                                COH901318_CX_CFG_LCR_DISABLE |
 281                                COH901318_CX_CFG_TC_IRQ_ENABLE |
 282                                COH901318_CX_CFG_BE_IRQ_ENABLE,
 283                .param.ctrl_lli_chained = 0 |
 284                                COH901318_CX_CTRL_TC_ENABLE |
 285                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 286                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 287                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 288                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 289                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 290                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 291                                COH901318_CX_CTRL_TCP_DISABLE |
 292                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 293                                COH901318_CX_CTRL_HSP_ENABLE |
 294                                COH901318_CX_CTRL_HSS_DISABLE |
 295                                COH901318_CX_CTRL_DDMA_LEGACY |
 296                                COH901318_CX_CTRL_PRDD_SOURCE,
 297                .param.ctrl_lli = 0 |
 298                                COH901318_CX_CTRL_TC_ENABLE |
 299                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 300                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 301                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 302                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 303                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 304                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 305                                COH901318_CX_CTRL_TCP_ENABLE |
 306                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 307                                COH901318_CX_CTRL_HSP_ENABLE |
 308                                COH901318_CX_CTRL_HSS_DISABLE |
 309                                COH901318_CX_CTRL_DDMA_LEGACY |
 310                                COH901318_CX_CTRL_PRDD_SOURCE,
 311                .param.ctrl_lli_last = 0 |
 312                                COH901318_CX_CTRL_TC_ENABLE |
 313                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 314                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 315                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 316                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 317                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 318                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 319                                COH901318_CX_CTRL_TCP_ENABLE |
 320                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 321                                COH901318_CX_CTRL_HSP_ENABLE |
 322                                COH901318_CX_CTRL_HSS_DISABLE |
 323                                COH901318_CX_CTRL_DDMA_LEGACY |
 324                                COH901318_CX_CTRL_PRDD_SOURCE,
 325        },
 326        {
 327                .number = U300_DMA_MSL_TX_2,
 328                .name = "MSL TX 2",
 329                .priority_high = 0,
 330                .param.config = COH901318_CX_CFG_CH_DISABLE |
 331                                COH901318_CX_CFG_LCR_DISABLE |
 332                                COH901318_CX_CFG_TC_IRQ_ENABLE |
 333                                COH901318_CX_CFG_BE_IRQ_ENABLE,
 334                .param.ctrl_lli_chained = 0 |
 335                                COH901318_CX_CTRL_TC_ENABLE |
 336                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 337                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 338                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 339                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 340                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 341                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 342                                COH901318_CX_CTRL_TCP_DISABLE |
 343                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 344                                COH901318_CX_CTRL_HSP_ENABLE |
 345                                COH901318_CX_CTRL_HSS_DISABLE |
 346                                COH901318_CX_CTRL_DDMA_LEGACY |
 347                                COH901318_CX_CTRL_PRDD_SOURCE,
 348                .param.ctrl_lli = 0 |
 349                                COH901318_CX_CTRL_TC_ENABLE |
 350                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 351                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 352                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 353                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 354                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 355                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 356                                COH901318_CX_CTRL_TCP_ENABLE |
 357                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 358                                COH901318_CX_CTRL_HSP_ENABLE |
 359                                COH901318_CX_CTRL_HSS_DISABLE |
 360                                COH901318_CX_CTRL_DDMA_LEGACY |
 361                                COH901318_CX_CTRL_PRDD_SOURCE,
 362                .param.ctrl_lli_last = 0 |
 363                                COH901318_CX_CTRL_TC_ENABLE |
 364                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 365                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 366                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 367                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 368                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 369                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 370                                COH901318_CX_CTRL_TCP_ENABLE |
 371                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 372                                COH901318_CX_CTRL_HSP_ENABLE |
 373                                COH901318_CX_CTRL_HSS_DISABLE |
 374                                COH901318_CX_CTRL_DDMA_LEGACY |
 375                                COH901318_CX_CTRL_PRDD_SOURCE,
 376                .desc_nbr_max = 10,
 377        },
 378        {
 379                .number = U300_DMA_MSL_TX_3,
 380                .name = "MSL TX 3",
 381                .priority_high = 0,
 382                .param.config = COH901318_CX_CFG_CH_DISABLE |
 383                                COH901318_CX_CFG_LCR_DISABLE |
 384                                COH901318_CX_CFG_TC_IRQ_ENABLE |
 385                                COH901318_CX_CFG_BE_IRQ_ENABLE,
 386                .param.ctrl_lli_chained = 0 |
 387                                COH901318_CX_CTRL_TC_ENABLE |
 388                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 389                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 390                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 391                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 392                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 393                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 394                                COH901318_CX_CTRL_TCP_DISABLE |
 395                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 396                                COH901318_CX_CTRL_HSP_ENABLE |
 397                                COH901318_CX_CTRL_HSS_DISABLE |
 398                                COH901318_CX_CTRL_DDMA_LEGACY |
 399                                COH901318_CX_CTRL_PRDD_SOURCE,
 400                .param.ctrl_lli = 0 |
 401                                COH901318_CX_CTRL_TC_ENABLE |
 402                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 403                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 404                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 405                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 406                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 407                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 408                                COH901318_CX_CTRL_TCP_ENABLE |
 409                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 410                                COH901318_CX_CTRL_HSP_ENABLE |
 411                                COH901318_CX_CTRL_HSS_DISABLE |
 412                                COH901318_CX_CTRL_DDMA_LEGACY |
 413                                COH901318_CX_CTRL_PRDD_SOURCE,
 414                .param.ctrl_lli_last = 0 |
 415                                COH901318_CX_CTRL_TC_ENABLE |
 416                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 417                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 418                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 419                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 420                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 421                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 422                                COH901318_CX_CTRL_TCP_ENABLE |
 423                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 424                                COH901318_CX_CTRL_HSP_ENABLE |
 425                                COH901318_CX_CTRL_HSS_DISABLE |
 426                                COH901318_CX_CTRL_DDMA_LEGACY |
 427                                COH901318_CX_CTRL_PRDD_SOURCE,
 428        },
 429        {
 430                .number = U300_DMA_MSL_TX_4,
 431                .name = "MSL TX 4",
 432                .priority_high = 0,
 433                .param.config = COH901318_CX_CFG_CH_DISABLE |
 434                                COH901318_CX_CFG_LCR_DISABLE |
 435                                COH901318_CX_CFG_TC_IRQ_ENABLE |
 436                                COH901318_CX_CFG_BE_IRQ_ENABLE,
 437                .param.ctrl_lli_chained = 0 |
 438                                COH901318_CX_CTRL_TC_ENABLE |
 439                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 440                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 441                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 442                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 443                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 444                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 445                                COH901318_CX_CTRL_TCP_DISABLE |
 446                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 447                                COH901318_CX_CTRL_HSP_ENABLE |
 448                                COH901318_CX_CTRL_HSS_DISABLE |
 449                                COH901318_CX_CTRL_DDMA_LEGACY |
 450                                COH901318_CX_CTRL_PRDD_SOURCE,
 451                .param.ctrl_lli = 0 |
 452                                COH901318_CX_CTRL_TC_ENABLE |
 453                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 454                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 455                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 456                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 457                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 458                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 459                                COH901318_CX_CTRL_TCP_ENABLE |
 460                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 461                                COH901318_CX_CTRL_HSP_ENABLE |
 462                                COH901318_CX_CTRL_HSS_DISABLE |
 463                                COH901318_CX_CTRL_DDMA_LEGACY |
 464                                COH901318_CX_CTRL_PRDD_SOURCE,
 465                .param.ctrl_lli_last = 0 |
 466                                COH901318_CX_CTRL_TC_ENABLE |
 467                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 468                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 469                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 470                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 471                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 472                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 473                                COH901318_CX_CTRL_TCP_ENABLE |
 474                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 475                                COH901318_CX_CTRL_HSP_ENABLE |
 476                                COH901318_CX_CTRL_HSS_DISABLE |
 477                                COH901318_CX_CTRL_DDMA_LEGACY |
 478                                COH901318_CX_CTRL_PRDD_SOURCE,
 479        },
 480        {
 481                .number = U300_DMA_MSL_TX_5,
 482                .name = "MSL TX 5",
 483                .priority_high = 0,
 484        },
 485        {
 486                .number = U300_DMA_MSL_TX_6,
 487                .name = "MSL TX 6",
 488                .priority_high = 0,
 489        },
 490        {
 491                .number = U300_DMA_MSL_RX_0,
 492                .name = "MSL RX 0",
 493                .priority_high = 0,
 494        },
 495        {
 496                .number = U300_DMA_MSL_RX_1,
 497                .name = "MSL RX 1",
 498                .priority_high = 0,
 499                .param.config = COH901318_CX_CFG_CH_DISABLE |
 500                                COH901318_CX_CFG_LCR_DISABLE |
 501                                COH901318_CX_CFG_TC_IRQ_ENABLE |
 502                                COH901318_CX_CFG_BE_IRQ_ENABLE,
 503                .param.ctrl_lli_chained = 0 |
 504                                COH901318_CX_CTRL_TC_ENABLE |
 505                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 506                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 507                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 508                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 509                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 510                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 511                                COH901318_CX_CTRL_TCP_DISABLE |
 512                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 513                                COH901318_CX_CTRL_HSP_ENABLE |
 514                                COH901318_CX_CTRL_HSS_DISABLE |
 515                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 516                                COH901318_CX_CTRL_PRDD_DEST,
 517                .param.ctrl_lli = 0,
 518                .param.ctrl_lli_last = 0 |
 519                                COH901318_CX_CTRL_TC_ENABLE |
 520                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 521                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 522                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 523                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 524                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 525                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 526                                COH901318_CX_CTRL_TCP_DISABLE |
 527                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 528                                COH901318_CX_CTRL_HSP_ENABLE |
 529                                COH901318_CX_CTRL_HSS_DISABLE |
 530                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 531                                COH901318_CX_CTRL_PRDD_DEST,
 532        },
 533        {
 534                .number = U300_DMA_MSL_RX_2,
 535                .name = "MSL RX 2",
 536                .priority_high = 0,
 537                .param.config = COH901318_CX_CFG_CH_DISABLE |
 538                                COH901318_CX_CFG_LCR_DISABLE |
 539                                COH901318_CX_CFG_TC_IRQ_ENABLE |
 540                                COH901318_CX_CFG_BE_IRQ_ENABLE,
 541                .param.ctrl_lli_chained = 0 |
 542                                COH901318_CX_CTRL_TC_ENABLE |
 543                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 544                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 545                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 546                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 547                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 548                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 549                                COH901318_CX_CTRL_TCP_DISABLE |
 550                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 551                                COH901318_CX_CTRL_HSP_ENABLE |
 552                                COH901318_CX_CTRL_HSS_DISABLE |
 553                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 554                                COH901318_CX_CTRL_PRDD_DEST,
 555                .param.ctrl_lli = 0 |
 556                                COH901318_CX_CTRL_TC_ENABLE |
 557                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 558                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 559                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 560                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 561                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 562                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 563                                COH901318_CX_CTRL_TCP_DISABLE |
 564                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 565                                COH901318_CX_CTRL_HSP_ENABLE |
 566                                COH901318_CX_CTRL_HSS_DISABLE |
 567                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 568                                COH901318_CX_CTRL_PRDD_DEST,
 569                .param.ctrl_lli_last = 0 |
 570                                COH901318_CX_CTRL_TC_ENABLE |
 571                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 572                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 573                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 574                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 575                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 576                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 577                                COH901318_CX_CTRL_TCP_DISABLE |
 578                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 579                                COH901318_CX_CTRL_HSP_ENABLE |
 580                                COH901318_CX_CTRL_HSS_DISABLE |
 581                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 582                                COH901318_CX_CTRL_PRDD_DEST,
 583        },
 584        {
 585                .number = U300_DMA_MSL_RX_3,
 586                .name = "MSL RX 3",
 587                .priority_high = 0,
 588                .param.config = COH901318_CX_CFG_CH_DISABLE |
 589                                COH901318_CX_CFG_LCR_DISABLE |
 590                                COH901318_CX_CFG_TC_IRQ_ENABLE |
 591                                COH901318_CX_CFG_BE_IRQ_ENABLE,
 592                .param.ctrl_lli_chained = 0 |
 593                                COH901318_CX_CTRL_TC_ENABLE |
 594                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 595                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 596                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 597                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 598                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 599                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 600                                COH901318_CX_CTRL_TCP_DISABLE |
 601                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 602                                COH901318_CX_CTRL_HSP_ENABLE |
 603                                COH901318_CX_CTRL_HSS_DISABLE |
 604                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 605                                COH901318_CX_CTRL_PRDD_DEST,
 606                .param.ctrl_lli = 0 |
 607                                COH901318_CX_CTRL_TC_ENABLE |
 608                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 609                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 610                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 611                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 612                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 613                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 614                                COH901318_CX_CTRL_TCP_DISABLE |
 615                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 616                                COH901318_CX_CTRL_HSP_ENABLE |
 617                                COH901318_CX_CTRL_HSS_DISABLE |
 618                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 619                                COH901318_CX_CTRL_PRDD_DEST,
 620                .param.ctrl_lli_last = 0 |
 621                                COH901318_CX_CTRL_TC_ENABLE |
 622                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 623                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 624                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 625                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 626                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 627                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 628                                COH901318_CX_CTRL_TCP_DISABLE |
 629                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 630                                COH901318_CX_CTRL_HSP_ENABLE |
 631                                COH901318_CX_CTRL_HSS_DISABLE |
 632                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 633                                COH901318_CX_CTRL_PRDD_DEST,
 634        },
 635        {
 636                .number = U300_DMA_MSL_RX_4,
 637                .name = "MSL RX 4",
 638                .priority_high = 0,
 639                .param.config = COH901318_CX_CFG_CH_DISABLE |
 640                                COH901318_CX_CFG_LCR_DISABLE |
 641                                COH901318_CX_CFG_TC_IRQ_ENABLE |
 642                                COH901318_CX_CFG_BE_IRQ_ENABLE,
 643                .param.ctrl_lli_chained = 0 |
 644                                COH901318_CX_CTRL_TC_ENABLE |
 645                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 646                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 647                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 648                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 649                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 650                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 651                                COH901318_CX_CTRL_TCP_DISABLE |
 652                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 653                                COH901318_CX_CTRL_HSP_ENABLE |
 654                                COH901318_CX_CTRL_HSS_DISABLE |
 655                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 656                                COH901318_CX_CTRL_PRDD_DEST,
 657                .param.ctrl_lli = 0 |
 658                                COH901318_CX_CTRL_TC_ENABLE |
 659                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 660                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 661                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 662                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 663                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 664                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 665                                COH901318_CX_CTRL_TCP_DISABLE |
 666                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 667                                COH901318_CX_CTRL_HSP_ENABLE |
 668                                COH901318_CX_CTRL_HSS_DISABLE |
 669                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 670                                COH901318_CX_CTRL_PRDD_DEST,
 671                .param.ctrl_lli_last = 0 |
 672                                COH901318_CX_CTRL_TC_ENABLE |
 673                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 674                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 675                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 676                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 677                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 678                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 679                                COH901318_CX_CTRL_TCP_DISABLE |
 680                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 681                                COH901318_CX_CTRL_HSP_ENABLE |
 682                                COH901318_CX_CTRL_HSS_DISABLE |
 683                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 684                                COH901318_CX_CTRL_PRDD_DEST,
 685        },
 686        {
 687                .number = U300_DMA_MSL_RX_5,
 688                .name = "MSL RX 5",
 689                .priority_high = 0,
 690                .param.config = COH901318_CX_CFG_CH_DISABLE |
 691                                COH901318_CX_CFG_LCR_DISABLE |
 692                                COH901318_CX_CFG_TC_IRQ_ENABLE |
 693                                COH901318_CX_CFG_BE_IRQ_ENABLE,
 694                .param.ctrl_lli_chained = 0 |
 695                                COH901318_CX_CTRL_TC_ENABLE |
 696                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 697                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 698                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 699                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 700                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 701                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 702                                COH901318_CX_CTRL_TCP_DISABLE |
 703                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 704                                COH901318_CX_CTRL_HSP_ENABLE |
 705                                COH901318_CX_CTRL_HSS_DISABLE |
 706                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 707                                COH901318_CX_CTRL_PRDD_DEST,
 708                .param.ctrl_lli = 0 |
 709                                COH901318_CX_CTRL_TC_ENABLE |
 710                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 711                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 712                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 713                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 714                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 715                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 716                                COH901318_CX_CTRL_TCP_DISABLE |
 717                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 718                                COH901318_CX_CTRL_HSP_ENABLE |
 719                                COH901318_CX_CTRL_HSS_DISABLE |
 720                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 721                                COH901318_CX_CTRL_PRDD_DEST,
 722                .param.ctrl_lli_last = 0 |
 723                                COH901318_CX_CTRL_TC_ENABLE |
 724                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 725                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 726                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 727                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 728                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 729                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 730                                COH901318_CX_CTRL_TCP_DISABLE |
 731                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 732                                COH901318_CX_CTRL_HSP_ENABLE |
 733                                COH901318_CX_CTRL_HSS_DISABLE |
 734                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 735                                COH901318_CX_CTRL_PRDD_DEST,
 736        },
 737        {
 738                .number = U300_DMA_MSL_RX_6,
 739                .name = "MSL RX 6",
 740                .priority_high = 0,
 741        },
 742        /*
 743         * Don't set up device address, burst count or size of src
 744         * or dst bus for this peripheral - handled by PrimeCell
 745         * DMA extension.
 746         */
 747        {
 748                .number = U300_DMA_MMCSD_RX_TX,
 749                .name = "MMCSD RX TX",
 750                .priority_high = 0,
 751                .param.config = COH901318_CX_CFG_CH_DISABLE |
 752                                COH901318_CX_CFG_LCR_DISABLE |
 753                                COH901318_CX_CFG_TC_IRQ_ENABLE |
 754                                COH901318_CX_CFG_BE_IRQ_ENABLE,
 755                .param.ctrl_lli_chained = 0 |
 756                                COH901318_CX_CTRL_TC_ENABLE |
 757                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
 758                                COH901318_CX_CTRL_TCP_ENABLE |
 759                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 760                                COH901318_CX_CTRL_HSP_ENABLE |
 761                                COH901318_CX_CTRL_HSS_DISABLE |
 762                                COH901318_CX_CTRL_DDMA_LEGACY,
 763                .param.ctrl_lli = 0 |
 764                                COH901318_CX_CTRL_TC_ENABLE |
 765                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
 766                                COH901318_CX_CTRL_TCP_ENABLE |
 767                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 768                                COH901318_CX_CTRL_HSP_ENABLE |
 769                                COH901318_CX_CTRL_HSS_DISABLE |
 770                                COH901318_CX_CTRL_DDMA_LEGACY,
 771                .param.ctrl_lli_last = 0 |
 772                                COH901318_CX_CTRL_TC_ENABLE |
 773                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
 774                                COH901318_CX_CTRL_TCP_DISABLE |
 775                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 776                                COH901318_CX_CTRL_HSP_ENABLE |
 777                                COH901318_CX_CTRL_HSS_DISABLE |
 778                                COH901318_CX_CTRL_DDMA_LEGACY,
 779
 780        },
 781        {
 782                .number = U300_DMA_MSPRO_TX,
 783                .name = "MSPRO TX",
 784                .priority_high = 0,
 785        },
 786        {
 787                .number = U300_DMA_MSPRO_RX,
 788                .name = "MSPRO RX",
 789                .priority_high = 0,
 790        },
 791        /*
 792         * Don't set up device address, burst count or size of src
 793         * or dst bus for this peripheral - handled by PrimeCell
 794         * DMA extension.
 795         */
 796        {
 797                .number = U300_DMA_UART0_TX,
 798                .name = "UART0 TX",
 799                .priority_high = 0,
 800                .param.config = COH901318_CX_CFG_CH_DISABLE |
 801                                COH901318_CX_CFG_LCR_DISABLE |
 802                                COH901318_CX_CFG_TC_IRQ_ENABLE |
 803                                COH901318_CX_CFG_BE_IRQ_ENABLE,
 804                .param.ctrl_lli_chained = 0 |
 805                                COH901318_CX_CTRL_TC_ENABLE |
 806                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
 807                                COH901318_CX_CTRL_TCP_ENABLE |
 808                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 809                                COH901318_CX_CTRL_HSP_ENABLE |
 810                                COH901318_CX_CTRL_HSS_DISABLE |
 811                                COH901318_CX_CTRL_DDMA_LEGACY,
 812                .param.ctrl_lli = 0 |
 813                                COH901318_CX_CTRL_TC_ENABLE |
 814                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
 815                                COH901318_CX_CTRL_TCP_ENABLE |
 816                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 817                                COH901318_CX_CTRL_HSP_ENABLE |
 818                                COH901318_CX_CTRL_HSS_DISABLE |
 819                                COH901318_CX_CTRL_DDMA_LEGACY,
 820                .param.ctrl_lli_last = 0 |
 821                                COH901318_CX_CTRL_TC_ENABLE |
 822                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
 823                                COH901318_CX_CTRL_TCP_ENABLE |
 824                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 825                                COH901318_CX_CTRL_HSP_ENABLE |
 826                                COH901318_CX_CTRL_HSS_DISABLE |
 827                                COH901318_CX_CTRL_DDMA_LEGACY,
 828        },
 829        {
 830                .number = U300_DMA_UART0_RX,
 831                .name = "UART0 RX",
 832                .priority_high = 0,
 833                .param.config = COH901318_CX_CFG_CH_DISABLE |
 834                                COH901318_CX_CFG_LCR_DISABLE |
 835                                COH901318_CX_CFG_TC_IRQ_ENABLE |
 836                                COH901318_CX_CFG_BE_IRQ_ENABLE,
 837                .param.ctrl_lli_chained = 0 |
 838                                COH901318_CX_CTRL_TC_ENABLE |
 839                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
 840                                COH901318_CX_CTRL_TCP_ENABLE |
 841                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 842                                COH901318_CX_CTRL_HSP_ENABLE |
 843                                COH901318_CX_CTRL_HSS_DISABLE |
 844                                COH901318_CX_CTRL_DDMA_LEGACY,
 845                .param.ctrl_lli = 0 |
 846                                COH901318_CX_CTRL_TC_ENABLE |
 847                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
 848                                COH901318_CX_CTRL_TCP_ENABLE |
 849                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 850                                COH901318_CX_CTRL_HSP_ENABLE |
 851                                COH901318_CX_CTRL_HSS_DISABLE |
 852                                COH901318_CX_CTRL_DDMA_LEGACY,
 853                .param.ctrl_lli_last = 0 |
 854                                COH901318_CX_CTRL_TC_ENABLE |
 855                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
 856                                COH901318_CX_CTRL_TCP_ENABLE |
 857                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 858                                COH901318_CX_CTRL_HSP_ENABLE |
 859                                COH901318_CX_CTRL_HSS_DISABLE |
 860                                COH901318_CX_CTRL_DDMA_LEGACY,
 861        },
 862        {
 863                .number = U300_DMA_APEX_TX,
 864                .name = "APEX TX",
 865                .priority_high = 0,
 866        },
 867        {
 868                .number = U300_DMA_APEX_RX,
 869                .name = "APEX RX",
 870                .priority_high = 0,
 871        },
 872        {
 873                .number = U300_DMA_PCM_I2S0_TX,
 874                .name = "PCM I2S0 TX",
 875                .priority_high = 1,
 876                .param.config = COH901318_CX_CFG_CH_DISABLE |
 877                                COH901318_CX_CFG_LCR_DISABLE |
 878                                COH901318_CX_CFG_TC_IRQ_ENABLE |
 879                                COH901318_CX_CFG_BE_IRQ_ENABLE,
 880                .param.ctrl_lli_chained = 0 |
 881                                COH901318_CX_CTRL_TC_ENABLE |
 882                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
 883                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 884                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 885                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 886                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 887                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
 888                                COH901318_CX_CTRL_TCP_DISABLE |
 889                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 890                                COH901318_CX_CTRL_HSP_ENABLE |
 891                                COH901318_CX_CTRL_HSS_DISABLE |
 892                                COH901318_CX_CTRL_DDMA_LEGACY |
 893                                COH901318_CX_CTRL_PRDD_SOURCE,
 894                .param.ctrl_lli = 0 |
 895                                COH901318_CX_CTRL_TC_ENABLE |
 896                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
 897                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 898                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 899                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 900                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 901                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
 902                                COH901318_CX_CTRL_TCP_ENABLE |
 903                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 904                                COH901318_CX_CTRL_HSP_ENABLE |
 905                                COH901318_CX_CTRL_HSS_DISABLE |
 906                                COH901318_CX_CTRL_DDMA_LEGACY |
 907                                COH901318_CX_CTRL_PRDD_SOURCE,
 908                .param.ctrl_lli_last = 0 |
 909                                COH901318_CX_CTRL_TC_ENABLE |
 910                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
 911                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 912                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 913                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 914                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 915                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
 916                                COH901318_CX_CTRL_TCP_ENABLE |
 917                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 918                                COH901318_CX_CTRL_HSP_ENABLE |
 919                                COH901318_CX_CTRL_HSS_DISABLE |
 920                                COH901318_CX_CTRL_DDMA_LEGACY |
 921                                COH901318_CX_CTRL_PRDD_SOURCE,
 922        },
 923        {
 924                .number = U300_DMA_PCM_I2S0_RX,
 925                .name = "PCM I2S0 RX",
 926                .priority_high = 1,
 927                .param.config = COH901318_CX_CFG_CH_DISABLE |
 928                                COH901318_CX_CFG_LCR_DISABLE |
 929                                COH901318_CX_CFG_TC_IRQ_ENABLE |
 930                                COH901318_CX_CFG_BE_IRQ_ENABLE,
 931                .param.ctrl_lli_chained = 0 |
 932                                COH901318_CX_CTRL_TC_ENABLE |
 933                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
 934                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 935                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 936                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 937                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 938                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
 939                                COH901318_CX_CTRL_TCP_DISABLE |
 940                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 941                                COH901318_CX_CTRL_HSP_ENABLE |
 942                                COH901318_CX_CTRL_HSS_DISABLE |
 943                                COH901318_CX_CTRL_DDMA_LEGACY |
 944                                COH901318_CX_CTRL_PRDD_DEST,
 945                .param.ctrl_lli = 0 |
 946                                COH901318_CX_CTRL_TC_ENABLE |
 947                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
 948                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 949                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 950                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 951                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 952                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
 953                                COH901318_CX_CTRL_TCP_ENABLE |
 954                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 955                                COH901318_CX_CTRL_HSP_ENABLE |
 956                                COH901318_CX_CTRL_HSS_DISABLE |
 957                                COH901318_CX_CTRL_DDMA_LEGACY |
 958                                COH901318_CX_CTRL_PRDD_DEST,
 959                .param.ctrl_lli_last = 0 |
 960                                COH901318_CX_CTRL_TC_ENABLE |
 961                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
 962                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 963                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 964                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 965                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 966                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
 967                                COH901318_CX_CTRL_TCP_ENABLE |
 968                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
 969                                COH901318_CX_CTRL_HSP_ENABLE |
 970                                COH901318_CX_CTRL_HSS_DISABLE |
 971                                COH901318_CX_CTRL_DDMA_LEGACY |
 972                                COH901318_CX_CTRL_PRDD_DEST,
 973        },
 974        {
 975                .number = U300_DMA_PCM_I2S1_TX,
 976                .name = "PCM I2S1 TX",
 977                .priority_high = 1,
 978                .param.config = COH901318_CX_CFG_CH_DISABLE |
 979                                COH901318_CX_CFG_LCR_DISABLE |
 980                                COH901318_CX_CFG_TC_IRQ_ENABLE |
 981                                COH901318_CX_CFG_BE_IRQ_ENABLE,
 982                .param.ctrl_lli_chained = 0 |
 983                                COH901318_CX_CTRL_TC_ENABLE |
 984                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
 985                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 986                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 987                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 988                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 989                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
 990                                COH901318_CX_CTRL_TCP_DISABLE |
 991                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
 992                                COH901318_CX_CTRL_HSP_ENABLE |
 993                                COH901318_CX_CTRL_HSS_DISABLE |
 994                                COH901318_CX_CTRL_DDMA_LEGACY |
 995                                COH901318_CX_CTRL_PRDD_SOURCE,
 996                .param.ctrl_lli = 0 |
 997                                COH901318_CX_CTRL_TC_ENABLE |
 998                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
 999                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1000                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1001                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1002                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1003                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
1004                                COH901318_CX_CTRL_TCP_ENABLE |
1005                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
1006                                COH901318_CX_CTRL_HSP_ENABLE |
1007                                COH901318_CX_CTRL_HSS_DISABLE |
1008                                COH901318_CX_CTRL_DDMA_LEGACY |
1009                                COH901318_CX_CTRL_PRDD_SOURCE,
1010                .param.ctrl_lli_last = 0 |
1011                                COH901318_CX_CTRL_TC_ENABLE |
1012                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1013                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1014                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1015                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1016                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1017                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
1018                                COH901318_CX_CTRL_TCP_ENABLE |
1019                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
1020                                COH901318_CX_CTRL_HSP_ENABLE |
1021                                COH901318_CX_CTRL_HSS_DISABLE |
1022                                COH901318_CX_CTRL_DDMA_LEGACY |
1023                                COH901318_CX_CTRL_PRDD_SOURCE,
1024        },
1025        {
1026                .number = U300_DMA_PCM_I2S1_RX,
1027                .name = "PCM I2S1 RX",
1028                .priority_high = 1,
1029                .param.config = COH901318_CX_CFG_CH_DISABLE |
1030                                COH901318_CX_CFG_LCR_DISABLE |
1031                                COH901318_CX_CFG_TC_IRQ_ENABLE |
1032                                COH901318_CX_CFG_BE_IRQ_ENABLE,
1033                .param.ctrl_lli_chained = 0 |
1034                                COH901318_CX_CTRL_TC_ENABLE |
1035                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1036                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1037                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1038                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1039                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1040                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
1041                                COH901318_CX_CTRL_TCP_DISABLE |
1042                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
1043                                COH901318_CX_CTRL_HSP_ENABLE |
1044                                COH901318_CX_CTRL_HSS_DISABLE |
1045                                COH901318_CX_CTRL_DDMA_LEGACY |
1046                                COH901318_CX_CTRL_PRDD_DEST,
1047                .param.ctrl_lli = 0 |
1048                                COH901318_CX_CTRL_TC_ENABLE |
1049                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1050                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1051                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1052                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1053                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1054                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
1055                                COH901318_CX_CTRL_TCP_ENABLE |
1056                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
1057                                COH901318_CX_CTRL_HSP_ENABLE |
1058                                COH901318_CX_CTRL_HSS_DISABLE |
1059                                COH901318_CX_CTRL_DDMA_LEGACY |
1060                                COH901318_CX_CTRL_PRDD_DEST,
1061                .param.ctrl_lli_last = 0 |
1062                                COH901318_CX_CTRL_TC_ENABLE |
1063                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1064                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1065                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1066                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1067                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1068                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
1069                                COH901318_CX_CTRL_TCP_ENABLE |
1070                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
1071                                COH901318_CX_CTRL_HSP_ENABLE |
1072                                COH901318_CX_CTRL_HSS_DISABLE |
1073                                COH901318_CX_CTRL_DDMA_LEGACY |
1074                                COH901318_CX_CTRL_PRDD_DEST,
1075        },
1076        {
1077                .number = U300_DMA_XGAM_CDI,
1078                .name = "XGAM CDI",
1079                .priority_high = 0,
1080        },
1081        {
1082                .number = U300_DMA_XGAM_PDI,
1083                .name = "XGAM PDI",
1084                .priority_high = 0,
1085        },
1086        /*
1087         * Don't set up device address, burst count or size of src
1088         * or dst bus for this peripheral - handled by PrimeCell
1089         * DMA extension.
1090         */
1091        {
1092                .number = U300_DMA_SPI_TX,
1093                .name = "SPI TX",
1094                .priority_high = 0,
1095                .param.config = COH901318_CX_CFG_CH_DISABLE |
1096                                COH901318_CX_CFG_LCR_DISABLE |
1097                                COH901318_CX_CFG_TC_IRQ_ENABLE |
1098                                COH901318_CX_CFG_BE_IRQ_ENABLE,
1099                .param.ctrl_lli_chained = 0 |
1100                                COH901318_CX_CTRL_TC_ENABLE |
1101                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
1102                                COH901318_CX_CTRL_TCP_DISABLE |
1103                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
1104                                COH901318_CX_CTRL_HSP_ENABLE |
1105                                COH901318_CX_CTRL_HSS_DISABLE |
1106                                COH901318_CX_CTRL_DDMA_LEGACY,
1107                .param.ctrl_lli = 0 |
1108                                COH901318_CX_CTRL_TC_ENABLE |
1109                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
1110                                COH901318_CX_CTRL_TCP_DISABLE |
1111                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
1112                                COH901318_CX_CTRL_HSP_ENABLE |
1113                                COH901318_CX_CTRL_HSS_DISABLE |
1114                                COH901318_CX_CTRL_DDMA_LEGACY,
1115                .param.ctrl_lli_last = 0 |
1116                                COH901318_CX_CTRL_TC_ENABLE |
1117                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
1118                                COH901318_CX_CTRL_TCP_DISABLE |
1119                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
1120                                COH901318_CX_CTRL_HSP_ENABLE |
1121                                COH901318_CX_CTRL_HSS_DISABLE |
1122                                COH901318_CX_CTRL_DDMA_LEGACY,
1123        },
1124        {
1125                .number = U300_DMA_SPI_RX,
1126                .name = "SPI RX",
1127                .priority_high = 0,
1128                .param.config = COH901318_CX_CFG_CH_DISABLE |
1129                                COH901318_CX_CFG_LCR_DISABLE |
1130                                COH901318_CX_CFG_TC_IRQ_ENABLE |
1131                                COH901318_CX_CFG_BE_IRQ_ENABLE,
1132                .param.ctrl_lli_chained = 0 |
1133                                COH901318_CX_CTRL_TC_ENABLE |
1134                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
1135                                COH901318_CX_CTRL_TCP_DISABLE |
1136                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
1137                                COH901318_CX_CTRL_HSP_ENABLE |
1138                                COH901318_CX_CTRL_HSS_DISABLE |
1139                                COH901318_CX_CTRL_DDMA_LEGACY,
1140                .param.ctrl_lli = 0 |
1141                                COH901318_CX_CTRL_TC_ENABLE |
1142                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
1143                                COH901318_CX_CTRL_TCP_DISABLE |
1144                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
1145                                COH901318_CX_CTRL_HSP_ENABLE |
1146                                COH901318_CX_CTRL_HSS_DISABLE |
1147                                COH901318_CX_CTRL_DDMA_LEGACY,
1148                .param.ctrl_lli_last = 0 |
1149                                COH901318_CX_CTRL_TC_ENABLE |
1150                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
1151                                COH901318_CX_CTRL_TCP_DISABLE |
1152                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
1153                                COH901318_CX_CTRL_HSP_ENABLE |
1154                                COH901318_CX_CTRL_HSS_DISABLE |
1155                                COH901318_CX_CTRL_DDMA_LEGACY,
1156
1157        },
1158        {
1159                .number = U300_DMA_GENERAL_PURPOSE_0,
1160                .name = "GENERAL 00",
1161                .priority_high = 0,
1162
1163                .param.config = flags_memcpy_config,
1164                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1165                .param.ctrl_lli = flags_memcpy_lli,
1166                .param.ctrl_lli_last = flags_memcpy_lli_last,
1167        },
1168        {
1169                .number = U300_DMA_GENERAL_PURPOSE_1,
1170                .name = "GENERAL 01",
1171                .priority_high = 0,
1172
1173                .param.config = flags_memcpy_config,
1174                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1175                .param.ctrl_lli = flags_memcpy_lli,
1176                .param.ctrl_lli_last = flags_memcpy_lli_last,
1177        },
1178        {
1179                .number = U300_DMA_GENERAL_PURPOSE_2,
1180                .name = "GENERAL 02",
1181                .priority_high = 0,
1182
1183                .param.config = flags_memcpy_config,
1184                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1185                .param.ctrl_lli = flags_memcpy_lli,
1186                .param.ctrl_lli_last = flags_memcpy_lli_last,
1187        },
1188        {
1189                .number = U300_DMA_GENERAL_PURPOSE_3,
1190                .name = "GENERAL 03",
1191                .priority_high = 0,
1192
1193                .param.config = flags_memcpy_config,
1194                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1195                .param.ctrl_lli = flags_memcpy_lli,
1196                .param.ctrl_lli_last = flags_memcpy_lli_last,
1197        },
1198        {
1199                .number = U300_DMA_GENERAL_PURPOSE_4,
1200                .name = "GENERAL 04",
1201                .priority_high = 0,
1202
1203                .param.config = flags_memcpy_config,
1204                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1205                .param.ctrl_lli = flags_memcpy_lli,
1206                .param.ctrl_lli_last = flags_memcpy_lli_last,
1207        },
1208        {
1209                .number = U300_DMA_GENERAL_PURPOSE_5,
1210                .name = "GENERAL 05",
1211                .priority_high = 0,
1212
1213                .param.config = flags_memcpy_config,
1214                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1215                .param.ctrl_lli = flags_memcpy_lli,
1216                .param.ctrl_lli_last = flags_memcpy_lli_last,
1217        },
1218        {
1219                .number = U300_DMA_GENERAL_PURPOSE_6,
1220                .name = "GENERAL 06",
1221                .priority_high = 0,
1222
1223                .param.config = flags_memcpy_config,
1224                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1225                .param.ctrl_lli = flags_memcpy_lli,
1226                .param.ctrl_lli_last = flags_memcpy_lli_last,
1227        },
1228        {
1229                .number = U300_DMA_GENERAL_PURPOSE_7,
1230                .name = "GENERAL 07",
1231                .priority_high = 0,
1232
1233                .param.config = flags_memcpy_config,
1234                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1235                .param.ctrl_lli = flags_memcpy_lli,
1236                .param.ctrl_lli_last = flags_memcpy_lli_last,
1237        },
1238        {
1239                .number = U300_DMA_GENERAL_PURPOSE_8,
1240                .name = "GENERAL 08",
1241                .priority_high = 0,
1242
1243                .param.config = flags_memcpy_config,
1244                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1245                .param.ctrl_lli = flags_memcpy_lli,
1246                .param.ctrl_lli_last = flags_memcpy_lli_last,
1247        },
1248        {
1249                .number = U300_DMA_UART1_TX,
1250                .name = "UART1 TX",
1251                .priority_high = 0,
1252        },
1253        {
1254                .number = U300_DMA_UART1_RX,
1255                .name = "UART1 RX",
1256                .priority_high = 0,
1257        }
1258};
1259
1260#define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
1261
1262#ifdef VERBOSE_DEBUG
1263#define COH_DBG(x) ({ if (1) x; 0; })
1264#else
1265#define COH_DBG(x) ({ if (0) x; 0; })
1266#endif
1267
1268struct coh901318_desc {
1269        struct dma_async_tx_descriptor desc;
1270        struct list_head node;
1271        struct scatterlist *sg;
1272        unsigned int sg_len;
1273        struct coh901318_lli *lli;
1274        enum dma_transfer_direction dir;
1275        unsigned long flags;
1276        u32 head_config;
1277        u32 head_ctrl;
1278};
1279
1280struct coh901318_base {
1281        struct device *dev;
1282        void __iomem *virtbase;
1283        struct coh901318_pool pool;
1284        struct powersave pm;
1285        struct dma_device dma_slave;
1286        struct dma_device dma_memcpy;
1287        struct coh901318_chan *chans;
1288};
1289
1290struct coh901318_chan {
1291        spinlock_t lock;
1292        int allocated;
1293        int id;
1294        int stopped;
1295
1296        struct work_struct free_work;
1297        struct dma_chan chan;
1298
1299        struct tasklet_struct tasklet;
1300
1301        struct list_head active;
1302        struct list_head queue;
1303        struct list_head free;
1304
1305        unsigned long nbr_active_done;
1306        unsigned long busy;
1307
1308        u32 addr;
1309        u32 ctrl;
1310
1311        struct coh901318_base *base;
1312};
1313
1314static void coh901318_list_print(struct coh901318_chan *cohc,
1315                                 struct coh901318_lli *lli)
1316{
1317        struct coh901318_lli *l = lli;
1318        int i = 0;
1319
1320        while (l) {
1321                dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
1322                         ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
1323                         i, l, l->control, l->src_addr, l->dst_addr,
1324                         l->link_addr, l->virt_link_addr);
1325                i++;
1326                l = l->virt_link_addr;
1327        }
1328}
1329
1330#ifdef CONFIG_DEBUG_FS
1331
1332#define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
1333
1334static struct coh901318_base *debugfs_dma_base;
1335static struct dentry *dma_dentry;
1336
1337static int coh901318_debugfs_read(struct file *file, char __user *buf,
1338                                  size_t count, loff_t *f_pos)
1339{
1340        u64 started_channels = debugfs_dma_base->pm.started_channels;
1341        int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
1342        int i;
1343        int ret = 0;
1344        char *dev_buf;
1345        char *tmp;
1346        int dev_size;
1347
1348        dev_buf = kmalloc(4*1024, GFP_KERNEL);
1349        if (dev_buf == NULL)
1350                goto err_kmalloc;
1351        tmp = dev_buf;
1352
1353        tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
1354
1355        for (i = 0; i < U300_DMA_CHANNELS; i++)
1356                if (started_channels & (1 << i))
1357                        tmp += sprintf(tmp, "channel %d\n", i);
1358
1359        tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
1360        dev_size = tmp  - dev_buf;
1361
1362        /* No more to read if offset != 0 */
1363        if (*f_pos > dev_size)
1364                goto out;
1365
1366        if (count > dev_size - *f_pos)
1367                count = dev_size - *f_pos;
1368
1369        if (copy_to_user(buf, dev_buf + *f_pos, count))
1370                ret = -EINVAL;
1371        ret = count;
1372        *f_pos += count;
1373
1374 out:
1375        kfree(dev_buf);
1376        return ret;
1377
1378 err_kmalloc:
1379        return 0;
1380}
1381
1382static const struct file_operations coh901318_debugfs_status_operations = {
1383        .owner          = THIS_MODULE,
1384        .open           = simple_open,
1385        .read           = coh901318_debugfs_read,
1386        .llseek         = default_llseek,
1387};
1388
1389
1390static int __init init_coh901318_debugfs(void)
1391{
1392
1393        dma_dentry = debugfs_create_dir("dma", NULL);
1394
1395        (void) debugfs_create_file("status",
1396                                   S_IFREG | S_IRUGO,
1397                                   dma_dentry, NULL,
1398                                   &coh901318_debugfs_status_operations);
1399        return 0;
1400}
1401
1402static void __exit exit_coh901318_debugfs(void)
1403{
1404        debugfs_remove_recursive(dma_dentry);
1405}
1406
1407module_init(init_coh901318_debugfs);
1408module_exit(exit_coh901318_debugfs);
1409#else
1410
1411#define COH901318_DEBUGFS_ASSIGN(x, y)
1412
1413#endif /* CONFIG_DEBUG_FS */
1414
1415static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
1416{
1417        return container_of(chan, struct coh901318_chan, chan);
1418}
1419
1420static inline const struct coh901318_params *
1421cohc_chan_param(struct coh901318_chan *cohc)
1422{
1423        return &chan_config[cohc->id].param;
1424}
1425
1426static inline const struct coh_dma_channel *
1427cohc_chan_conf(struct coh901318_chan *cohc)
1428{
1429        return &chan_config[cohc->id];
1430}
1431
1432static void enable_powersave(struct coh901318_chan *cohc)
1433{
1434        unsigned long flags;
1435        struct powersave *pm = &cohc->base->pm;
1436
1437        spin_lock_irqsave(&pm->lock, flags);
1438
1439        pm->started_channels &= ~(1ULL << cohc->id);
1440
1441        spin_unlock_irqrestore(&pm->lock, flags);
1442}
1443static void disable_powersave(struct coh901318_chan *cohc)
1444{
1445        unsigned long flags;
1446        struct powersave *pm = &cohc->base->pm;
1447
1448        spin_lock_irqsave(&pm->lock, flags);
1449
1450        pm->started_channels |= (1ULL << cohc->id);
1451
1452        spin_unlock_irqrestore(&pm->lock, flags);
1453}
1454
1455static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
1456{
1457        int channel = cohc->id;
1458        void __iomem *virtbase = cohc->base->virtbase;
1459
1460        writel(control,
1461               virtbase + COH901318_CX_CTRL +
1462               COH901318_CX_CTRL_SPACING * channel);
1463        return 0;
1464}
1465
1466static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
1467{
1468        int channel = cohc->id;
1469        void __iomem *virtbase = cohc->base->virtbase;
1470
1471        writel(conf,
1472               virtbase + COH901318_CX_CFG +
1473               COH901318_CX_CFG_SPACING*channel);
1474        return 0;
1475}
1476
1477
1478static int coh901318_start(struct coh901318_chan *cohc)
1479{
1480        u32 val;
1481        int channel = cohc->id;
1482        void __iomem *virtbase = cohc->base->virtbase;
1483
1484        disable_powersave(cohc);
1485
1486        val = readl(virtbase + COH901318_CX_CFG +
1487                    COH901318_CX_CFG_SPACING * channel);
1488
1489        /* Enable channel */
1490        val |= COH901318_CX_CFG_CH_ENABLE;
1491        writel(val, virtbase + COH901318_CX_CFG +
1492               COH901318_CX_CFG_SPACING * channel);
1493
1494        return 0;
1495}
1496
1497static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
1498                                      struct coh901318_lli *lli)
1499{
1500        int channel = cohc->id;
1501        void __iomem *virtbase = cohc->base->virtbase;
1502
1503        BUG_ON(readl(virtbase + COH901318_CX_STAT +
1504                     COH901318_CX_STAT_SPACING*channel) &
1505               COH901318_CX_STAT_ACTIVE);
1506
1507        writel(lli->src_addr,
1508               virtbase + COH901318_CX_SRC_ADDR +
1509               COH901318_CX_SRC_ADDR_SPACING * channel);
1510
1511        writel(lli->dst_addr, virtbase +
1512               COH901318_CX_DST_ADDR +
1513               COH901318_CX_DST_ADDR_SPACING * channel);
1514
1515        writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
1516               COH901318_CX_LNK_ADDR_SPACING * channel);
1517
1518        writel(lli->control, virtbase + COH901318_CX_CTRL +
1519               COH901318_CX_CTRL_SPACING * channel);
1520
1521        return 0;
1522}
1523
1524static struct coh901318_desc *
1525coh901318_desc_get(struct coh901318_chan *cohc)
1526{
1527        struct coh901318_desc *desc;
1528
1529        if (list_empty(&cohc->free)) {
1530                /* alloc new desc because we're out of used ones
1531                 * TODO: alloc a pile of descs instead of just one,
1532                 * avoid many small allocations.
1533                 */
1534                desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
1535                if (desc == NULL)
1536                        goto out;
1537                INIT_LIST_HEAD(&desc->node);
1538                dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
1539        } else {
1540                /* Reuse an old desc. */
1541                desc = list_first_entry(&cohc->free,
1542                                        struct coh901318_desc,
1543                                        node);
1544                list_del(&desc->node);
1545                /* Initialize it a bit so it's not insane */
1546                desc->sg = NULL;
1547                desc->sg_len = 0;
1548                desc->desc.callback = NULL;
1549                desc->desc.callback_param = NULL;
1550        }
1551
1552 out:
1553        return desc;
1554}
1555
1556static void
1557coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
1558{
1559        list_add_tail(&cohd->node, &cohc->free);
1560}
1561
1562/* call with irq lock held */
1563static void
1564coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
1565{
1566        list_add_tail(&desc->node, &cohc->active);
1567}
1568
1569static struct coh901318_desc *
1570coh901318_first_active_get(struct coh901318_chan *cohc)
1571{
1572        struct coh901318_desc *d;
1573
1574        if (list_empty(&cohc->active))
1575                return NULL;
1576
1577        d = list_first_entry(&cohc->active,
1578                             struct coh901318_desc,
1579                             node);
1580        return d;
1581}
1582
1583static void
1584coh901318_desc_remove(struct coh901318_desc *cohd)
1585{
1586        list_del(&cohd->node);
1587}
1588
1589static void
1590coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
1591{
1592        list_add_tail(&desc->node, &cohc->queue);
1593}
1594
1595static struct coh901318_desc *
1596coh901318_first_queued(struct coh901318_chan *cohc)
1597{
1598        struct coh901318_desc *d;
1599
1600        if (list_empty(&cohc->queue))
1601                return NULL;
1602
1603        d = list_first_entry(&cohc->queue,
1604                             struct coh901318_desc,
1605                             node);
1606        return d;
1607}
1608
1609static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
1610{
1611        struct coh901318_lli *lli = in_lli;
1612        u32 bytes = 0;
1613
1614        while (lli) {
1615                bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
1616                lli = lli->virt_link_addr;
1617        }
1618        return bytes;
1619}
1620
1621/*
1622 * Get the number of bytes left to transfer on this channel,
1623 * it is unwise to call this before stopping the channel for
1624 * absolute measures, but for a rough guess you can still call
1625 * it.
1626 */
1627static u32 coh901318_get_bytes_left(struct dma_chan *chan)
1628{
1629        struct coh901318_chan *cohc = to_coh901318_chan(chan);
1630        struct coh901318_desc *cohd;
1631        struct list_head *pos;
1632        unsigned long flags;
1633        u32 left = 0;
1634        int i = 0;
1635
1636        spin_lock_irqsave(&cohc->lock, flags);
1637
1638        /*
1639         * If there are many queued jobs, we iterate and add the
1640         * size of them all. We take a special look on the first
1641         * job though, since it is probably active.
1642         */
1643        list_for_each(pos, &cohc->active) {
1644                /*
1645                 * The first job in the list will be working on the
1646                 * hardware. The job can be stopped but still active,
1647                 * so that the transfer counter is somewhere inside
1648                 * the buffer.
1649                 */
1650                cohd = list_entry(pos, struct coh901318_desc, node);
1651
1652                if (i == 0) {
1653                        struct coh901318_lli *lli;
1654                        dma_addr_t ladd;
1655
1656                        /* Read current transfer count value */
1657                        left = readl(cohc->base->virtbase +
1658                                     COH901318_CX_CTRL +
1659                                     COH901318_CX_CTRL_SPACING * cohc->id) &
1660                                COH901318_CX_CTRL_TC_VALUE_MASK;
1661
1662                        /* See if the transfer is linked... */
1663                        ladd = readl(cohc->base->virtbase +
1664                                     COH901318_CX_LNK_ADDR +
1665                                     COH901318_CX_LNK_ADDR_SPACING *
1666                                     cohc->id) &
1667                                ~COH901318_CX_LNK_LINK_IMMEDIATE;
1668                        /* Single transaction */
1669                        if (!ladd)
1670                                continue;
1671
1672                        /*
1673                         * Linked transaction, follow the lli, find the
1674                         * currently processing lli, and proceed to the next
1675                         */
1676                        lli = cohd->lli;
1677                        while (lli && lli->link_addr != ladd)
1678                                lli = lli->virt_link_addr;
1679
1680                        if (lli)
1681                                lli = lli->virt_link_addr;
1682
1683                        /*
1684                         * Follow remaining lli links around to count the total
1685                         * number of bytes left
1686                         */
1687                        left += coh901318_get_bytes_in_lli(lli);
1688                } else {
1689                        left += coh901318_get_bytes_in_lli(cohd->lli);
1690                }
1691                i++;
1692        }
1693
1694        /* Also count bytes in the queued jobs */
1695        list_for_each(pos, &cohc->queue) {
1696                cohd = list_entry(pos, struct coh901318_desc, node);
1697                left += coh901318_get_bytes_in_lli(cohd->lli);
1698        }
1699
1700        spin_unlock_irqrestore(&cohc->lock, flags);
1701
1702        return left;
1703}
1704
1705/*
1706 * Pauses a transfer without losing data. Enables power save.
1707 * Use this function in conjunction with coh901318_resume.
1708 */
1709static void coh901318_pause(struct dma_chan *chan)
1710{
1711        u32 val;
1712        unsigned long flags;
1713        struct coh901318_chan *cohc = to_coh901318_chan(chan);
1714        int channel = cohc->id;
1715        void __iomem *virtbase = cohc->base->virtbase;
1716
1717        spin_lock_irqsave(&cohc->lock, flags);
1718
1719        /* Disable channel in HW */
1720        val = readl(virtbase + COH901318_CX_CFG +
1721                    COH901318_CX_CFG_SPACING * channel);
1722
1723        /* Stopping infinite transfer */
1724        if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
1725            (val & COH901318_CX_CFG_CH_ENABLE))
1726                cohc->stopped = 1;
1727
1728
1729        val &= ~COH901318_CX_CFG_CH_ENABLE;
1730        /* Enable twice, HW bug work around */
1731        writel(val, virtbase + COH901318_CX_CFG +
1732               COH901318_CX_CFG_SPACING * channel);
1733        writel(val, virtbase + COH901318_CX_CFG +
1734               COH901318_CX_CFG_SPACING * channel);
1735
1736        /* Spin-wait for it to actually go inactive */
1737        while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
1738                     channel) & COH901318_CX_STAT_ACTIVE)
1739                cpu_relax();
1740
1741        /* Check if we stopped an active job */
1742        if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
1743                   channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
1744                cohc->stopped = 1;
1745
1746        enable_powersave(cohc);
1747
1748        spin_unlock_irqrestore(&cohc->lock, flags);
1749}
1750
1751/* Resumes a transfer that has been stopped via 300_dma_stop(..).
1752   Power save is handled.
1753*/
1754static void coh901318_resume(struct dma_chan *chan)
1755{
1756        u32 val;
1757        unsigned long flags;
1758        struct coh901318_chan *cohc = to_coh901318_chan(chan);
1759        int channel = cohc->id;
1760
1761        spin_lock_irqsave(&cohc->lock, flags);
1762
1763        disable_powersave(cohc);
1764
1765        if (cohc->stopped) {
1766                /* Enable channel in HW */
1767                val = readl(cohc->base->virtbase + COH901318_CX_CFG +
1768                            COH901318_CX_CFG_SPACING * channel);
1769
1770                val |= COH901318_CX_CFG_CH_ENABLE;
1771
1772                writel(val, cohc->base->virtbase + COH901318_CX_CFG +
1773                       COH901318_CX_CFG_SPACING*channel);
1774
1775                cohc->stopped = 0;
1776        }
1777
1778        spin_unlock_irqrestore(&cohc->lock, flags);
1779}
1780
1781bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
1782{
1783        unsigned int ch_nr = (unsigned int) chan_id;
1784
1785        if (ch_nr == to_coh901318_chan(chan)->id)
1786                return true;
1787
1788        return false;
1789}
1790EXPORT_SYMBOL(coh901318_filter_id);
1791
1792struct coh901318_filter_args {
1793        struct coh901318_base *base;
1794        unsigned int ch_nr;
1795};
1796
1797static bool coh901318_filter_base_and_id(struct dma_chan *chan, void *data)
1798{
1799        struct coh901318_filter_args *args = data;
1800
1801        if (&args->base->dma_slave == chan->device &&
1802            args->ch_nr == to_coh901318_chan(chan)->id)
1803                return true;
1804
1805        return false;
1806}
1807
1808static struct dma_chan *coh901318_xlate(struct of_phandle_args *dma_spec,
1809                                        struct of_dma *ofdma)
1810{
1811        struct coh901318_filter_args args = {
1812                .base = ofdma->of_dma_data,
1813                .ch_nr = dma_spec->args[0],
1814        };
1815        dma_cap_mask_t cap;
1816        dma_cap_zero(cap);
1817        dma_cap_set(DMA_SLAVE, cap);
1818
1819        return dma_request_channel(cap, coh901318_filter_base_and_id, &args);
1820}
1821/*
1822 * DMA channel allocation
1823 */
1824static int coh901318_config(struct coh901318_chan *cohc,
1825                            struct coh901318_params *param)
1826{
1827        unsigned long flags;
1828        const struct coh901318_params *p;
1829        int channel = cohc->id;
1830        void __iomem *virtbase = cohc->base->virtbase;
1831
1832        spin_lock_irqsave(&cohc->lock, flags);
1833
1834        if (param)
1835                p = param;
1836        else
1837                p = cohc_chan_param(cohc);
1838
1839        /* Clear any pending BE or TC interrupt */
1840        if (channel < 32) {
1841                writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
1842                writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
1843        } else {
1844                writel(1 << (channel - 32), virtbase +
1845                       COH901318_BE_INT_CLEAR2);
1846                writel(1 << (channel - 32), virtbase +
1847                       COH901318_TC_INT_CLEAR2);
1848        }
1849
1850        coh901318_set_conf(cohc, p->config);
1851        coh901318_set_ctrl(cohc, p->ctrl_lli_last);
1852
1853        spin_unlock_irqrestore(&cohc->lock, flags);
1854
1855        return 0;
1856}
1857
1858/* must lock when calling this function
1859 * start queued jobs, if any
1860 * TODO: start all queued jobs in one go
1861 *
1862 * Returns descriptor if queued job is started otherwise NULL.
1863 * If the queue is empty NULL is returned.
1864 */
1865static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
1866{
1867        struct coh901318_desc *cohd;
1868
1869        /*
1870         * start queued jobs, if any
1871         * TODO: transmit all queued jobs in one go
1872         */
1873        cohd = coh901318_first_queued(cohc);
1874
1875        if (cohd != NULL) {
1876                /* Remove from queue */
1877                coh901318_desc_remove(cohd);
1878                /* initiate DMA job */
1879                cohc->busy = 1;
1880
1881                coh901318_desc_submit(cohc, cohd);
1882
1883                /* Program the transaction head */
1884                coh901318_set_conf(cohc, cohd->head_config);
1885                coh901318_set_ctrl(cohc, cohd->head_ctrl);
1886                coh901318_prep_linked_list(cohc, cohd->lli);
1887
1888                /* start dma job on this channel */
1889                coh901318_start(cohc);
1890
1891        }
1892
1893        return cohd;
1894}
1895
1896/*
1897 * This tasklet is called from the interrupt handler to
1898 * handle each descriptor (DMA job) that is sent to a channel.
1899 */
1900static void dma_tasklet(unsigned long data)
1901{
1902        struct coh901318_chan *cohc = (struct coh901318_chan *) data;
1903        struct coh901318_desc *cohd_fin;
1904        unsigned long flags;
1905        dma_async_tx_callback callback;
1906        void *callback_param;
1907
1908        dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
1909                 " nbr_active_done %ld\n", __func__,
1910                 cohc->id, cohc->nbr_active_done);
1911
1912        spin_lock_irqsave(&cohc->lock, flags);
1913
1914        /* get first active descriptor entry from list */
1915        cohd_fin = coh901318_first_active_get(cohc);
1916
1917        if (cohd_fin == NULL)
1918                goto err;
1919
1920        /* locate callback to client */
1921        callback = cohd_fin->desc.callback;
1922        callback_param = cohd_fin->desc.callback_param;
1923
1924        /* sign this job as completed on the channel */
1925        dma_cookie_complete(&cohd_fin->desc);
1926
1927        /* release the lli allocation and remove the descriptor */
1928        coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
1929
1930        /* return desc to free-list */
1931        coh901318_desc_remove(cohd_fin);
1932        coh901318_desc_free(cohc, cohd_fin);
1933
1934        spin_unlock_irqrestore(&cohc->lock, flags);
1935
1936        /* Call the callback when we're done */
1937        if (callback)
1938                callback(callback_param);
1939
1940        spin_lock_irqsave(&cohc->lock, flags);
1941
1942        /*
1943         * If another interrupt fired while the tasklet was scheduling,
1944         * we don't get called twice, so we have this number of active
1945         * counter that keep track of the number of IRQs expected to
1946         * be handled for this channel. If there happen to be more than
1947         * one IRQ to be ack:ed, we simply schedule this tasklet again.
1948         */
1949        cohc->nbr_active_done--;
1950        if (cohc->nbr_active_done) {
1951                dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
1952                        "came in while we were scheduling this tasklet\n");
1953                if (cohc_chan_conf(cohc)->priority_high)
1954                        tasklet_hi_schedule(&cohc->tasklet);
1955                else
1956                        tasklet_schedule(&cohc->tasklet);
1957        }
1958
1959        spin_unlock_irqrestore(&cohc->lock, flags);
1960
1961        return;
1962
1963 err:
1964        spin_unlock_irqrestore(&cohc->lock, flags);
1965        dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
1966}
1967
1968
1969/* called from interrupt context */
1970static void dma_tc_handle(struct coh901318_chan *cohc)
1971{
1972        /*
1973         * If the channel is not allocated, then we shouldn't have
1974         * any TC interrupts on it.
1975         */
1976        if (!cohc->allocated) {
1977                dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
1978                        "unallocated channel\n");
1979                return;
1980        }
1981
1982        spin_lock(&cohc->lock);
1983
1984        /*
1985         * When we reach this point, at least one queue item
1986         * should have been moved over from cohc->queue to
1987         * cohc->active and run to completion, that is why we're
1988         * getting a terminal count interrupt is it not?
1989         * If you get this BUG() the most probable cause is that
1990         * the individual nodes in the lli chain have IRQ enabled,
1991         * so check your platform config for lli chain ctrl.
1992         */
1993        BUG_ON(list_empty(&cohc->active));
1994
1995        cohc->nbr_active_done++;
1996
1997        /*
1998         * This attempt to take a job from cohc->queue, put it
1999         * into cohc->active and start it.
2000         */
2001        if (coh901318_queue_start(cohc) == NULL)
2002                cohc->busy = 0;
2003
2004        spin_unlock(&cohc->lock);
2005
2006        /*
2007         * This tasklet will remove items from cohc->active
2008         * and thus terminates them.
2009         */
2010        if (cohc_chan_conf(cohc)->priority_high)
2011                tasklet_hi_schedule(&cohc->tasklet);
2012        else
2013                tasklet_schedule(&cohc->tasklet);
2014}
2015
2016
2017static irqreturn_t dma_irq_handler(int irq, void *dev_id)
2018{
2019        u32 status1;
2020        u32 status2;
2021        int i;
2022        int ch;
2023        struct coh901318_base *base  = dev_id;
2024        struct coh901318_chan *cohc;
2025        void __iomem *virtbase = base->virtbase;
2026
2027        status1 = readl(virtbase + COH901318_INT_STATUS1);
2028        status2 = readl(virtbase + COH901318_INT_STATUS2);
2029
2030        if (unlikely(status1 == 0 && status2 == 0)) {
2031                dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
2032                return IRQ_HANDLED;
2033        }
2034
2035        /* TODO: consider handle IRQ in tasklet here to
2036         *       minimize interrupt latency */
2037
2038        /* Check the first 32 DMA channels for IRQ */
2039        while (status1) {
2040                /* Find first bit set, return as a number. */
2041                i = ffs(status1) - 1;
2042                ch = i;
2043
2044                cohc = &base->chans[ch];
2045                spin_lock(&cohc->lock);
2046
2047                /* Mask off this bit */
2048                status1 &= ~(1 << i);
2049                /* Check the individual channel bits */
2050                if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
2051                        dev_crit(COHC_2_DEV(cohc),
2052                                 "DMA bus error on channel %d!\n", ch);
2053                        BUG_ON(1);
2054                        /* Clear BE interrupt */
2055                        __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
2056                } else {
2057                        /* Caused by TC, really? */
2058                        if (unlikely(!test_bit(i, virtbase +
2059                                               COH901318_TC_INT_STATUS1))) {
2060                                dev_warn(COHC_2_DEV(cohc),
2061                                         "ignoring interrupt not caused by terminal count on channel %d\n", ch);
2062                                /* Clear TC interrupt */
2063                                BUG_ON(1);
2064                                __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
2065                        } else {
2066                                /* Enable powersave if transfer has finished */
2067                                if (!(readl(virtbase + COH901318_CX_STAT +
2068                                            COH901318_CX_STAT_SPACING*ch) &
2069                                      COH901318_CX_STAT_ENABLED)) {
2070                                        enable_powersave(cohc);
2071                                }
2072
2073                                /* Must clear TC interrupt before calling
2074                                 * dma_tc_handle
2075                                 * in case tc_handle initiate a new dma job
2076                                 */
2077                                __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
2078
2079                                dma_tc_handle(cohc);
2080                        }
2081                }
2082                spin_unlock(&cohc->lock);
2083        }
2084
2085        /* Check the remaining 32 DMA channels for IRQ */
2086        while (status2) {
2087                /* Find first bit set, return as a number. */
2088                i = ffs(status2) - 1;
2089                ch = i + 32;
2090                cohc = &base->chans[ch];
2091                spin_lock(&cohc->lock);
2092
2093                /* Mask off this bit */
2094                status2 &= ~(1 << i);
2095                /* Check the individual channel bits */
2096                if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
2097                        dev_crit(COHC_2_DEV(cohc),
2098                                 "DMA bus error on channel %d!\n", ch);
2099                        /* Clear BE interrupt */
2100                        BUG_ON(1);
2101                        __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
2102                } else {
2103                        /* Caused by TC, really? */
2104                        if (unlikely(!test_bit(i, virtbase +
2105                                               COH901318_TC_INT_STATUS2))) {
2106                                dev_warn(COHC_2_DEV(cohc),
2107                                         "ignoring interrupt not caused by terminal count on channel %d\n", ch);
2108                                /* Clear TC interrupt */
2109                                __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
2110                                BUG_ON(1);
2111                        } else {
2112                                /* Enable powersave if transfer has finished */
2113                                if (!(readl(virtbase + COH901318_CX_STAT +
2114                                            COH901318_CX_STAT_SPACING*ch) &
2115                                      COH901318_CX_STAT_ENABLED)) {
2116                                        enable_powersave(cohc);
2117                                }
2118                                /* Must clear TC interrupt before calling
2119                                 * dma_tc_handle
2120                                 * in case tc_handle initiate a new dma job
2121                                 */
2122                                __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
2123
2124                                dma_tc_handle(cohc);
2125                        }
2126                }
2127                spin_unlock(&cohc->lock);
2128        }
2129
2130        return IRQ_HANDLED;
2131}
2132
2133static int coh901318_alloc_chan_resources(struct dma_chan *chan)
2134{
2135        struct coh901318_chan   *cohc = to_coh901318_chan(chan);
2136        unsigned long flags;
2137
2138        dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
2139                 __func__, cohc->id);
2140
2141        if (chan->client_count > 1)
2142                return -EBUSY;
2143
2144        spin_lock_irqsave(&cohc->lock, flags);
2145
2146        coh901318_config(cohc, NULL);
2147
2148        cohc->allocated = 1;
2149        dma_cookie_init(chan);
2150
2151        spin_unlock_irqrestore(&cohc->lock, flags);
2152
2153        return 1;
2154}
2155
2156static void
2157coh901318_free_chan_resources(struct dma_chan *chan)
2158{
2159        struct coh901318_chan   *cohc = to_coh901318_chan(chan);
2160        int channel = cohc->id;
2161        unsigned long flags;
2162
2163        spin_lock_irqsave(&cohc->lock, flags);
2164
2165        /* Disable HW */
2166        writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
2167               COH901318_CX_CFG_SPACING*channel);
2168        writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
2169               COH901318_CX_CTRL_SPACING*channel);
2170
2171        cohc->allocated = 0;
2172
2173        spin_unlock_irqrestore(&cohc->lock, flags);
2174
2175        chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
2176}
2177
2178
2179static dma_cookie_t
2180coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
2181{
2182        struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
2183                                                   desc);
2184        struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
2185        unsigned long flags;
2186        dma_cookie_t cookie;
2187
2188        spin_lock_irqsave(&cohc->lock, flags);
2189        cookie = dma_cookie_assign(tx);
2190
2191        coh901318_desc_queue(cohc, cohd);
2192
2193        spin_unlock_irqrestore(&cohc->lock, flags);
2194
2195        return cookie;
2196}
2197
2198static struct dma_async_tx_descriptor *
2199coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
2200                      size_t size, unsigned long flags)
2201{
2202        struct coh901318_lli *lli;
2203        struct coh901318_desc *cohd;
2204        unsigned long flg;
2205        struct coh901318_chan *cohc = to_coh901318_chan(chan);
2206        int lli_len;
2207        u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
2208        int ret;
2209
2210        spin_lock_irqsave(&cohc->lock, flg);
2211
2212        dev_vdbg(COHC_2_DEV(cohc),
2213                 "[%s] channel %d src 0x%x dest 0x%x size %d\n",
2214                 __func__, cohc->id, src, dest, size);
2215
2216        if (flags & DMA_PREP_INTERRUPT)
2217                /* Trigger interrupt after last lli */
2218                ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
2219
2220        lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
2221        if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
2222                lli_len++;
2223
2224        lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
2225
2226        if (lli == NULL)
2227                goto err;
2228
2229        ret = coh901318_lli_fill_memcpy(
2230                &cohc->base->pool, lli, src, size, dest,
2231                cohc_chan_param(cohc)->ctrl_lli_chained,
2232                ctrl_last);
2233        if (ret)
2234                goto err;
2235
2236        COH_DBG(coh901318_list_print(cohc, lli));
2237
2238        /* Pick a descriptor to handle this transfer */
2239        cohd = coh901318_desc_get(cohc);
2240        cohd->lli = lli;
2241        cohd->flags = flags;
2242        cohd->desc.tx_submit = coh901318_tx_submit;
2243
2244        spin_unlock_irqrestore(&cohc->lock, flg);
2245
2246        return &cohd->desc;
2247 err:
2248        spin_unlock_irqrestore(&cohc->lock, flg);
2249        return NULL;
2250}
2251
2252static struct dma_async_tx_descriptor *
2253coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2254                        unsigned int sg_len, enum dma_transfer_direction direction,
2255                        unsigned long flags, void *context)
2256{
2257        struct coh901318_chan *cohc = to_coh901318_chan(chan);
2258        struct coh901318_lli *lli;
2259        struct coh901318_desc *cohd;
2260        const struct coh901318_params *params;
2261        struct scatterlist *sg;
2262        int len = 0;
2263        int size;
2264        int i;
2265        u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
2266        u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
2267        u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
2268        u32 config;
2269        unsigned long flg;
2270        int ret;
2271
2272        if (!sgl)
2273                goto out;
2274        if (sg_dma_len(sgl) == 0)
2275                goto out;
2276
2277        spin_lock_irqsave(&cohc->lock, flg);
2278
2279        dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
2280                 __func__, sg_len, direction);
2281
2282        if (flags & DMA_PREP_INTERRUPT)
2283                /* Trigger interrupt after last lli */
2284                ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
2285
2286        params = cohc_chan_param(cohc);
2287        config = params->config;
2288        /*
2289         * Add runtime-specific control on top, make
2290         * sure the bits you set per peripheral channel are
2291         * cleared in the default config from the platform.
2292         */
2293        ctrl_chained |= cohc->ctrl;
2294        ctrl_last |= cohc->ctrl;
2295        ctrl |= cohc->ctrl;
2296
2297        if (direction == DMA_MEM_TO_DEV) {
2298                u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
2299                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
2300
2301                config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
2302                ctrl_chained |= tx_flags;
2303                ctrl_last |= tx_flags;
2304                ctrl |= tx_flags;
2305        } else if (direction == DMA_DEV_TO_MEM) {
2306                u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
2307                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
2308
2309                config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
2310                ctrl_chained |= rx_flags;
2311                ctrl_last |= rx_flags;
2312                ctrl |= rx_flags;
2313        } else
2314                goto err_direction;
2315
2316        /* The dma only supports transmitting packages up to
2317         * MAX_DMA_PACKET_SIZE. Calculate to total number of
2318         * dma elemts required to send the entire sg list
2319         */
2320        for_each_sg(sgl, sg, sg_len, i) {
2321                unsigned int factor;
2322                size = sg_dma_len(sg);
2323
2324                if (size <= MAX_DMA_PACKET_SIZE) {
2325                        len++;
2326                        continue;
2327                }
2328
2329                factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
2330                if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
2331                        factor++;
2332
2333                len += factor;
2334        }
2335
2336        pr_debug("Allocate %d lli:s for this transfer\n", len);
2337        lli = coh901318_lli_alloc(&cohc->base->pool, len);
2338
2339        if (lli == NULL)
2340                goto err_dma_alloc;
2341
2342        /* initiate allocated lli list */
2343        ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
2344                                    cohc->addr,
2345                                    ctrl_chained,
2346                                    ctrl,
2347                                    ctrl_last,
2348                                    direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
2349        if (ret)
2350                goto err_lli_fill;
2351
2352
2353        COH_DBG(coh901318_list_print(cohc, lli));
2354
2355        /* Pick a descriptor to handle this transfer */
2356        cohd = coh901318_desc_get(cohc);
2357        cohd->head_config = config;
2358        /*
2359         * Set the default head ctrl for the channel to the one from the
2360         * lli, things may have changed due to odd buffer alignment
2361         * etc.
2362         */
2363        cohd->head_ctrl = lli->control;
2364        cohd->dir = direction;
2365        cohd->flags = flags;
2366        cohd->desc.tx_submit = coh901318_tx_submit;
2367        cohd->lli = lli;
2368
2369        spin_unlock_irqrestore(&cohc->lock, flg);
2370
2371        return &cohd->desc;
2372 err_lli_fill:
2373 err_dma_alloc:
2374 err_direction:
2375        spin_unlock_irqrestore(&cohc->lock, flg);
2376 out:
2377        return NULL;
2378}
2379
2380static enum dma_status
2381coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2382                 struct dma_tx_state *txstate)
2383{
2384        struct coh901318_chan *cohc = to_coh901318_chan(chan);
2385        enum dma_status ret;
2386
2387        ret = dma_cookie_status(chan, cookie, txstate);
2388        if (ret == DMA_SUCCESS)
2389                return ret;
2390
2391        dma_set_residue(txstate, coh901318_get_bytes_left(chan));
2392
2393        if (ret == DMA_IN_PROGRESS && cohc->stopped)
2394                ret = DMA_PAUSED;
2395
2396        return ret;
2397}
2398
2399static void
2400coh901318_issue_pending(struct dma_chan *chan)
2401{
2402        struct coh901318_chan *cohc = to_coh901318_chan(chan);
2403        unsigned long flags;
2404
2405        spin_lock_irqsave(&cohc->lock, flags);
2406
2407        /*
2408         * Busy means that pending jobs are already being processed,
2409         * and then there is no point in starting the queue: the
2410         * terminal count interrupt on the channel will take the next
2411         * job on the queue and execute it anyway.
2412         */
2413        if (!cohc->busy)
2414                coh901318_queue_start(cohc);
2415
2416        spin_unlock_irqrestore(&cohc->lock, flags);
2417}
2418
2419/*
2420 * Here we wrap in the runtime dma control interface
2421 */
2422struct burst_table {
2423        int burst_8bit;
2424        int burst_16bit;
2425        int burst_32bit;
2426        u32 reg;
2427};
2428
2429static const struct burst_table burst_sizes[] = {
2430        {
2431                .burst_8bit = 64,
2432                .burst_16bit = 32,
2433                .burst_32bit = 16,
2434                .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
2435        },
2436        {
2437                .burst_8bit = 48,
2438                .burst_16bit = 24,
2439                .burst_32bit = 12,
2440                .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
2441        },
2442        {
2443                .burst_8bit = 32,
2444                .burst_16bit = 16,
2445                .burst_32bit = 8,
2446                .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
2447        },
2448        {
2449                .burst_8bit = 16,
2450                .burst_16bit = 8,
2451                .burst_32bit = 4,
2452                .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
2453        },
2454        {
2455                .burst_8bit = 8,
2456                .burst_16bit = 4,
2457                .burst_32bit = 2,
2458                .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
2459        },
2460        {
2461                .burst_8bit = 4,
2462                .burst_16bit = 2,
2463                .burst_32bit = 1,
2464                .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
2465        },
2466        {
2467                .burst_8bit = 2,
2468                .burst_16bit = 1,
2469                .burst_32bit = 0,
2470                .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
2471        },
2472        {
2473                .burst_8bit = 1,
2474                .burst_16bit = 0,
2475                .burst_32bit = 0,
2476                .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
2477        },
2478};
2479
2480static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
2481                        struct dma_slave_config *config)
2482{
2483        struct coh901318_chan *cohc = to_coh901318_chan(chan);
2484        dma_addr_t addr;
2485        enum dma_slave_buswidth addr_width;
2486        u32 maxburst;
2487        u32 ctrl = 0;
2488        int i = 0;
2489
2490        /* We only support mem to per or per to mem transfers */
2491        if (config->direction == DMA_DEV_TO_MEM) {
2492                addr = config->src_addr;
2493                addr_width = config->src_addr_width;
2494                maxburst = config->src_maxburst;
2495        } else if (config->direction == DMA_MEM_TO_DEV) {
2496                addr = config->dst_addr;
2497                addr_width = config->dst_addr_width;
2498                maxburst = config->dst_maxburst;
2499        } else {
2500                dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
2501                return;
2502        }
2503
2504        dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
2505                addr_width);
2506        switch (addr_width)  {
2507        case DMA_SLAVE_BUSWIDTH_1_BYTE:
2508                ctrl |=
2509                        COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
2510                        COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
2511
2512                while (i < ARRAY_SIZE(burst_sizes)) {
2513                        if (burst_sizes[i].burst_8bit <= maxburst)
2514                                break;
2515                        i++;
2516                }
2517
2518                break;
2519        case DMA_SLAVE_BUSWIDTH_2_BYTES:
2520                ctrl |=
2521                        COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
2522                        COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
2523
2524                while (i < ARRAY_SIZE(burst_sizes)) {
2525                        if (burst_sizes[i].burst_16bit <= maxburst)
2526                                break;
2527                        i++;
2528                }
2529
2530                break;
2531        case DMA_SLAVE_BUSWIDTH_4_BYTES:
2532                /* Direction doesn't matter here, it's 32/32 bits */
2533                ctrl |=
2534                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
2535                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
2536
2537                while (i < ARRAY_SIZE(burst_sizes)) {
2538                        if (burst_sizes[i].burst_32bit <= maxburst)
2539                                break;
2540                        i++;
2541                }
2542
2543                break;
2544        default:
2545                dev_err(COHC_2_DEV(cohc),
2546                        "bad runtimeconfig: alien address width\n");
2547                return;
2548        }
2549
2550        ctrl |= burst_sizes[i].reg;
2551        dev_dbg(COHC_2_DEV(cohc),
2552                "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
2553                burst_sizes[i].burst_8bit, addr_width, maxburst);
2554
2555        cohc->addr = addr;
2556        cohc->ctrl = ctrl;
2557}
2558
2559static int
2560coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2561                  unsigned long arg)
2562{
2563        unsigned long flags;
2564        struct coh901318_chan *cohc = to_coh901318_chan(chan);
2565        struct coh901318_desc *cohd;
2566        void __iomem *virtbase = cohc->base->virtbase;
2567
2568        if (cmd == DMA_SLAVE_CONFIG) {
2569                struct dma_slave_config *config =
2570                        (struct dma_slave_config *) arg;
2571
2572                coh901318_dma_set_runtimeconfig(chan, config);
2573                return 0;
2574          }
2575
2576        if (cmd == DMA_PAUSE) {
2577                coh901318_pause(chan);
2578                return 0;
2579        }
2580
2581        if (cmd == DMA_RESUME) {
2582                coh901318_resume(chan);
2583                return 0;
2584        }
2585
2586        if (cmd != DMA_TERMINATE_ALL)
2587                return -ENXIO;
2588
2589        /* The remainder of this function terminates the transfer */
2590        coh901318_pause(chan);
2591        spin_lock_irqsave(&cohc->lock, flags);
2592
2593        /* Clear any pending BE or TC interrupt */
2594        if (cohc->id < 32) {
2595                writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
2596                writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
2597        } else {
2598                writel(1 << (cohc->id - 32), virtbase +
2599                       COH901318_BE_INT_CLEAR2);
2600                writel(1 << (cohc->id - 32), virtbase +
2601                       COH901318_TC_INT_CLEAR2);
2602        }
2603
2604        enable_powersave(cohc);
2605
2606        while ((cohd = coh901318_first_active_get(cohc))) {
2607                /* release the lli allocation*/
2608                coh901318_lli_free(&cohc->base->pool, &cohd->lli);
2609
2610                /* return desc to free-list */
2611                coh901318_desc_remove(cohd);
2612                coh901318_desc_free(cohc, cohd);
2613        }
2614
2615        while ((cohd = coh901318_first_queued(cohc))) {
2616                /* release the lli allocation*/
2617                coh901318_lli_free(&cohc->base->pool, &cohd->lli);
2618
2619                /* return desc to free-list */
2620                coh901318_desc_remove(cohd);
2621                coh901318_desc_free(cohc, cohd);
2622        }
2623
2624
2625        cohc->nbr_active_done = 0;
2626        cohc->busy = 0;
2627
2628        spin_unlock_irqrestore(&cohc->lock, flags);
2629
2630        return 0;
2631}
2632
2633void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
2634                         struct coh901318_base *base)
2635{
2636        int chans_i;
2637        int i = 0;
2638        struct coh901318_chan *cohc;
2639
2640        INIT_LIST_HEAD(&dma->channels);
2641
2642        for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
2643                for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
2644                        cohc = &base->chans[i];
2645
2646                        cohc->base = base;
2647                        cohc->chan.device = dma;
2648                        cohc->id = i;
2649
2650                        /* TODO: do we really need this lock if only one
2651                         * client is connected to each channel?
2652                         */
2653
2654                        spin_lock_init(&cohc->lock);
2655
2656                        cohc->nbr_active_done = 0;
2657                        cohc->busy = 0;
2658                        INIT_LIST_HEAD(&cohc->free);
2659                        INIT_LIST_HEAD(&cohc->active);
2660                        INIT_LIST_HEAD(&cohc->queue);
2661
2662                        tasklet_init(&cohc->tasklet, dma_tasklet,
2663                                     (unsigned long) cohc);
2664
2665                        list_add_tail(&cohc->chan.device_node,
2666                                      &dma->channels);
2667                }
2668        }
2669}
2670
2671static int __init coh901318_probe(struct platform_device *pdev)
2672{
2673        int err = 0;
2674        struct coh901318_base *base;
2675        int irq;
2676        struct resource *io;
2677
2678        io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2679        if (!io)
2680                return -ENODEV;
2681
2682        /* Map DMA controller registers to virtual memory */
2683        if (devm_request_mem_region(&pdev->dev,
2684                                    io->start,
2685                                    resource_size(io),
2686                                    pdev->dev.driver->name) == NULL)
2687                return -ENOMEM;
2688
2689        base = devm_kzalloc(&pdev->dev,
2690                            ALIGN(sizeof(struct coh901318_base), 4) +
2691                            U300_DMA_CHANNELS *
2692                            sizeof(struct coh901318_chan),
2693                            GFP_KERNEL);
2694        if (!base)
2695                return -ENOMEM;
2696
2697        base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
2698
2699        base->virtbase = devm_ioremap(&pdev->dev, io->start, resource_size(io));
2700        if (!base->virtbase)
2701                return -ENOMEM;
2702
2703        base->dev = &pdev->dev;
2704        spin_lock_init(&base->pm.lock);
2705        base->pm.started_channels = 0;
2706
2707        COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
2708
2709        irq = platform_get_irq(pdev, 0);
2710        if (irq < 0)
2711                return irq;
2712
2713        err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, IRQF_DISABLED,
2714                               "coh901318", base);
2715        if (err)
2716                return err;
2717
2718        err = coh901318_pool_create(&base->pool, &pdev->dev,
2719                                    sizeof(struct coh901318_lli),
2720                                    32);
2721        if (err)
2722                return err;
2723
2724        /* init channels for device transfers */
2725        coh901318_base_init(&base->dma_slave, dma_slave_channels,
2726                            base);
2727
2728        dma_cap_zero(base->dma_slave.cap_mask);
2729        dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2730
2731        base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
2732        base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
2733        base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
2734        base->dma_slave.device_tx_status = coh901318_tx_status;
2735        base->dma_slave.device_issue_pending = coh901318_issue_pending;
2736        base->dma_slave.device_control = coh901318_control;
2737        base->dma_slave.dev = &pdev->dev;
2738
2739        err = dma_async_device_register(&base->dma_slave);
2740
2741        if (err)
2742                goto err_register_slave;
2743
2744        /* init channels for memcpy */
2745        coh901318_base_init(&base->dma_memcpy, dma_memcpy_channels,
2746                            base);
2747
2748        dma_cap_zero(base->dma_memcpy.cap_mask);
2749        dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2750
2751        base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
2752        base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
2753        base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
2754        base->dma_memcpy.device_tx_status = coh901318_tx_status;
2755        base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
2756        base->dma_memcpy.device_control = coh901318_control;
2757        base->dma_memcpy.dev = &pdev->dev;
2758        /*
2759         * This controller can only access address at even 32bit boundaries,
2760         * i.e. 2^2
2761         */
2762        base->dma_memcpy.copy_align = 2;
2763        err = dma_async_device_register(&base->dma_memcpy);
2764
2765        if (err)
2766                goto err_register_memcpy;
2767
2768        err = of_dma_controller_register(pdev->dev.of_node, coh901318_xlate,
2769                                         base);
2770        if (err)
2771                goto err_register_of_dma;
2772
2773        platform_set_drvdata(pdev, base);
2774        dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
2775                (u32) base->virtbase);
2776
2777        return err;
2778
2779 err_register_of_dma:
2780        dma_async_device_unregister(&base->dma_memcpy);
2781 err_register_memcpy:
2782        dma_async_device_unregister(&base->dma_slave);
2783 err_register_slave:
2784        coh901318_pool_destroy(&base->pool);
2785        return err;
2786}
2787
2788static int coh901318_remove(struct platform_device *pdev)
2789{
2790        struct coh901318_base *base = platform_get_drvdata(pdev);
2791
2792        of_dma_controller_free(pdev->dev.of_node);
2793        dma_async_device_unregister(&base->dma_memcpy);
2794        dma_async_device_unregister(&base->dma_slave);
2795        coh901318_pool_destroy(&base->pool);
2796        return 0;
2797}
2798
2799static const struct of_device_id coh901318_dt_match[] = {
2800        { .compatible = "stericsson,coh901318" },
2801        {},
2802};
2803
2804static struct platform_driver coh901318_driver = {
2805        .remove = coh901318_remove,
2806        .driver = {
2807                .name   = "coh901318",
2808                .of_match_table = coh901318_dt_match,
2809        },
2810};
2811
2812int __init coh901318_init(void)
2813{
2814        return platform_driver_probe(&coh901318_driver, coh901318_probe);
2815}
2816subsys_initcall(coh901318_init);
2817
2818void __exit coh901318_exit(void)
2819{
2820        platform_driver_unregister(&coh901318_driver);
2821}
2822module_exit(coh901318_exit);
2823
2824MODULE_LICENSE("GPL");
2825MODULE_AUTHOR("Per Friden");
2826
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